LLVM 19.0.0git
PPCFastISel.cpp
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1//===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the PowerPC-specific support for the FastISel class. Some
10// of the target-specific code is generated by tablegen in the file
11// PPCGenFastISel.inc, which is #included here.
12//
13//===----------------------------------------------------------------------===//
14
16#include "PPC.h"
17#include "PPCCCState.h"
18#include "PPCCallingConv.h"
19#include "PPCISelLowering.h"
21#include "PPCSubtarget.h"
22#include "PPCTargetMachine.h"
31#include "llvm/IR/CallingConv.h"
33#include "llvm/IR/GlobalAlias.h"
36#include "llvm/IR/Operator.h"
37#include "llvm/Support/Debug.h"
39
40//===----------------------------------------------------------------------===//
41//
42// TBD:
43// fastLowerArguments: Handle simple cases.
44// PPCMaterializeGV: Handle TLS.
45// SelectCall: Handle function pointers.
46// SelectCall: Handle multi-register return values.
47// SelectCall: Optimize away nops for local calls.
48// processCallArgs: Handle bit-converted arguments.
49// finishCall: Handle multi-register return values.
50// PPCComputeAddress: Handle parameter references as FrameIndex's.
51// PPCEmitCmp: Handle immediate as operand 1.
52// SelectCall: Handle small byval arguments.
53// SelectIntrinsicCall: Implement.
54// SelectSelect: Implement.
55// Consider factoring isTypeLegal into the base class.
56// Implement switches and jump tables.
57//
58//===----------------------------------------------------------------------===//
59using namespace llvm;
60
61#define DEBUG_TYPE "ppcfastisel"
62
63namespace {
64
65struct Address {
66 enum {
67 RegBase,
68 FrameIndexBase
69 } BaseType;
70
71 union {
72 unsigned Reg;
73 int FI;
74 } Base;
75
76 int64_t Offset;
77
78 // Innocuous defaults for our address.
79 Address()
80 : BaseType(RegBase), Offset(0) {
81 Base.Reg = 0;
82 }
83};
84
85class PPCFastISel final : public FastISel {
86
87 const TargetMachine &TM;
88 const PPCSubtarget *Subtarget;
89 PPCFunctionInfo *PPCFuncInfo;
90 const TargetInstrInfo &TII;
91 const TargetLowering &TLI;
92 LLVMContext *Context;
93
94 public:
95 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
96 const TargetLibraryInfo *LibInfo)
97 : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
98 Subtarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
99 PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
100 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()),
101 Context(&FuncInfo.Fn->getContext()) {}
102
103 // Backend specific FastISel code.
104 private:
105 bool fastSelectInstruction(const Instruction *I) override;
106 unsigned fastMaterializeConstant(const Constant *C) override;
107 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
108 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
109 const LoadInst *LI) override;
110 bool fastLowerArguments() override;
111 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
112 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
113 const TargetRegisterClass *RC,
114 unsigned Op0, uint64_t Imm);
115 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
116 const TargetRegisterClass *RC, unsigned Op0);
117 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
118 const TargetRegisterClass *RC,
119 unsigned Op0, unsigned Op1);
120
121 bool fastLowerCall(CallLoweringInfo &CLI) override;
122
123 // Instruction selection routines.
124 private:
125 bool SelectLoad(const Instruction *I);
126 bool SelectStore(const Instruction *I);
127 bool SelectBranch(const Instruction *I);
128 bool SelectIndirectBr(const Instruction *I);
129 bool SelectFPExt(const Instruction *I);
130 bool SelectFPTrunc(const Instruction *I);
131 bool SelectIToFP(const Instruction *I, bool IsSigned);
132 bool SelectFPToI(const Instruction *I, bool IsSigned);
133 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
134 bool SelectRet(const Instruction *I);
135 bool SelectTrunc(const Instruction *I);
136 bool SelectIntExt(const Instruction *I);
137
138 // Utility routines.
139 private:
140 bool isTypeLegal(Type *Ty, MVT &VT);
141 bool isLoadTypeLegal(Type *Ty, MVT &VT);
142 bool isValueAvailable(const Value *V) const;
143 bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
144 return RC->getID() == PPC::VSFRCRegClassID;
145 }
146 bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
147 return RC->getID() == PPC::VSSRCRegClassID;
148 }
149 unsigned copyRegToRegClass(const TargetRegisterClass *ToRC,
150 unsigned SrcReg, unsigned Flag = 0,
151 unsigned SubReg = 0) {
152 Register TmpReg = createResultReg(ToRC);
153 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
154 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
155 return TmpReg;
156 }
157 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
158 bool isZExt, unsigned DestReg,
159 const PPC::Predicate Pred);
160 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
161 const TargetRegisterClass *RC, bool IsZExt = true,
162 unsigned FP64LoadOpc = PPC::LFD);
163 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
164 bool PPCComputeAddress(const Value *Obj, Address &Addr);
165 void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
166 unsigned &IndexReg);
167 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
168 unsigned DestReg, bool IsZExt);
169 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
170 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
171 unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
172 bool UseSExt = true);
173 unsigned PPCMaterialize32BitInt(int64_t Imm,
174 const TargetRegisterClass *RC);
175 unsigned PPCMaterialize64BitInt(int64_t Imm,
176 const TargetRegisterClass *RC);
177 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
178 unsigned SrcReg, bool IsSigned);
179 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
180
181 // Call handling routines.
182 private:
183 bool processCallArgs(SmallVectorImpl<Value*> &Args,
185 SmallVectorImpl<MVT> &ArgVTs,
189 unsigned &NumBytes,
190 bool IsVarArg);
191 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
192
193 private:
194 #include "PPCGenFastISel.inc"
195
196};
197
198} // end anonymous namespace
199
200static std::optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
201 switch (Pred) {
202 // These are not representable with any single compare.
205 // Major concern about the following 6 cases is NaN result. The comparison
206 // result consists of 4 bits, indicating lt, eq, gt and un (unordered),
207 // only one of which will be set. The result is generated by fcmpu
208 // instruction. However, bc instruction only inspects one of the first 3
209 // bits, so when un is set, bc instruction may jump to an undesired
210 // place.
211 //
212 // More specifically, if we expect an unordered comparison and un is set, we
213 // expect to always go to true branch; in such case UEQ, UGT and ULT still
214 // give false, which are undesired; but UNE, UGE, ULE happen to give true,
215 // since they are tested by inspecting !eq, !lt, !gt, respectively.
216 //
217 // Similarly, for ordered comparison, when un is set, we always expect the
218 // result to be false. In such case OGT, OLT and OEQ is good, since they are
219 // actually testing GT, LT, and EQ respectively, which are false. OGE, OLE
220 // and ONE are tested through !lt, !gt and !eq, and these are true.
227 default:
228 return std::nullopt;
229
231 case CmpInst::ICMP_EQ:
232 return PPC::PRED_EQ;
233
237 return PPC::PRED_GT;
238
242 return PPC::PRED_GE;
243
247 return PPC::PRED_LT;
248
252 return PPC::PRED_LE;
253
255 case CmpInst::ICMP_NE:
256 return PPC::PRED_NE;
257
259 return PPC::PRED_NU;
260
262 return PPC::PRED_UN;
263 }
264}
265
266// Determine whether the type Ty is simple enough to be handled by
267// fast-isel, and return its equivalent machine type in VT.
268// FIXME: Copied directly from ARM -- factor into base class?
269bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
270 EVT Evt = TLI.getValueType(DL, Ty, true);
271
272 // Only handle simple types.
273 if (Evt == MVT::Other || !Evt.isSimple()) return false;
274 VT = Evt.getSimpleVT();
275
276 // Handle all legal types, i.e. a register that will directly hold this
277 // value.
278 return TLI.isTypeLegal(VT);
279}
280
281// Determine whether the type Ty is simple enough to be handled by
282// fast-isel as a load target, and return its equivalent machine type in VT.
283bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
284 if (isTypeLegal(Ty, VT)) return true;
285
286 // If this is a type than can be sign or zero-extended to a basic operation
287 // go ahead and accept it now.
288 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
289 return true;
290 }
291
292 return false;
293}
294
295bool PPCFastISel::isValueAvailable(const Value *V) const {
296 if (!isa<Instruction>(V))
297 return true;
298
299 const auto *I = cast<Instruction>(V);
300 return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
301}
302
303// Given a value Obj, create an Address object Addr that represents its
304// address. Return false if we can't handle it.
305bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
306 const User *U = nullptr;
307 unsigned Opcode = Instruction::UserOp1;
308 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
309 // Don't walk into other basic blocks unless the object is an alloca from
310 // another block, otherwise it may not have a virtual register assigned.
311 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
312 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
313 Opcode = I->getOpcode();
314 U = I;
315 }
316 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
317 Opcode = C->getOpcode();
318 U = C;
319 }
320
321 switch (Opcode) {
322 default:
323 break;
324 case Instruction::BitCast:
325 // Look through bitcasts.
326 return PPCComputeAddress(U->getOperand(0), Addr);
327 case Instruction::IntToPtr:
328 // Look past no-op inttoptrs.
329 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
330 TLI.getPointerTy(DL))
331 return PPCComputeAddress(U->getOperand(0), Addr);
332 break;
333 case Instruction::PtrToInt:
334 // Look past no-op ptrtoints.
335 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
336 return PPCComputeAddress(U->getOperand(0), Addr);
337 break;
338 case Instruction::GetElementPtr: {
339 Address SavedAddr = Addr;
340 int64_t TmpOffset = Addr.Offset;
341
342 // Iterate through the GEP folding the constants into offsets where
343 // we can.
345 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
346 II != IE; ++II, ++GTI) {
347 const Value *Op = *II;
348 if (StructType *STy = GTI.getStructTypeOrNull()) {
349 const StructLayout *SL = DL.getStructLayout(STy);
350 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
351 TmpOffset += SL->getElementOffset(Idx);
352 } else {
354 for (;;) {
355 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
356 // Constant-offset addressing.
357 TmpOffset += CI->getSExtValue() * S;
358 break;
359 }
360 if (canFoldAddIntoGEP(U, Op)) {
361 // A compatible add with a constant operand. Fold the constant.
362 ConstantInt *CI =
363 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
364 TmpOffset += CI->getSExtValue() * S;
365 // Iterate on the other operand.
366 Op = cast<AddOperator>(Op)->getOperand(0);
367 continue;
368 }
369 // Unsupported
370 goto unsupported_gep;
371 }
372 }
373 }
374
375 // Try to grab the base operand now.
376 Addr.Offset = TmpOffset;
377 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
378
379 // We failed, restore everything and try the other options.
380 Addr = SavedAddr;
381
382 unsupported_gep:
383 break;
384 }
385 case Instruction::Alloca: {
386 const AllocaInst *AI = cast<AllocaInst>(Obj);
388 FuncInfo.StaticAllocaMap.find(AI);
389 if (SI != FuncInfo.StaticAllocaMap.end()) {
390 Addr.BaseType = Address::FrameIndexBase;
391 Addr.Base.FI = SI->second;
392 return true;
393 }
394 break;
395 }
396 }
397
398 // FIXME: References to parameters fall through to the behavior
399 // below. They should be able to reference a frame index since
400 // they are stored to the stack, so we can get "ld rx, offset(r1)"
401 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
402 // just contain the parameter. Try to handle this with a FI.
403
404 // Try to get this in a register if nothing else has worked.
405 if (Addr.Base.Reg == 0)
406 Addr.Base.Reg = getRegForValue(Obj);
407
408 // Prevent assignment of base register to X0, which is inappropriate
409 // for loads and stores alike.
410 if (Addr.Base.Reg != 0)
411 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
412
413 return Addr.Base.Reg != 0;
414}
415
416// Fix up some addresses that can't be used directly. For example, if
417// an offset won't fit in an instruction field, we may need to move it
418// into an index register.
419void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
420 unsigned &IndexReg) {
421
422 // Check whether the offset fits in the instruction field.
423 if (!isInt<16>(Addr.Offset))
424 UseOffset = false;
425
426 // If this is a stack pointer and the offset needs to be simplified then
427 // put the alloca address into a register, set the base type back to
428 // register and continue. This should almost never happen.
429 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
430 Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDI8),
432 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
433 Addr.Base.Reg = ResultReg;
434 Addr.BaseType = Address::RegBase;
435 }
436
437 if (!UseOffset) {
438 IntegerType *OffsetTy = Type::getInt64Ty(*Context);
439 const ConstantInt *Offset = ConstantInt::getSigned(OffsetTy, Addr.Offset);
440 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
441 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
442 }
443}
444
445// Emit a load instruction if possible, returning true if we succeeded,
446// otherwise false. See commentary below for how the register class of
447// the load is determined.
448bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
449 const TargetRegisterClass *RC,
450 bool IsZExt, unsigned FP64LoadOpc) {
451 unsigned Opc;
452 bool UseOffset = true;
453 bool HasSPE = Subtarget->hasSPE();
454
455 // If ResultReg is given, it determines the register class of the load.
456 // Otherwise, RC is the register class to use. If the result of the
457 // load isn't anticipated in this block, both may be zero, in which
458 // case we must make a conservative guess. In particular, don't assign
459 // R0 or X0 to the result register, as the result may be used in a load,
460 // store, add-immediate, or isel that won't permit this. (Though
461 // perhaps the spill and reload of live-exit values would handle this?)
462 const TargetRegisterClass *UseRC =
463 (ResultReg ? MRI.getRegClass(ResultReg) :
464 (RC ? RC :
465 (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
466 (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
467 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
468 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
469
470 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
471
472 switch (VT.SimpleTy) {
473 default: // e.g., vector types not handled
474 return false;
475 case MVT::i8:
476 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
477 break;
478 case MVT::i16:
479 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
480 : (Is32BitInt ? PPC::LHA : PPC::LHA8));
481 break;
482 case MVT::i32:
483 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
484 : (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
485 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
486 UseOffset = false;
487 break;
488 case MVT::i64:
489 Opc = PPC::LD;
490 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
491 "64-bit load with 32-bit target??");
492 UseOffset = ((Addr.Offset & 3) == 0);
493 break;
494 case MVT::f32:
495 Opc = Subtarget->hasSPE() ? PPC::SPELWZ : PPC::LFS;
496 break;
497 case MVT::f64:
498 Opc = FP64LoadOpc;
499 break;
500 }
501
502 // If necessary, materialize the offset into a register and use
503 // the indexed form. Also handle stack pointers with special needs.
504 unsigned IndexReg = 0;
505 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
506
507 // If this is a potential VSX load with an offset of 0, a VSX indexed load can
508 // be used.
509 bool IsVSSRC = isVSSRCRegClass(UseRC);
510 bool IsVSFRC = isVSFRCRegClass(UseRC);
511 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
512 bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD;
513 if ((Is32VSXLoad || Is64VSXLoad) &&
514 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
515 (Addr.Offset == 0)) {
516 UseOffset = false;
517 }
518
519 if (ResultReg == 0)
520 ResultReg = createResultReg(UseRC);
521
522 // Note: If we still have a frame index here, we know the offset is
523 // in range, as otherwise PPCSimplifyAddress would have converted it
524 // into a RegBase.
525 if (Addr.BaseType == Address::FrameIndexBase) {
526 // VSX only provides an indexed load.
527 if (Is32VSXLoad || Is64VSXLoad) return false;
528
529 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
530 MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
531 Addr.Offset),
532 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
533 MFI.getObjectAlign(Addr.Base.FI));
534
535 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
536 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
537
538 // Base reg with offset in range.
539 } else if (UseOffset) {
540 // VSX only provides an indexed load.
541 if (Is32VSXLoad || Is64VSXLoad) return false;
542
543 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
544 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
545
546 // Indexed form.
547 } else {
548 // Get the RR opcode corresponding to the RI one. FIXME: It would be
549 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
550 // is hard to get at.
551 switch (Opc) {
552 default: llvm_unreachable("Unexpected opcode!");
553 case PPC::LBZ: Opc = PPC::LBZX; break;
554 case PPC::LBZ8: Opc = PPC::LBZX8; break;
555 case PPC::LHZ: Opc = PPC::LHZX; break;
556 case PPC::LHZ8: Opc = PPC::LHZX8; break;
557 case PPC::LHA: Opc = PPC::LHAX; break;
558 case PPC::LHA8: Opc = PPC::LHAX8; break;
559 case PPC::LWZ: Opc = PPC::LWZX; break;
560 case PPC::LWZ8: Opc = PPC::LWZX8; break;
561 case PPC::LWA: Opc = PPC::LWAX; break;
562 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
563 case PPC::LD: Opc = PPC::LDX; break;
564 case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
565 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
566 case PPC::EVLDD: Opc = PPC::EVLDDX; break;
567 case PPC::SPELWZ: Opc = PPC::SPELWZX; break;
568 }
569
570 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
571 ResultReg);
572
573 // If we have an index register defined we use it in the store inst,
574 // otherwise we use X0 as base as it makes the vector instructions to
575 // use zero in the computation of the effective address regardless the
576 // content of the register.
577 if (IndexReg)
578 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
579 else
580 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
581 }
582
583 return true;
584}
585
586// Attempt to fast-select a load instruction.
587bool PPCFastISel::SelectLoad(const Instruction *I) {
588 // FIXME: No atomic loads are supported.
589 if (cast<LoadInst>(I)->isAtomic())
590 return false;
591
592 // Verify we have a legal type before going any further.
593 MVT VT;
594 if (!isLoadTypeLegal(I->getType(), VT))
595 return false;
596
597 // See if we can handle this address.
599 if (!PPCComputeAddress(I->getOperand(0), Addr))
600 return false;
601
602 // Look at the currently assigned register for this instruction
603 // to determine the required register class. This is necessary
604 // to constrain RA from using R0/X0 when this is not legal.
605 Register AssignedReg = FuncInfo.ValueMap[I];
606 const TargetRegisterClass *RC =
607 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
608
609 Register ResultReg = 0;
610 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
611 Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
612 return false;
613 updateValueMap(I, ResultReg);
614 return true;
615}
616
617// Emit a store instruction to store SrcReg at Addr.
618bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
619 assert(SrcReg && "Nothing to store!");
620 unsigned Opc;
621 bool UseOffset = true;
622
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
624 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
625
626 switch (VT.SimpleTy) {
627 default: // e.g., vector types not handled
628 return false;
629 case MVT::i8:
630 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
631 break;
632 case MVT::i16:
633 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
634 break;
635 case MVT::i32:
636 assert(Is32BitInt && "Not GPRC for i32??");
637 Opc = PPC::STW;
638 break;
639 case MVT::i64:
640 Opc = PPC::STD;
641 UseOffset = ((Addr.Offset & 3) == 0);
642 break;
643 case MVT::f32:
644 Opc = Subtarget->hasSPE() ? PPC::SPESTW : PPC::STFS;
645 break;
646 case MVT::f64:
647 Opc = Subtarget->hasSPE() ? PPC::EVSTDD : PPC::STFD;
648 break;
649 }
650
651 // If necessary, materialize the offset into a register and use
652 // the indexed form. Also handle stack pointers with special needs.
653 unsigned IndexReg = 0;
654 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
655
656 // If this is a potential VSX store with an offset of 0, a VSX indexed store
657 // can be used.
658 bool IsVSSRC = isVSSRCRegClass(RC);
659 bool IsVSFRC = isVSFRCRegClass(RC);
660 bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
661 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
662 if ((Is32VSXStore || Is64VSXStore) &&
663 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
664 (Addr.Offset == 0)) {
665 UseOffset = false;
666 }
667
668 // Note: If we still have a frame index here, we know the offset is
669 // in range, as otherwise PPCSimplifyAddress would have converted it
670 // into a RegBase.
671 if (Addr.BaseType == Address::FrameIndexBase) {
672 // VSX only provides an indexed store.
673 if (Is32VSXStore || Is64VSXStore) return false;
674
675 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
676 MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
677 Addr.Offset),
678 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
679 MFI.getObjectAlign(Addr.Base.FI));
680
681 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
682 .addReg(SrcReg)
683 .addImm(Addr.Offset)
684 .addFrameIndex(Addr.Base.FI)
685 .addMemOperand(MMO);
686
687 // Base reg with offset in range.
688 } else if (UseOffset) {
689 // VSX only provides an indexed store.
690 if (Is32VSXStore || Is64VSXStore)
691 return false;
692
693 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
694 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
695
696 // Indexed form.
697 } else {
698 // Get the RR opcode corresponding to the RI one. FIXME: It would be
699 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
700 // is hard to get at.
701 switch (Opc) {
702 default: llvm_unreachable("Unexpected opcode!");
703 case PPC::STB: Opc = PPC::STBX; break;
704 case PPC::STH : Opc = PPC::STHX; break;
705 case PPC::STW : Opc = PPC::STWX; break;
706 case PPC::STB8: Opc = PPC::STBX8; break;
707 case PPC::STH8: Opc = PPC::STHX8; break;
708 case PPC::STW8: Opc = PPC::STWX8; break;
709 case PPC::STD: Opc = PPC::STDX; break;
710 case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
711 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
712 case PPC::EVSTDD: Opc = PPC::EVSTDDX; break;
713 case PPC::SPESTW: Opc = PPC::SPESTWX; break;
714 }
715
716 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
717 .addReg(SrcReg);
718
719 // If we have an index register defined we use it in the store inst,
720 // otherwise we use X0 as base as it makes the vector instructions to
721 // use zero in the computation of the effective address regardless the
722 // content of the register.
723 if (IndexReg)
724 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
725 else
726 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
727 }
728
729 return true;
730}
731
732// Attempt to fast-select a store instruction.
733bool PPCFastISel::SelectStore(const Instruction *I) {
734 Value *Op0 = I->getOperand(0);
735 unsigned SrcReg = 0;
736
737 // FIXME: No atomics loads are supported.
738 if (cast<StoreInst>(I)->isAtomic())
739 return false;
740
741 // Verify we have a legal type before going any further.
742 MVT VT;
743 if (!isLoadTypeLegal(Op0->getType(), VT))
744 return false;
745
746 // Get the value to be stored into a register.
747 SrcReg = getRegForValue(Op0);
748 if (SrcReg == 0)
749 return false;
750
751 // See if we can handle this address.
753 if (!PPCComputeAddress(I->getOperand(1), Addr))
754 return false;
755
756 if (!PPCEmitStore(VT, SrcReg, Addr))
757 return false;
758
759 return true;
760}
761
762// Attempt to fast-select a branch instruction.
763bool PPCFastISel::SelectBranch(const Instruction *I) {
764 const BranchInst *BI = cast<BranchInst>(I);
765 MachineBasicBlock *BrBB = FuncInfo.MBB;
766 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
767 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
768
769 // For now, just try the simplest case where it's fed by a compare.
770 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
771 if (isValueAvailable(CI)) {
772 std::optional<PPC::Predicate> OptPPCPred =
773 getComparePred(CI->getPredicate());
774 if (!OptPPCPred)
775 return false;
776
777 PPC::Predicate PPCPred = *OptPPCPred;
778
779 // Take advantage of fall-through opportunities.
780 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
781 std::swap(TBB, FBB);
782 PPCPred = PPC::InvertPredicate(PPCPred);
783 }
784
785 Register CondReg = createResultReg(&PPC::CRRCRegClass);
786
787 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
788 CondReg, PPCPred))
789 return false;
790
791 BuildMI(*BrBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::BCC))
792 .addImm(Subtarget->hasSPE() ? PPC::PRED_SPE : PPCPred)
793 .addReg(CondReg)
794 .addMBB(TBB);
795 finishCondBranch(BI->getParent(), TBB, FBB);
796 return true;
797 }
798 } else if (const ConstantInt *CI =
799 dyn_cast<ConstantInt>(BI->getCondition())) {
800 uint64_t Imm = CI->getZExtValue();
801 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
802 fastEmitBranch(Target, MIMD.getDL());
803 return true;
804 }
805
806 // FIXME: ARM looks for a case where the block containing the compare
807 // has been split from the block containing the branch. If this happens,
808 // there is a vreg available containing the result of the compare. I'm
809 // not sure we can do much, as we've lost the predicate information with
810 // the compare instruction -- we have a 4-bit CR but don't know which bit
811 // to test here.
812 return false;
813}
814
815// Attempt to emit a compare of the two source values. Signed and unsigned
816// comparisons are supported. Return false if we can't handle it.
817bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
818 bool IsZExt, unsigned DestReg,
819 const PPC::Predicate Pred) {
820 Type *Ty = SrcValue1->getType();
821 EVT SrcEVT = TLI.getValueType(DL, Ty, true);
822 if (!SrcEVT.isSimple())
823 return false;
824 MVT SrcVT = SrcEVT.getSimpleVT();
825
826 if (SrcVT == MVT::i1 && Subtarget->useCRBits())
827 return false;
828
829 // See if operand 2 is an immediate encodeable in the compare.
830 // FIXME: Operands are not in canonical order at -O0, so an immediate
831 // operand in position 1 is a lost opportunity for now. We are
832 // similar to ARM in this regard.
833 int64_t Imm = 0;
834 bool UseImm = false;
835 const bool HasSPE = Subtarget->hasSPE();
836
837 // Only 16-bit integer constants can be represented in compares for
838 // PowerPC. Others will be materialized into a register.
839 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
840 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
841 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
842 const APInt &CIVal = ConstInt->getValue();
843 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() :
844 (int64_t)CIVal.getSExtValue();
845 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
846 UseImm = true;
847 }
848 }
849
850 Register SrcReg1 = getRegForValue(SrcValue1);
851 if (SrcReg1 == 0)
852 return false;
853
854 unsigned SrcReg2 = 0;
855 if (!UseImm) {
856 SrcReg2 = getRegForValue(SrcValue2);
857 if (SrcReg2 == 0)
858 return false;
859 }
860
861 unsigned CmpOpc;
862 bool NeedsExt = false;
863
864 auto RC1 = MRI.getRegClass(SrcReg1);
865 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
866
867 switch (SrcVT.SimpleTy) {
868 default: return false;
869 case MVT::f32:
870 if (HasSPE) {
871 switch (Pred) {
872 default: return false;
873 case PPC::PRED_EQ:
874 CmpOpc = PPC::EFSCMPEQ;
875 break;
876 case PPC::PRED_LT:
877 CmpOpc = PPC::EFSCMPLT;
878 break;
879 case PPC::PRED_GT:
880 CmpOpc = PPC::EFSCMPGT;
881 break;
882 }
883 } else {
884 CmpOpc = PPC::FCMPUS;
885 if (isVSSRCRegClass(RC1))
886 SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1);
887 if (RC2 && isVSSRCRegClass(RC2))
888 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
889 }
890 break;
891 case MVT::f64:
892 if (HasSPE) {
893 switch (Pred) {
894 default: return false;
895 case PPC::PRED_EQ:
896 CmpOpc = PPC::EFDCMPEQ;
897 break;
898 case PPC::PRED_LT:
899 CmpOpc = PPC::EFDCMPLT;
900 break;
901 case PPC::PRED_GT:
902 CmpOpc = PPC::EFDCMPGT;
903 break;
904 }
905 } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) {
906 CmpOpc = PPC::XSCMPUDP;
907 } else {
908 CmpOpc = PPC::FCMPUD;
909 }
910 break;
911 case MVT::i1:
912 case MVT::i8:
913 case MVT::i16:
914 NeedsExt = true;
915 [[fallthrough]];
916 case MVT::i32:
917 if (!UseImm)
918 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
919 else
920 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
921 break;
922 case MVT::i64:
923 if (!UseImm)
924 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
925 else
926 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
927 break;
928 }
929
930 if (NeedsExt) {
931 Register ExtReg = createResultReg(&PPC::GPRCRegClass);
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
933 return false;
934 SrcReg1 = ExtReg;
935
936 if (!UseImm) {
937 Register ExtReg = createResultReg(&PPC::GPRCRegClass);
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
939 return false;
940 SrcReg2 = ExtReg;
941 }
942 }
943
944 if (!UseImm)
945 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(CmpOpc), DestReg)
946 .addReg(SrcReg1).addReg(SrcReg2);
947 else
948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(CmpOpc), DestReg)
949 .addReg(SrcReg1).addImm(Imm);
950
951 return true;
952}
953
954// Attempt to fast-select a floating-point extend instruction.
955bool PPCFastISel::SelectFPExt(const Instruction *I) {
956 Value *Src = I->getOperand(0);
957 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
958 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
959
960 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
961 return false;
962
963 Register SrcReg = getRegForValue(Src);
964 if (!SrcReg)
965 return false;
966
967 // No code is generated for a FP extend.
968 updateValueMap(I, SrcReg);
969 return true;
970}
971
972// Attempt to fast-select a floating-point truncate instruction.
973bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
974 Value *Src = I->getOperand(0);
975 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
976 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
977
978 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
979 return false;
980
981 Register SrcReg = getRegForValue(Src);
982 if (!SrcReg)
983 return false;
984
985 // Round the result to single precision.
986 unsigned DestReg;
987 auto RC = MRI.getRegClass(SrcReg);
988 if (Subtarget->hasSPE()) {
989 DestReg = createResultReg(&PPC::GPRCRegClass);
990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::EFSCFD),
991 DestReg)
992 .addReg(SrcReg);
993 } else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
994 DestReg = createResultReg(&PPC::VSSRCRegClass);
995 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::XSRSP),
996 DestReg)
997 .addReg(SrcReg);
998 } else {
999 SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
1000 DestReg = createResultReg(&PPC::F4RCRegClass);
1001 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1002 TII.get(PPC::FRSP), DestReg)
1003 .addReg(SrcReg);
1004 }
1005
1006 updateValueMap(I, DestReg);
1007 return true;
1008}
1009
1010// Move an i32 or i64 value in a GPR to an f64 value in an FPR.
1011// FIXME: When direct register moves are implemented (see PowerISA 2.07),
1012// those should be used instead of moving via a stack slot when the
1013// subtarget permits.
1014// FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
1015// stack slot and 4-byte store/load sequence. Or just sext the 4-byte
1016// case to 8 bytes which produces tighter code but wastes stack space.
1017unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
1018 bool IsSigned) {
1019
1020 // If necessary, extend 32-bit int to 64-bit.
1021 if (SrcVT == MVT::i32) {
1022 Register TmpReg = createResultReg(&PPC::G8RCRegClass);
1023 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1024 return 0;
1025 SrcReg = TmpReg;
1026 }
1027
1028 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1029 Address Addr;
1030 Addr.BaseType = Address::FrameIndexBase;
1031 Addr.Base.FI = MFI.CreateStackObject(8, Align(8), false);
1032
1033 // Store the value from the GPR.
1034 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1035 return 0;
1036
1037 // Load the integer value into an FPR. The kind of load used depends
1038 // on a number of conditions.
1039 unsigned LoadOpc = PPC::LFD;
1040
1041 if (SrcVT == MVT::i32) {
1042 if (!IsSigned) {
1043 LoadOpc = PPC::LFIWZX;
1044 Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1045 } else if (Subtarget->hasLFIWAX()) {
1046 LoadOpc = PPC::LFIWAX;
1047 Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1048 }
1049 }
1050
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1052 Register ResultReg = 0;
1053 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1054 return 0;
1055
1056 return ResultReg;
1057}
1058
1059// Attempt to fast-select an integer-to-floating-point conversion.
1060// FIXME: Once fast-isel has better support for VSX, conversions using
1061// direct moves should be implemented.
1062bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
1063 MVT DstVT;
1064 Type *DstTy = I->getType();
1065 if (!isTypeLegal(DstTy, DstVT))
1066 return false;
1067
1068 if (DstVT != MVT::f32 && DstVT != MVT::f64)
1069 return false;
1070
1071 Value *Src = I->getOperand(0);
1072 EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1073 if (!SrcEVT.isSimple())
1074 return false;
1075
1076 MVT SrcVT = SrcEVT.getSimpleVT();
1077
1078 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
1079 SrcVT != MVT::i32 && SrcVT != MVT::i64)
1080 return false;
1081
1082 Register SrcReg = getRegForValue(Src);
1083 if (SrcReg == 0)
1084 return false;
1085
1086 // Shortcut for SPE. Doesn't need to store/load, since it's all in the GPRs
1087 if (Subtarget->hasSPE()) {
1088 unsigned Opc;
1089 if (DstVT == MVT::f32)
1090 Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI;
1091 else
1092 Opc = IsSigned ? PPC::EFDCFSI : PPC::EFDCFUI;
1093
1094 Register DestReg = createResultReg(&PPC::SPERCRegClass);
1095 // Generate the convert.
1096 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1097 .addReg(SrcReg);
1098 updateValueMap(I, DestReg);
1099 return true;
1100 }
1101
1102 // We can only lower an unsigned convert if we have the newer
1103 // floating-point conversion operations.
1104 if (!IsSigned && !Subtarget->hasFPCVT())
1105 return false;
1106
1107 // FIXME: For now we require the newer floating-point conversion operations
1108 // (which are present only on P7 and A2 server models) when converting
1109 // to single-precision float. Otherwise we have to generate a lot of
1110 // fiddly code to avoid double rounding. If necessary, the fiddly code
1111 // can be found in PPCTargetLowering::LowerINT_TO_FP().
1112 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT())
1113 return false;
1114
1115 // Extend the input if necessary.
1116 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1117 Register TmpReg = createResultReg(&PPC::G8RCRegClass);
1118 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1119 return false;
1120 SrcVT = MVT::i64;
1121 SrcReg = TmpReg;
1122 }
1123
1124 // Move the integer value to an FPR.
1125 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1126 if (FPReg == 0)
1127 return false;
1128
1129 // Determine the opcode for the conversion.
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1131 Register DestReg = createResultReg(RC);
1132 unsigned Opc;
1133
1134 if (DstVT == MVT::f32)
1135 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1136 else
1137 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1138
1139 // Generate the convert.
1140 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1141 .addReg(FPReg);
1142
1143 updateValueMap(I, DestReg);
1144 return true;
1145}
1146
1147// Move the floating-point value in SrcReg into an integer destination
1148// register, and return the register (or zero if we can't handle it).
1149// FIXME: When direct register moves are implemented (see PowerISA 2.07),
1150// those should be used instead of moving via a stack slot when the
1151// subtarget permits.
1152unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1153 unsigned SrcReg, bool IsSigned) {
1154 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1155 // Note that if have STFIWX available, we could use a 4-byte stack
1156 // slot for i32, but this being fast-isel we'll just go with the
1157 // easiest code gen possible.
1158 Address Addr;
1159 Addr.BaseType = Address::FrameIndexBase;
1160 Addr.Base.FI = MFI.CreateStackObject(8, Align(8), false);
1161
1162 // Store the value from the FPR.
1163 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1164 return 0;
1165
1166 // Reload it into a GPR. If we want an i32 on big endian, modify the
1167 // address to have a 4-byte offset so we load from the right place.
1168 if (VT == MVT::i32)
1169 Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1170
1171 // Look at the currently assigned register for this instruction
1172 // to determine the required register class.
1173 Register AssignedReg = FuncInfo.ValueMap[I];
1174 const TargetRegisterClass *RC =
1175 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1176
1177 Register ResultReg = 0;
1178 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1179 return 0;
1180
1181 return ResultReg;
1182}
1183
1184// Attempt to fast-select a floating-point-to-integer conversion.
1185// FIXME: Once fast-isel has better support for VSX, conversions using
1186// direct moves should be implemented.
1187bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1188 MVT DstVT, SrcVT;
1189 Type *DstTy = I->getType();
1190 if (!isTypeLegal(DstTy, DstVT))
1191 return false;
1192
1193 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1194 return false;
1195
1196 // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG.
1197 if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() &&
1198 !Subtarget->hasSPE())
1199 return false;
1200
1201 Value *Src = I->getOperand(0);
1202 Type *SrcTy = Src->getType();
1203 if (!isTypeLegal(SrcTy, SrcVT))
1204 return false;
1205
1206 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1207 return false;
1208
1209 Register SrcReg = getRegForValue(Src);
1210 if (SrcReg == 0)
1211 return false;
1212
1213 // Convert f32 to f64 or convert VSSRC to VSFRC if necessary. This is just a
1214 // meaningless copy to get the register class right.
1215 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1216 if (InRC == &PPC::F4RCRegClass)
1217 SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
1218 else if (InRC == &PPC::VSSRCRegClass)
1219 SrcReg = copyRegToRegClass(&PPC::VSFRCRegClass, SrcReg);
1220
1221 // Determine the opcode for the conversion, which takes place
1222 // entirely within FPRs or VSRs.
1223 unsigned DestReg;
1224 unsigned Opc;
1225 auto RC = MRI.getRegClass(SrcReg);
1226
1227 if (Subtarget->hasSPE()) {
1228 DestReg = createResultReg(&PPC::GPRCRegClass);
1229 if (IsSigned)
1230 Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
1231 else
1232 Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
1233 } else if (isVSFRCRegClass(RC)) {
1234 DestReg = createResultReg(&PPC::VSFRCRegClass);
1235 if (DstVT == MVT::i32)
1236 Opc = IsSigned ? PPC::XSCVDPSXWS : PPC::XSCVDPUXWS;
1237 else
1238 Opc = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
1239 } else {
1240 DestReg = createResultReg(&PPC::F8RCRegClass);
1241 if (DstVT == MVT::i32)
1242 if (IsSigned)
1243 Opc = PPC::FCTIWZ;
1244 else
1245 Opc = Subtarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1246 else
1247 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1248 }
1249
1250 // Generate the convert.
1251 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1252 .addReg(SrcReg);
1253
1254 // Now move the integer value from a float register to an integer register.
1255 unsigned IntReg = Subtarget->hasSPE()
1256 ? DestReg
1257 : PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1258
1259 if (IntReg == 0)
1260 return false;
1261
1262 updateValueMap(I, IntReg);
1263 return true;
1264}
1265
1266// Attempt to fast-select a binary integer operation that isn't already
1267// handled automatically.
1268bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1269 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1270
1271 // We can get here in the case when we have a binary operation on a non-legal
1272 // type and the target independent selector doesn't know how to handle it.
1273 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1274 return false;
1275
1276 // Look at the currently assigned register for this instruction
1277 // to determine the required register class. If there is no register,
1278 // make a conservative choice (don't assign R0).
1279 Register AssignedReg = FuncInfo.ValueMap[I];
1280 const TargetRegisterClass *RC =
1281 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1282 &PPC::GPRC_and_GPRC_NOR0RegClass);
1283 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1284
1285 unsigned Opc;
1286 switch (ISDOpcode) {
1287 default: return false;
1288 case ISD::ADD:
1289 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1290 break;
1291 case ISD::OR:
1292 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1293 break;
1294 case ISD::SUB:
1295 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1296 break;
1297 }
1298
1299 Register ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1300 Register SrcReg1 = getRegForValue(I->getOperand(0));
1301 if (SrcReg1 == 0) return false;
1302
1303 // Handle case of small immediate operand.
1304 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1305 const APInt &CIVal = ConstInt->getValue();
1306 int Imm = (int)CIVal.getSExtValue();
1307 bool UseImm = true;
1308 if (isInt<16>(Imm)) {
1309 switch (Opc) {
1310 default:
1311 llvm_unreachable("Missing case!");
1312 case PPC::ADD4:
1313 Opc = PPC::ADDI;
1314 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1315 break;
1316 case PPC::ADD8:
1317 Opc = PPC::ADDI8;
1318 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1319 break;
1320 case PPC::OR:
1321 Opc = PPC::ORI;
1322 break;
1323 case PPC::OR8:
1324 Opc = PPC::ORI8;
1325 break;
1326 case PPC::SUBF:
1327 if (Imm == -32768)
1328 UseImm = false;
1329 else {
1330 Opc = PPC::ADDI;
1331 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1332 Imm = -Imm;
1333 }
1334 break;
1335 case PPC::SUBF8:
1336 if (Imm == -32768)
1337 UseImm = false;
1338 else {
1339 Opc = PPC::ADDI8;
1340 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1341 Imm = -Imm;
1342 }
1343 break;
1344 }
1345
1346 if (UseImm) {
1347 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
1348 ResultReg)
1349 .addReg(SrcReg1)
1350 .addImm(Imm);
1351 updateValueMap(I, ResultReg);
1352 return true;
1353 }
1354 }
1355 }
1356
1357 // Reg-reg case.
1358 Register SrcReg2 = getRegForValue(I->getOperand(1));
1359 if (SrcReg2 == 0) return false;
1360
1361 // Reverse operands for subtract-from.
1362 if (ISDOpcode == ISD::SUB)
1363 std::swap(SrcReg1, SrcReg2);
1364
1365 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
1366 .addReg(SrcReg1).addReg(SrcReg2);
1367 updateValueMap(I, ResultReg);
1368 return true;
1369}
1370
1371// Handle arguments to a call that we're attempting to fast-select.
1372// Return false if the arguments are too complex for us at the moment.
1373bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1375 SmallVectorImpl<MVT> &ArgVTs,
1379 unsigned &NumBytes,
1380 bool IsVarArg) {
1382 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1383
1384 // Reserve space for the linkage area on the stack.
1385 unsigned LinkageSize = Subtarget->getFrameLowering()->getLinkageSize();
1386 CCInfo.AllocateStack(LinkageSize, Align(8));
1387
1388 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1389
1390 // Bail out if we can't handle any of the arguments.
1391 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1392 CCValAssign &VA = ArgLocs[I];
1393 MVT ArgVT = ArgVTs[VA.getValNo()];
1394
1395 // Skip vector arguments for now, as well as long double and
1396 // uint128_t, and anything that isn't passed in a register.
1397 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1398 !VA.isRegLoc() || VA.needsCustom())
1399 return false;
1400
1401 // Skip bit-converted arguments for now.
1402 if (VA.getLocInfo() == CCValAssign::BCvt)
1403 return false;
1404 }
1405
1406 // Get a count of how many bytes are to be pushed onto the stack.
1407 NumBytes = CCInfo.getStackSize();
1408
1409 // The prolog code of the callee may store up to 8 GPR argument registers to
1410 // the stack, allowing va_start to index over them in memory if its varargs.
1411 // Because we cannot tell if this is needed on the caller side, we have to
1412 // conservatively assume that it is needed. As such, make sure we have at
1413 // least enough stack space for the caller to store the 8 GPRs.
1414 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1415 NumBytes = std::max(NumBytes, LinkageSize + 64);
1416
1417 // Issue CALLSEQ_START.
1418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1419 TII.get(TII.getCallFrameSetupOpcode()))
1420 .addImm(NumBytes).addImm(0);
1421
1422 // Prepare to assign register arguments. Every argument uses up a
1423 // GPR protocol register even if it's passed in a floating-point
1424 // register (unless we're using the fast calling convention).
1425 unsigned NextGPR = PPC::X3;
1426 unsigned NextFPR = PPC::F1;
1427
1428 // Process arguments.
1429 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1430 CCValAssign &VA = ArgLocs[I];
1431 unsigned Arg = ArgRegs[VA.getValNo()];
1432 MVT ArgVT = ArgVTs[VA.getValNo()];
1433
1434 // Handle argument promotion and bitcasts.
1435 switch (VA.getLocInfo()) {
1436 default:
1437 llvm_unreachable("Unknown loc info!");
1438 case CCValAssign::Full:
1439 break;
1440 case CCValAssign::SExt: {
1441 MVT DestVT = VA.getLocVT();
1442 const TargetRegisterClass *RC =
1443 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1444 Register TmpReg = createResultReg(RC);
1445 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1446 llvm_unreachable("Failed to emit a sext!");
1447 ArgVT = DestVT;
1448 Arg = TmpReg;
1449 break;
1450 }
1451 case CCValAssign::AExt:
1452 case CCValAssign::ZExt: {
1453 MVT DestVT = VA.getLocVT();
1454 const TargetRegisterClass *RC =
1455 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1456 Register TmpReg = createResultReg(RC);
1457 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1458 llvm_unreachable("Failed to emit a zext!");
1459 ArgVT = DestVT;
1460 Arg = TmpReg;
1461 break;
1462 }
1463 case CCValAssign::BCvt: {
1464 // FIXME: Not yet handled.
1465 llvm_unreachable("Should have bailed before getting here!");
1466 break;
1467 }
1468 }
1469
1470 // Copy this argument to the appropriate register.
1471 unsigned ArgReg;
1472 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1473 ArgReg = NextFPR++;
1474 if (CC != CallingConv::Fast)
1475 ++NextGPR;
1476 } else
1477 ArgReg = NextGPR++;
1478
1479 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1480 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1481 RegArgs.push_back(ArgReg);
1482 }
1483
1484 return true;
1485}
1486
1487// For a call that we've determined we can fast-select, finish the
1488// call sequence and generate a copy to obtain the return value (if any).
1489bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1490 CallingConv::ID CC = CLI.CallConv;
1491
1492 // Issue CallSEQ_END.
1493 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1494 TII.get(TII.getCallFrameDestroyOpcode()))
1495 .addImm(NumBytes).addImm(0);
1496
1497 // Next, generate a copy to obtain the return value.
1498 // FIXME: No multi-register return values yet, though I don't foresee
1499 // any real difficulties there.
1500 if (RetVT != MVT::isVoid) {
1502 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1503 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1504 CCValAssign &VA = RVLocs[0];
1505 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1506 assert(VA.isRegLoc() && "Can only return in registers!");
1507
1508 MVT DestVT = VA.getValVT();
1509 MVT CopyVT = DestVT;
1510
1511 // Ints smaller than a register still arrive in a full 64-bit
1512 // register, so make sure we recognize this.
1513 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1514 CopyVT = MVT::i64;
1515
1516 unsigned SourcePhysReg = VA.getLocReg();
1517 unsigned ResultReg = 0;
1518
1519 if (RetVT == CopyVT) {
1520 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1521 ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg);
1522
1523 // If necessary, round the floating result to single precision.
1524 } else if (CopyVT == MVT::f64) {
1525 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1526 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::FRSP),
1527 ResultReg).addReg(SourcePhysReg);
1528
1529 // If only the low half of a general register is needed, generate
1530 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1531 // used along the fast-isel path (not lowered), and downstream logic
1532 // also doesn't like a direct subreg copy on a physical reg.)
1533 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1534 // Convert physical register from G8RC to GPRC.
1535 SourcePhysReg -= PPC::X0 - PPC::R0;
1536 ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
1537 }
1538
1539 assert(ResultReg && "ResultReg unset!");
1540 CLI.InRegs.push_back(SourcePhysReg);
1541 CLI.ResultReg = ResultReg;
1542 CLI.NumResultRegs = 1;
1543 }
1544
1545 return true;
1546}
1547
1548bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1549 CallingConv::ID CC = CLI.CallConv;
1550 bool IsTailCall = CLI.IsTailCall;
1551 bool IsVarArg = CLI.IsVarArg;
1552 const Value *Callee = CLI.Callee;
1553 const MCSymbol *Symbol = CLI.Symbol;
1554
1555 if (!Callee && !Symbol)
1556 return false;
1557
1558 // Allow SelectionDAG isel to handle tail calls and long calls.
1559 if (IsTailCall || Subtarget->useLongCalls())
1560 return false;
1561
1562 // Let SDISel handle vararg functions.
1563 if (IsVarArg)
1564 return false;
1565
1566 // If this is a PC-Rel function, let SDISel handle the call.
1567 if (Subtarget->isUsingPCRelativeCalls())
1568 return false;
1569
1570 // Handle simple calls for now, with legal return types and
1571 // those that can be extended.
1572 Type *RetTy = CLI.RetTy;
1573 MVT RetVT;
1574 if (RetTy->isVoidTy())
1575 RetVT = MVT::isVoid;
1576 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1577 RetVT != MVT::i8)
1578 return false;
1579 else if (RetVT == MVT::i1 && Subtarget->useCRBits())
1580 // We can't handle boolean returns when CR bits are in use.
1581 return false;
1582
1583 // FIXME: No multi-register return values yet.
1584 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1585 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1586 RetVT != MVT::f64) {
1588 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1589 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1590 if (RVLocs.size() > 1)
1591 return false;
1592 }
1593
1594 // Bail early if more than 8 arguments, as we only currently
1595 // handle arguments passed in registers.
1596 unsigned NumArgs = CLI.OutVals.size();
1597 if (NumArgs > 8)
1598 return false;
1599
1600 // Set up the argument vectors.
1603 SmallVector<MVT, 8> ArgVTs;
1605
1606 Args.reserve(NumArgs);
1607 ArgRegs.reserve(NumArgs);
1608 ArgVTs.reserve(NumArgs);
1609 ArgFlags.reserve(NumArgs);
1610
1611 for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1612 // Only handle easy calls for now. It would be reasonably easy
1613 // to handle <= 8-byte structures passed ByVal in registers, but we
1614 // have to ensure they are right-justified in the register.
1615 ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1616 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1617 return false;
1618
1619 Value *ArgValue = CLI.OutVals[i];
1620 Type *ArgTy = ArgValue->getType();
1621 MVT ArgVT;
1622 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1623 return false;
1624
1625 // FIXME: FastISel cannot handle non-simple types yet, including 128-bit FP
1626 // types, which is passed through vector register. Skip these types and
1627 // fallback to default SelectionDAG based selection.
1628 if (ArgVT.isVector() || ArgVT == MVT::f128)
1629 return false;
1630
1631 Register Arg = getRegForValue(ArgValue);
1632 if (Arg == 0)
1633 return false;
1634
1635 Args.push_back(ArgValue);
1636 ArgRegs.push_back(Arg);
1637 ArgVTs.push_back(ArgVT);
1638 ArgFlags.push_back(Flags);
1639 }
1640
1641 // Process the arguments.
1643 unsigned NumBytes;
1644
1645 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1646 RegArgs, CC, NumBytes, IsVarArg))
1647 return false;
1648
1650 // FIXME: No handling for function pointers yet. This requires
1651 // implementing the function descriptor (OPD) setup.
1652 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1653 if (!GV) {
1654 // patchpoints are a special case; they always dispatch to a pointer value.
1655 // However, we don't actually want to generate the indirect call sequence
1656 // here (that will be generated, as necessary, during asm printing), and
1657 // the call we generate here will be erased by FastISel::selectPatchpoint,
1658 // so don't try very hard...
1659 if (CLI.IsPatchPoint)
1660 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::NOP));
1661 else
1662 return false;
1663 } else {
1664 // Build direct call with NOP for TOC restore.
1665 // FIXME: We can and should optimize away the NOP for local calls.
1666 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1667 TII.get(PPC::BL8_NOP));
1668 // Add callee.
1669 MIB.addGlobalAddress(GV);
1670 }
1671
1672 // Add implicit physical register uses to the call.
1673 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1674 MIB.addReg(RegArgs[II], RegState::Implicit);
1675
1676 // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1677 // into the call.
1678 PPCFuncInfo->setUsesTOCBasePtr();
1679 MIB.addReg(PPC::X2, RegState::Implicit);
1680
1681 // Add a register mask with the call-preserved registers. Proper
1682 // defs for return values will be added by setPhysRegsDeadExcept().
1683 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1684
1685 CLI.Call = MIB;
1686
1687 // Finish off the call including any return values.
1688 return finishCall(RetVT, CLI, NumBytes);
1689}
1690
1691// Attempt to fast-select a return instruction.
1692bool PPCFastISel::SelectRet(const Instruction *I) {
1693
1694 if (!FuncInfo.CanLowerReturn)
1695 return false;
1696
1697 const ReturnInst *Ret = cast<ReturnInst>(I);
1698 const Function &F = *I->getParent()->getParent();
1699
1700 // Build a list of return value registers.
1702 CallingConv::ID CC = F.getCallingConv();
1703
1704 if (Ret->getNumOperands() > 0) {
1706 GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1707
1708 // Analyze operands of the call, assigning locations to each operand.
1710 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1711 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1712 const Value *RV = Ret->getOperand(0);
1713
1714 // FIXME: Only one output register for now.
1715 if (ValLocs.size() > 1)
1716 return false;
1717
1718 // Special case for returning a constant integer of any size - materialize
1719 // the constant as an i64 and copy it to the return register.
1720 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1721 CCValAssign &VA = ValLocs[0];
1722
1723 Register RetReg = VA.getLocReg();
1724 // We still need to worry about properly extending the sign. For example,
1725 // we could have only a single bit or a constant that needs zero
1726 // extension rather than sign extension. Make sure we pass the return
1727 // value extension property to integer materialization.
1728 unsigned SrcReg =
1729 PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
1730
1731 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1732 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1733
1734 RetRegs.push_back(RetReg);
1735
1736 } else {
1737 Register Reg = getRegForValue(RV);
1738
1739 if (Reg == 0)
1740 return false;
1741
1742 // Copy the result values into the output registers.
1743 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1744
1745 CCValAssign &VA = ValLocs[i];
1746 assert(VA.isRegLoc() && "Can only return in registers!");
1747 RetRegs.push_back(VA.getLocReg());
1748 unsigned SrcReg = Reg + VA.getValNo();
1749
1750 EVT RVEVT = TLI.getValueType(DL, RV->getType());
1751 if (!RVEVT.isSimple())
1752 return false;
1753 MVT RVVT = RVEVT.getSimpleVT();
1754 MVT DestVT = VA.getLocVT();
1755
1756 if (RVVT != DestVT && RVVT != MVT::i8 &&
1757 RVVT != MVT::i16 && RVVT != MVT::i32)
1758 return false;
1759
1760 if (RVVT != DestVT) {
1761 switch (VA.getLocInfo()) {
1762 default:
1763 llvm_unreachable("Unknown loc info!");
1764 case CCValAssign::Full:
1765 llvm_unreachable("Full value assign but types don't match?");
1766 case CCValAssign::AExt:
1767 case CCValAssign::ZExt: {
1768 const TargetRegisterClass *RC =
1769 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1770 Register TmpReg = createResultReg(RC);
1771 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1772 return false;
1773 SrcReg = TmpReg;
1774 break;
1775 }
1776 case CCValAssign::SExt: {
1777 const TargetRegisterClass *RC =
1778 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1779 Register TmpReg = createResultReg(RC);
1780 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1781 return false;
1782 SrcReg = TmpReg;
1783 break;
1784 }
1785 }
1786 }
1787
1788 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1789 TII.get(TargetOpcode::COPY), RetRegs[i])
1790 .addReg(SrcReg);
1791 }
1792 }
1793 }
1794
1795 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1796 TII.get(PPC::BLR8));
1797
1798 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1799 MIB.addReg(RetRegs[i], RegState::Implicit);
1800
1801 return true;
1802}
1803
1804// Attempt to emit an integer extend of SrcReg into DestReg. Both
1805// signed and zero extensions are supported. Return false if we
1806// can't handle it.
1807bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1808 unsigned DestReg, bool IsZExt) {
1809 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1810 return false;
1811 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1812 return false;
1813
1814 // Signed extensions use EXTSB, EXTSH, EXTSW.
1815 if (!IsZExt) {
1816 unsigned Opc;
1817 if (SrcVT == MVT::i8)
1818 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1819 else if (SrcVT == MVT::i16)
1820 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1821 else {
1822 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1823 Opc = PPC::EXTSW_32_64;
1824 }
1825 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1826 .addReg(SrcReg);
1827
1828 // Unsigned 32-bit extensions use RLWINM.
1829 } else if (DestVT == MVT::i32) {
1830 unsigned MB;
1831 if (SrcVT == MVT::i8)
1832 MB = 24;
1833 else {
1834 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1835 MB = 16;
1836 }
1837 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::RLWINM),
1838 DestReg)
1839 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1840
1841 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1842 } else {
1843 unsigned MB;
1844 if (SrcVT == MVT::i8)
1845 MB = 56;
1846 else if (SrcVT == MVT::i16)
1847 MB = 48;
1848 else
1849 MB = 32;
1850 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1851 TII.get(PPC::RLDICL_32_64), DestReg)
1852 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1853 }
1854
1855 return true;
1856}
1857
1858// Attempt to fast-select an indirect branch instruction.
1859bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1860 Register AddrReg = getRegForValue(I->getOperand(0));
1861 if (AddrReg == 0)
1862 return false;
1863
1864 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::MTCTR8))
1865 .addReg(AddrReg);
1866 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::BCTR8));
1867
1868 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1869 for (const BasicBlock *SuccBB : IB->successors())
1870 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1871
1872 return true;
1873}
1874
1875// Attempt to fast-select an integer truncate instruction.
1876bool PPCFastISel::SelectTrunc(const Instruction *I) {
1877 Value *Src = I->getOperand(0);
1878 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1879 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1880
1881 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1882 return false;
1883
1884 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1885 return false;
1886
1887 Register SrcReg = getRegForValue(Src);
1888 if (!SrcReg)
1889 return false;
1890
1891 // The only interesting case is when we need to switch register classes.
1892 if (SrcVT == MVT::i64)
1893 SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
1894
1895 updateValueMap(I, SrcReg);
1896 return true;
1897}
1898
1899// Attempt to fast-select an integer extend instruction.
1900bool PPCFastISel::SelectIntExt(const Instruction *I) {
1901 Type *DestTy = I->getType();
1902 Value *Src = I->getOperand(0);
1903 Type *SrcTy = Src->getType();
1904
1905 bool IsZExt = isa<ZExtInst>(I);
1906 Register SrcReg = getRegForValue(Src);
1907 if (!SrcReg) return false;
1908
1909 EVT SrcEVT, DestEVT;
1910 SrcEVT = TLI.getValueType(DL, SrcTy, true);
1911 DestEVT = TLI.getValueType(DL, DestTy, true);
1912 if (!SrcEVT.isSimple())
1913 return false;
1914 if (!DestEVT.isSimple())
1915 return false;
1916
1917 MVT SrcVT = SrcEVT.getSimpleVT();
1918 MVT DestVT = DestEVT.getSimpleVT();
1919
1920 // If we know the register class needed for the result of this
1921 // instruction, use it. Otherwise pick the register class of the
1922 // correct size that does not contain X0/R0, since we don't know
1923 // whether downstream uses permit that assignment.
1924 Register AssignedReg = FuncInfo.ValueMap[I];
1925 const TargetRegisterClass *RC =
1926 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1927 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1928 &PPC::GPRC_and_GPRC_NOR0RegClass));
1929 Register ResultReg = createResultReg(RC);
1930
1931 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1932 return false;
1933
1934 updateValueMap(I, ResultReg);
1935 return true;
1936}
1937
1938// Attempt to fast-select an instruction that wasn't handled by
1939// the table-generated machinery.
1940bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1941
1942 switch (I->getOpcode()) {
1943 case Instruction::Load:
1944 return SelectLoad(I);
1945 case Instruction::Store:
1946 return SelectStore(I);
1947 case Instruction::Br:
1948 return SelectBranch(I);
1949 case Instruction::IndirectBr:
1950 return SelectIndirectBr(I);
1951 case Instruction::FPExt:
1952 return SelectFPExt(I);
1953 case Instruction::FPTrunc:
1954 return SelectFPTrunc(I);
1955 case Instruction::SIToFP:
1956 return SelectIToFP(I, /*IsSigned*/ true);
1957 case Instruction::UIToFP:
1958 return SelectIToFP(I, /*IsSigned*/ false);
1959 case Instruction::FPToSI:
1960 return SelectFPToI(I, /*IsSigned*/ true);
1961 case Instruction::FPToUI:
1962 return SelectFPToI(I, /*IsSigned*/ false);
1963 case Instruction::Add:
1964 return SelectBinaryIntOp(I, ISD::ADD);
1965 case Instruction::Or:
1966 return SelectBinaryIntOp(I, ISD::OR);
1967 case Instruction::Sub:
1968 return SelectBinaryIntOp(I, ISD::SUB);
1969 case Instruction::Ret:
1970 return SelectRet(I);
1971 case Instruction::Trunc:
1972 return SelectTrunc(I);
1973 case Instruction::ZExt:
1974 case Instruction::SExt:
1975 return SelectIntExt(I);
1976 // Here add other flavors of Instruction::XXX that automated
1977 // cases don't catch. For example, switches are terminators
1978 // that aren't yet handled.
1979 default:
1980 break;
1981 }
1982 return false;
1983}
1984
1985// Materialize a floating-point constant into a register, and return
1986// the register number (or zero if we failed to handle it).
1987unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1988 // If this is a PC-Rel function, let SDISel handle constant pool.
1989 if (Subtarget->isUsingPCRelativeCalls())
1990 return false;
1991
1992 // No plans to handle long double here.
1993 if (VT != MVT::f32 && VT != MVT::f64)
1994 return 0;
1995
1996 // All FP constants are loaded from the constant pool.
1997 Align Alignment = DL.getPrefTypeAlign(CFP->getType());
1998 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Alignment);
1999 const bool HasSPE = Subtarget->hasSPE();
2000 const TargetRegisterClass *RC;
2001 if (HasSPE)
2002 RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
2003 else
2004 RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2005
2006 Register DestReg = createResultReg(RC);
2007 CodeModel::Model CModel = TM.getCodeModel();
2008
2009 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2011 MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Alignment);
2012
2013 unsigned Opc;
2014
2015 if (HasSPE)
2016 Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2017 else
2018 Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
2019
2020 Register TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2021
2022 PPCFuncInfo->setUsesTOCBasePtr();
2023 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
2024 if (CModel == CodeModel::Small) {
2025 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtocCPT),
2026 TmpReg)
2027 .addConstantPoolIndex(Idx).addReg(PPC::X2);
2028 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
2029 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2030 } else {
2031 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)).
2032 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDIStocHA8),
2033 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
2034 // But for large code model, we must generate a LDtocL followed
2035 // by the LF[SD].
2036 if (CModel == CodeModel::Large) {
2037 Register TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2038 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtocL),
2039 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
2040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
2041 .addImm(0)
2042 .addReg(TmpReg2);
2043 } else
2044 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
2046 .addReg(TmpReg)
2047 .addMemOperand(MMO);
2048 }
2049
2050 return DestReg;
2051}
2052
2053// Materialize the address of a global value into a register, and return
2054// the register number (or zero if we failed to handle it).
2055unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
2056 // If this is a PC-Rel function, let SDISel handle GV materialization.
2057 if (Subtarget->isUsingPCRelativeCalls())
2058 return false;
2059
2060 assert(VT == MVT::i64 && "Non-address!");
2061 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2062 Register DestReg = createResultReg(RC);
2063
2064 // Global values may be plain old object addresses, TLS object
2065 // addresses, constant pool entries, or jump tables. How we generate
2066 // code for these may depend on small, medium, or large code model.
2067 CodeModel::Model CModel = TM.getCodeModel();
2068
2069 // FIXME: Jump tables are not yet required because fast-isel doesn't
2070 // handle switches; if that changes, we need them as well. For now,
2071 // what follows assumes everything's a generic (or TLS) global address.
2072
2073 // FIXME: We don't yet handle the complexity of TLS.
2074 if (GV->isThreadLocal())
2075 return 0;
2076
2077 PPCFuncInfo->setUsesTOCBasePtr();
2078 bool IsAIXTocData = TM.getTargetTriple().isOSAIX() &&
2079 isa<GlobalVariable>(GV) &&
2080 cast<GlobalVariable>(GV)->hasAttribute("toc-data");
2081
2082 // For small code model, generate a simple TOC load.
2083 if (CModel == CodeModel::Small) {
2084 auto MIB = BuildMI(
2085 *FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2086 IsAIXTocData ? TII.get(PPC::ADDItoc8) : TII.get(PPC::LDtoc), DestReg);
2087 if (IsAIXTocData)
2088 MIB.addReg(PPC::X2).addGlobalAddress(GV);
2089 else
2090 MIB.addGlobalAddress(GV).addReg(PPC::X2);
2091 } else {
2092 // If the address is an externally defined symbol, a symbol with common
2093 // or externally available linkage, a non-local function address, or a
2094 // jump table address (not yet needed), or if we are generating code
2095 // for large code model, we generate:
2096 // LDtocL(GV, ADDIStocHA8(%x2, GV))
2097 // Otherwise we generate:
2098 // ADDItocL8(ADDIStocHA8(%x2, GV), GV)
2099 // Either way, start with the ADDIStocHA8:
2100 Register HighPartReg = createResultReg(RC);
2101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDIStocHA8),
2102 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
2103
2104 if (Subtarget->isGVIndirectSymbol(GV)) {
2105 assert(!IsAIXTocData && "TOC data should always be direct.");
2106 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtocL),
2107 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
2108 } else {
2109 // Otherwise generate the ADDItocL8.
2110 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDItocL8),
2111 DestReg)
2112 .addReg(HighPartReg)
2113 .addGlobalAddress(GV);
2114 }
2115 }
2116
2117 return DestReg;
2118}
2119
2120// Materialize a 32-bit integer constant into a register, and return
2121// the register number (or zero if we failed to handle it).
2122unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2123 const TargetRegisterClass *RC) {
2124 unsigned Lo = Imm & 0xFFFF;
2125 unsigned Hi = (Imm >> 16) & 0xFFFF;
2126
2127 Register ResultReg = createResultReg(RC);
2128 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2129
2130 if (isInt<16>(Imm))
2131 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2132 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2133 .addImm(Imm);
2134 else if (Lo) {
2135 // Both Lo and Hi have nonzero bits.
2136 Register TmpReg = createResultReg(RC);
2137 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2138 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2139 .addImm(Hi);
2140 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2141 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2142 .addReg(TmpReg).addImm(Lo);
2143 } else
2144 // Just Hi bits.
2145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2146 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2147 .addImm(Hi);
2148
2149 return ResultReg;
2150}
2151
2152// Materialize a 64-bit integer constant into a register, and return
2153// the register number (or zero if we failed to handle it).
2154unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2155 const TargetRegisterClass *RC) {
2156 unsigned Remainder = 0;
2157 unsigned Shift = 0;
2158
2159 // If the value doesn't fit in 32 bits, see if we can shift it
2160 // so that it fits in 32 bits.
2161 if (!isInt<32>(Imm)) {
2162 Shift = llvm::countr_zero<uint64_t>(Imm);
2163 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2164
2165 if (isInt<32>(ImmSh))
2166 Imm = ImmSh;
2167 else {
2168 Remainder = Imm;
2169 Shift = 32;
2170 Imm >>= 32;
2171 }
2172 }
2173
2174 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2175 // (if not shifted).
2176 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2177 if (!Shift)
2178 return TmpReg1;
2179
2180 // If upper 32 bits were not zero, we've built them and need to shift
2181 // them into place.
2182 unsigned TmpReg2;
2183 if (Imm) {
2184 TmpReg2 = createResultReg(RC);
2185 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::RLDICR),
2186 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2187 } else
2188 TmpReg2 = TmpReg1;
2189
2190 unsigned TmpReg3, Hi, Lo;
2191 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2192 TmpReg3 = createResultReg(RC);
2193 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ORIS8),
2194 TmpReg3).addReg(TmpReg2).addImm(Hi);
2195 } else
2196 TmpReg3 = TmpReg2;
2197
2198 if ((Lo = Remainder & 0xFFFF)) {
2199 Register ResultReg = createResultReg(RC);
2200 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ORI8),
2201 ResultReg).addReg(TmpReg3).addImm(Lo);
2202 return ResultReg;
2203 }
2204
2205 return TmpReg3;
2206}
2207
2208// Materialize an integer constant into a register, and return
2209// the register number (or zero if we failed to handle it).
2210unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
2211 bool UseSExt) {
2212 // If we're using CR bit registers for i1 values, handle that as a special
2213 // case first.
2214 if (VT == MVT::i1 && Subtarget->useCRBits()) {
2215 Register ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2216 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2217 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2218 return ImmReg;
2219 }
2220
2221 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2222 VT != MVT::i1)
2223 return 0;
2224
2225 const TargetRegisterClass *RC =
2226 ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2227 int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
2228
2229 // If the constant is in range, use a load-immediate.
2230 // Since LI will sign extend the constant we need to make sure that for
2231 // our zeroext constants that the sign extended constant fits into 16-bits -
2232 // a range of 0..0x7fff.
2233 if (isInt<16>(Imm)) {
2234 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2235 Register ImmReg = createResultReg(RC);
2236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ImmReg)
2237 .addImm(Imm);
2238 return ImmReg;
2239 }
2240
2241 // Construct the constant piecewise.
2242 if (VT == MVT::i64)
2243 return PPCMaterialize64BitInt(Imm, RC);
2244 else if (VT == MVT::i32)
2245 return PPCMaterialize32BitInt(Imm, RC);
2246
2247 return 0;
2248}
2249
2250// Materialize a constant into a register, and return the register
2251// number (or zero if we failed to handle it).
2252unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2253 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2254
2255 // Only handle simple types.
2256 if (!CEVT.isSimple()) return 0;
2257 MVT VT = CEVT.getSimpleVT();
2258
2259 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2260 return PPCMaterializeFP(CFP, VT);
2261 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2262 return PPCMaterializeGV(GV, VT);
2263 else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2264 // Note that the code in FunctionLoweringInfo::ComputePHILiveOutRegInfo
2265 // assumes that constant PHI operands will be zero extended, and failure to
2266 // match that assumption will cause problems if we sign extend here but
2267 // some user of a PHI is in a block for which we fall back to full SDAG
2268 // instruction selection.
2269 return PPCMaterializeInt(CI, VT, false);
2270
2271 return 0;
2272}
2273
2274// Materialize the address created by an alloca into a register, and
2275// return the register number (or zero if we failed to handle it).
2276unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2277 // Don't handle dynamic allocas.
2278 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2279
2280 MVT VT;
2281 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2282
2284 FuncInfo.StaticAllocaMap.find(AI);
2285
2286 if (SI != FuncInfo.StaticAllocaMap.end()) {
2287 Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDI8),
2289 ResultReg).addFrameIndex(SI->second).addImm(0);
2290 return ResultReg;
2291 }
2292
2293 return 0;
2294}
2295
2296// Fold loads into extends when possible.
2297// FIXME: We can have multiple redundant extend/trunc instructions
2298// following a load. The folding only picks up one. Extend this
2299// to check subsequent instructions for the same pattern and remove
2300// them. Thus ResultReg should be the def reg for the last redundant
2301// instruction in a chain, and all intervening instructions can be
2302// removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2303// to add ELF64-NOT: rldicl to the appropriate tests when this works.
2304bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2305 const LoadInst *LI) {
2306 // Verify we have a legal type before going any further.
2307 MVT VT;
2308 if (!isLoadTypeLegal(LI->getType(), VT))
2309 return false;
2310
2311 // Combine load followed by zero- or sign-extend.
2312 bool IsZExt = false;
2313 switch(MI->getOpcode()) {
2314 default:
2315 return false;
2316
2317 case PPC::RLDICL:
2318 case PPC::RLDICL_32_64: {
2319 IsZExt = true;
2320 unsigned MB = MI->getOperand(3).getImm();
2321 if ((VT == MVT::i8 && MB <= 56) ||
2322 (VT == MVT::i16 && MB <= 48) ||
2323 (VT == MVT::i32 && MB <= 32))
2324 break;
2325 return false;
2326 }
2327
2328 case PPC::RLWINM:
2329 case PPC::RLWINM8: {
2330 IsZExt = true;
2331 unsigned MB = MI->getOperand(3).getImm();
2332 if ((VT == MVT::i8 && MB <= 24) ||
2333 (VT == MVT::i16 && MB <= 16))
2334 break;
2335 return false;
2336 }
2337
2338 case PPC::EXTSB:
2339 case PPC::EXTSB8:
2340 case PPC::EXTSB8_32_64:
2341 /* There is no sign-extending load-byte instruction. */
2342 return false;
2343
2344 case PPC::EXTSH:
2345 case PPC::EXTSH8:
2346 case PPC::EXTSH8_32_64: {
2347 if (VT != MVT::i16 && VT != MVT::i8)
2348 return false;
2349 break;
2350 }
2351
2352 case PPC::EXTSW:
2353 case PPC::EXTSW_32:
2354 case PPC::EXTSW_32_64: {
2355 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2356 return false;
2357 break;
2358 }
2359 }
2360
2361 // See if we can handle this address.
2362 Address Addr;
2363 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2364 return false;
2365
2366 Register ResultReg = MI->getOperand(0).getReg();
2367
2368 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,
2369 Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
2370 return false;
2371
2373 removeDeadCode(I, std::next(I));
2374 return true;
2375}
2376
2377// Attempt to lower call arguments in a faster way than done by
2378// the selection DAG code.
2379bool PPCFastISel::fastLowerArguments() {
2380 // Defer to normal argument lowering for now. It's reasonably
2381 // efficient. Consider doing something like ARM to handle the
2382 // case where all args fit in registers, no varargs, no float
2383 // or vector args.
2384 return false;
2385}
2386
2387// Handle materializing integer constants into a register. This is not
2388// automatically generated for PowerPC, so must be explicitly created here.
2389unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2390
2391 if (Opc != ISD::Constant)
2392 return 0;
2393
2394 // If we're using CR bit registers for i1 values, handle that as a special
2395 // case first.
2396 if (VT == MVT::i1 && Subtarget->useCRBits()) {
2397 Register ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2398 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2399 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2400 return ImmReg;
2401 }
2402
2403 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2404 VT != MVT::i1)
2405 return 0;
2406
2407 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2408 &PPC::GPRCRegClass);
2409 if (VT == MVT::i64)
2410 return PPCMaterialize64BitInt(Imm, RC);
2411 else
2412 return PPCMaterialize32BitInt(Imm, RC);
2413}
2414
2415// Override for ADDI and ADDI8 to set the correct register class
2416// on RHS operand 0. The automatic infrastructure naively assumes
2417// GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2418// for these cases. At the moment, none of the other automatically
2419// generated RI instructions require special treatment. However, once
2420// SelectSelect is implemented, "isel" requires similar handling.
2421//
2422// Also be conservative about the output register class. Avoid
2423// assigning R0 or X0 to the output register for GPRC and G8RC
2424// register classes, as any such result could be used in ADDI, etc.,
2425// where those regs have another meaning.
2426unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2427 const TargetRegisterClass *RC,
2428 unsigned Op0,
2429 uint64_t Imm) {
2430 if (MachineInstOpcode == PPC::ADDI)
2431 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2432 else if (MachineInstOpcode == PPC::ADDI8)
2433 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2434
2435 const TargetRegisterClass *UseRC =
2436 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2437 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2438
2439 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm);
2440}
2441
2442// Override for instructions with one register operand to avoid use of
2443// R0/X0. The automatic infrastructure isn't aware of the context so
2444// we must be conservative.
2445unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2446 const TargetRegisterClass* RC,
2447 unsigned Op0) {
2448 const TargetRegisterClass *UseRC =
2449 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2450 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2451
2452 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0);
2453}
2454
2455// Override for instructions with two register operands to avoid use
2456// of R0/X0. The automatic infrastructure isn't aware of the context
2457// so we must be conservative.
2458unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2459 const TargetRegisterClass* RC,
2460 unsigned Op0, unsigned Op1) {
2461 const TargetRegisterClass *UseRC =
2462 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2463 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2464
2465 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op1);
2466}
2467
2468namespace llvm {
2469 // Create the fast instruction selector for PowerPC64 ELF.
2471 const TargetLibraryInfo *LibInfo) {
2472 // Only available on 64-bit for now.
2473 const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2474 if (Subtarget.isPPC64())
2475 return new PPCFastISel(FuncInfo, LibInfo);
2476 return nullptr;
2477 }
2478}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
This file defines the FastISel class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
static std::optional< PPC::Predicate > getComparePred(CmpInst::Predicate Pred)
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
support::ulittle16_t & Lo
Definition: aarch32.cpp:206
support::ulittle16_t & Hi
Definition: aarch32.cpp:205
Class for arbitrary precision integers.
Definition: APInt.h:77
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1499
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1521
an instruction to allocate memory on the stack
Definition: Instructions.h:60
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:108
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
Conditional or Unconditional Branch instruction.
BasicBlock * getSuccessor(unsigned i) const
Value * getCondition() const
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool needsCustom() const
unsigned getValNo() const
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:983
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:993
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:996
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:1010
@ ICMP_SLT
signed less than
Definition: InstrTypes.h:1022
@ ICMP_SLE
signed less or equal
Definition: InstrTypes.h:1023
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:999
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:1008
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:997
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:998
@ ICMP_UGE
unsigned greater or equal
Definition: InstrTypes.h:1017
@ ICMP_UGT
unsigned greater than
Definition: InstrTypes.h:1016
@ ICMP_SGT
signed greater than
Definition: InstrTypes.h:1020
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:1007
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:1001
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:1004
@ ICMP_ULT
unsigned less than
Definition: InstrTypes.h:1018
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:1005
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:1000
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:1002
@ ICMP_EQ
equal
Definition: InstrTypes.h:1014
@ ICMP_NE
not equal
Definition: InstrTypes.h:1015
@ ICMP_SGE
signed greater or equal
Definition: InstrTypes.h:1021
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:1009
@ ICMP_ULE
unsigned less or equal
Definition: InstrTypes.h:1019
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:1006
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:995
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:1003
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:1084
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:269
This is the shared class of boolean and integer constants.
Definition: Constants.h:81
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:206
static ConstantInt * getSigned(IntegerType *Ty, int64_t V)
Return a ConstantInt with the specified value for the specified type.
Definition: Constants.h:124
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:161
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:155
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
Register fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0)
Emit a MachineInstr with one register operand and a result register in the given register class.
Definition: FastISel.cpp:2046
virtual bool tryToFoldLoadIntoMI(MachineInstr *, unsigned, const LoadInst *)
The specified machine instr operand is a vreg, and that vreg is being provided by the specified load ...
Definition: FastISel.h:300
virtual unsigned fastMaterializeConstant(const Constant *C)
Emit a constant in a register using target-specific logic, such as constant pool loads.
Definition: FastISel.h:473
virtual bool fastLowerCall(CallLoweringInfo &CLI)
This method is called by target-independent code to do target- specific call lowering.
Definition: FastISel.cpp:1946
Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1)
Emit a MachineInstr with two register operands and a result register in the given register class.
Definition: FastISel.cpp:2067
Register createResultReg(const TargetRegisterClass *RC)
Definition: FastISel.cpp:2016
virtual bool fastLowerArguments()
This method is called by target-independent code to do target- specific argument lowering.
Definition: FastISel.cpp:1944
const TargetInstrInfo & TII
Definition: FastISel.h:211
virtual bool fastSelectInstruction(const Instruction *I)=0
This method is called by target-independent code when the normal FastISel process fails to select an ...
const TargetLowering & TLI
Definition: FastISel.h:212
const TargetMachine & TM
Definition: FastISel.h:209
Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:2118
virtual unsigned fastMaterializeAlloca(const AllocaInst *C)
Emit an alloca address in a register using target-specific logic.
Definition: FastISel.h:476
virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1963
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
MachineBasicBlock * MBB
MBB - The current block.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:358
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:262
Indirect Branch Instruction.
const BasicBlock * getParent() const
Definition: Instruction.h:152
Class to represent integer types.
Definition: DerivedTypes.h:40
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:185
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Machine Value Type.
SimpleValueType SimpleTy
bool isVector() const
Return true if this is a vector value type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:146
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:145
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Return a value (possibly void), from a function.
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void reserve(size_type N)
Definition: SmallVector.h:676
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:622
TypeSize getElementOffset(unsigned Idx) const
Definition: DataLayout.h:651
Class to represent struct types.
Definition: DerivedTypes.h:216
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
unsigned getID() const
Return the register class ID number.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static IntegerType * getInt64Ty(LLVMContext &C)
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
Value * getOperand(unsigned i) const
Definition: User.h:169
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
TypeSize getSequentialElementStride(const DataLayout &DL) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:240
@ MO_TOC_LO
Definition: PPC.h:185
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
gep_type_iterator gep_type_begin(const User *GEP)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:136
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:306
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.