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22 #define GET_REGINFO_TARGET_DESC
23 #include "SystemZGenRegisterInfo.inc"
32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35 return &SystemZ::GR32BitRegClass;
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39 return &SystemZ::GRH32BitRegClass;
43 if (SystemZ::GR32BitRegClass.
contains(PhysReg))
44 return &SystemZ::GR32BitRegClass;
46 "Phys reg not in GR32 or GRH32?");
47 return &SystemZ::GRH32BitRegClass;
50 assert (RC == &SystemZ::GRX32BitRegClass);
62 CopyHints.
insert(Hints.begin(), Hints.end());
83 VirtReg, Order, Hints, MF, VRM,
Matrix);
93 if (VirtReg ==
Use.getOperand(0).getReg()) {
94 VRRegMO = &
Use.getOperand(0);
95 OtherMO = &
Use.getOperand(1);
96 if (
Use.isCommutable())
97 CommuMO = &
Use.getOperand(2);
98 }
else if (VirtReg ==
Use.getOperand(1).getReg()) {
99 VRRegMO = &
Use.getOperand(1);
100 OtherMO = &
Use.getOperand(0);
101 }
else if (VirtReg ==
Use.getOperand(2).getReg() &&
102 Use.isCommutable()) {
103 VRRegMO = &
Use.getOperand(2);
104 OtherMO = &
Use.getOperand(0);
115 PhysReg = getSubReg(PhysReg, MO->getSubReg());
117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->
getSubReg(),
120 TwoAddrHints.
insert(PhysReg);
128 if (TwoAddrHints.
count(OrderReg))
129 Hints.push_back(OrderReg);
135 Worklist.push_back(VirtReg);
136 while (Worklist.size()) {
146 if (
Use.getOpcode() == SystemZ::LOCRMux ||
147 Use.getOpcode() == SystemZ::SELRMux) {
153 if (
Use.getOpcode() == SystemZ::SELRMux)
156 if (RC && RC != &SystemZ::GRX32BitRegClass) {
168 Worklist.push_back(OtherReg);
170 else if (
Use.getOpcode() == SystemZ::CHIMux ||
171 Use.getOpcode() == SystemZ::CFIMux) {
172 if (
Use.getOperand(1).getImm() == 0) {
173 bool OnlyLMuxes =
true;
175 if (
DefMI.getOpcode() != SystemZ::LMux)
178 addHints(Order, Hints, &SystemZ::GR32BitRegClass,
MRI);
188 return BaseImplRetVal;
194 return Subtarget.
hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList
195 : CSR_SystemZ_XPLINK64_SaveList;
202 return CSR_SystemZ_NoRegs_SaveList;
204 return Subtarget.
hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
205 : CSR_SystemZ_AllRegs_SaveList;
208 Attribute::SwiftError))
209 return CSR_SystemZ_SwiftError_SaveList;
210 return CSR_SystemZ_ELF_SaveList;
217 return Subtarget.
hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask
218 : CSR_SystemZ_XPLINK64_RegMask;
226 return CSR_SystemZ_NoRegs_RegMask;
228 return Subtarget.
hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
229 : CSR_SystemZ_AllRegs_RegMask;
232 Attribute::SwiftError))
233 return CSR_SystemZ_SwiftError_RegMask;
234 return CSR_SystemZ_ELF_RegMask;
276 Reserved.
set(SystemZ::A0);
277 Reserved.
set(SystemZ::A1);
280 Reserved.
set(SystemZ::FPC);
287 int SPAdj,
unsigned FIOperandNum,
289 assert(SPAdj == 0 &&
"Outgoing arguments should be part of the frame");
299 int FrameIndex =
MI->getOperand(FIOperandNum).getIndex();
303 MI->getOperand(FIOperandNum + 1).getImm());
306 if (
MI->isDebugValue()) {
307 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr,
false);
308 if (
MI->isNonListDebugValue()) {
309 MI->getDebugOffset().ChangeToImmediate(Offset);
311 unsigned OpIdx =
MI->getDebugOperandIndex(&
MI->getOperand(FIOperandNum));
315 MI->getDebugExpressionOp().setMetadata(
323 unsigned Opcode =
MI->getOpcode();
324 unsigned OpcodeForOffset =
TII->getOpcodeForOffset(Opcode, Offset);
325 if (OpcodeForOffset) {
329 OpcodeForOffset = SystemZ::LDE32;
331 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr,
false);
336 int64_t OldOffset = Offset;
337 int64_t
Mask = 0xffff;
339 Offset = OldOffset &
Mask;
340 OpcodeForOffset =
TII->getOpcodeForOffset(Opcode, Offset);
343 }
while (!OpcodeForOffset);
347 int64_t HighOffset = OldOffset - Offset;
350 &&
MI->getOperand(FIOperandNum + 2).getReg() == 0) {
353 TII->loadImmediate(
MBB,
MI, ScratchReg, HighOffset);
354 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr,
false);
355 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
359 unsigned LAOpcode =
TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
366 TII->loadImmediate(
MBB,
MI, ScratchReg, HighOffset);
372 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
376 MI->setDesc(
TII->get(OpcodeForOffset));
377 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
387 assert (
MI->isCopy() &&
"Only expecting COPY instructions");
391 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
398 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
399 Register GR128Reg =
MI->getOperand(WideOpNo).getReg();
412 if ((!FirstMI_GR128 || FirstMI_GR128->
getParent() !=
MBB) ||
413 (!FirstMI_GRNar || FirstMI_GRNar->
getParent() !=
MBB) ||
431 for (; MII != MEE; ++MII) {
437 PhysClobbered.
set(*
SI);
444 unsigned const DemandedFreeGR128 = 3;
457 return TFI->
hasFP(MF) ? Regs->getFramePointerRegister()
458 : Regs->getStackPointerRegister();
463 if (RC == &SystemZ::CCRRegClass)
464 return &SystemZ::GR32BitRegClass;
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override final
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SystemZRegisterInfo(unsigned int RA)
virtual const TargetInstrInfo * getInstrInfo() const
return AArch64::GPR64RegClass contains(Reg)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void addHints(ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const TargetRegisterClass *RC, const MachineRegisterInfo *MRI)
Register getFrameRegister(const MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
LLVM_NODISCARD T pop_back_val()
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned const TargetRegisterInfo * TRI
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
const SystemZRegisterInfo * getRegisterInfo() const override
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
size_type count() const
count - Returns the number of bits which are set.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override final
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override final
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
AttributeList getAttributes() const
Return the attribute list for this Function.
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Representation of each machine instruction.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StandardInstrumentations SI(Debug, VerifyEach)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
MCSuperRegIterator enumerates all super-registers of Reg.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
SI optimize exec mask operations pre RA
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const =0
LiveInterval & getInterval(Register Reg)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
const MachineBasicBlock * getParent() const
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
static StackOffset getFixed(ScalarTy Fixed)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
A SystemZ-specific class detailing special use registers particular for calling conventions.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
unsigned getNumRegs() const
Return the number of registers in this class.
Function & getFunction()
Return the LLVM function that this machine code represents.
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
int getTwoOperandOpcode(uint16_t Opcode)
virtual const TargetLowering * getTargetLowering() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBuilder MachineInstrBuilder & DefMI
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
@ Kill
The last use of a register.
SystemZCallingConventionRegisters * getSpecialRegisters() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override final
MCRegAliasIterator enumerates all registers aliasing Reg.
A Use represents the edge between a Value definition and its users.