LLVM 19.0.0git
SystemZRegisterInfo.cpp
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1//===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "SystemZInstrInfo.h"
11#include "SystemZSubtarget.h"
12#include "llvm/ADT/SmallSet.h"
19
20using namespace llvm;
21
22#define GET_REGINFO_TARGET_DESC
23#include "SystemZGenRegisterInfo.inc"
24
25// Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
26// somehow belongs in it. Otherwise, return GRX32.
28 const VirtRegMap *VRM,
29 const MachineRegisterInfo *MRI) {
30 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
31
32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
33 MO.getSubReg() == SystemZ::subreg_ll32 ||
34 MO.getSubReg() == SystemZ::subreg_l32)
35 return &SystemZ::GR32BitRegClass;
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
37 MO.getSubReg() == SystemZ::subreg_lh32 ||
38 MO.getSubReg() == SystemZ::subreg_h32)
39 return &SystemZ::GRH32BitRegClass;
40
41 if (VRM && VRM->hasPhys(MO.getReg())) {
42 Register PhysReg = VRM->getPhys(MO.getReg());
43 if (SystemZ::GR32BitRegClass.contains(PhysReg))
44 return &SystemZ::GR32BitRegClass;
45 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
46 "Phys reg not in GR32 or GRH32?");
47 return &SystemZ::GRH32BitRegClass;
48 }
49
50 assert (RC == &SystemZ::GRX32BitRegClass);
51 return RC;
52}
53
54// Pass the registers of RC as hints while making sure that if any of these
55// registers are copy hints (and therefore already in Hints), hint them
56// first.
57static void addHints(ArrayRef<MCPhysReg> Order,
59 const TargetRegisterClass *RC,
60 const MachineRegisterInfo *MRI) {
61 SmallSet<unsigned, 4> CopyHints;
62 CopyHints.insert(Hints.begin(), Hints.end());
63 Hints.clear();
64 for (MCPhysReg Reg : Order)
65 if (CopyHints.count(Reg) &&
66 RC->contains(Reg) && !MRI->isReserved(Reg))
67 Hints.push_back(Reg);
68 for (MCPhysReg Reg : Order)
69 if (!CopyHints.count(Reg) &&
70 RC->contains(Reg) && !MRI->isReserved(Reg))
71 Hints.push_back(Reg);
72}
73
75 Register VirtReg, ArrayRef<MCPhysReg> Order,
77 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
78 const MachineRegisterInfo *MRI = &MF.getRegInfo();
79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
81
83 VirtReg, Order, Hints, MF, VRM, Matrix);
84
85 if (VRM != nullptr) {
86 // Add any two address hints after any copy hints.
87 SmallSet<unsigned, 4> TwoAddrHints;
88 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
89 if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
90 const MachineOperand *VRRegMO = nullptr;
91 const MachineOperand *OtherMO = nullptr;
92 const MachineOperand *CommuMO = nullptr;
93 if (VirtReg == Use.getOperand(0).getReg()) {
94 VRRegMO = &Use.getOperand(0);
95 OtherMO = &Use.getOperand(1);
96 if (Use.isCommutable())
97 CommuMO = &Use.getOperand(2);
98 } else if (VirtReg == Use.getOperand(1).getReg()) {
99 VRRegMO = &Use.getOperand(1);
100 OtherMO = &Use.getOperand(0);
101 } else if (VirtReg == Use.getOperand(2).getReg() &&
102 Use.isCommutable()) {
103 VRRegMO = &Use.getOperand(2);
104 OtherMO = &Use.getOperand(0);
105 } else
106 continue;
107
108 auto tryAddHint = [&](const MachineOperand *MO) -> void {
109 Register Reg = MO->getReg();
110 Register PhysReg =
111 Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
112 if (PhysReg) {
113 if (MO->getSubReg())
114 PhysReg = getSubReg(PhysReg, MO->getSubReg());
115 if (VRRegMO->getSubReg())
116 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
117 MRI->getRegClass(VirtReg));
118 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
119 TwoAddrHints.insert(PhysReg);
120 }
121 };
122 tryAddHint(OtherMO);
123 if (CommuMO)
124 tryAddHint(CommuMO);
125 }
126 for (MCPhysReg OrderReg : Order)
127 if (TwoAddrHints.count(OrderReg))
128 Hints.push_back(OrderReg);
129 }
130
131 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
133 SmallSet<Register, 4> DoneRegs;
134 Worklist.push_back(VirtReg);
135 while (Worklist.size()) {
136 Register Reg = Worklist.pop_back_val();
137 if (!DoneRegs.insert(Reg).second)
138 continue;
139
140 for (auto &Use : MRI->reg_instructions(Reg)) {
141 // For LOCRMux, see if the other operand is already a high or low
142 // register, and in that case give the corresponding hints for
143 // VirtReg. LOCR instructions need both operands in either high or
144 // low parts. Same handling for SELRMux.
145 if (Use.getOpcode() == SystemZ::LOCRMux ||
146 Use.getOpcode() == SystemZ::SELRMux) {
147 MachineOperand &TrueMO = Use.getOperand(1);
148 MachineOperand &FalseMO = Use.getOperand(2);
149 const TargetRegisterClass *RC =
150 TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
151 getRC32(TrueMO, VRM, MRI));
152 if (Use.getOpcode() == SystemZ::SELRMux)
153 RC = TRI->getCommonSubClass(RC,
154 getRC32(Use.getOperand(0), VRM, MRI));
155 if (RC && RC != &SystemZ::GRX32BitRegClass) {
156 addHints(Order, Hints, RC, MRI);
157 // Return true to make these hints the only regs available to
158 // RA. This may mean extra spilling but since the alternative is
159 // a jump sequence expansion of the LOCRMux, it is preferred.
160 return true;
161 }
162
163 // Add the other operand of the LOCRMux to the worklist.
164 Register OtherReg =
165 (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
166 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
167 Worklist.push_back(OtherReg);
168 } // end LOCRMux
169 else if (Use.getOpcode() == SystemZ::CHIMux ||
170 Use.getOpcode() == SystemZ::CFIMux) {
171 if (Use.getOperand(1).getImm() == 0) {
172 bool OnlyLMuxes = true;
173 for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
174 if (DefMI.getOpcode() != SystemZ::LMux)
175 OnlyLMuxes = false;
176 if (OnlyLMuxes) {
177 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
178 // Return false to make these hints preferred but not obligatory.
179 return false;
180 }
181 }
182 } // end CHIMux / CFIMux
183 }
184 }
185 }
186
187 return BaseImplRetVal;
188}
189
190const MCPhysReg *
192 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
193 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList
194 : CSR_SystemZ_XPLINK64_SaveList;
195}
196
197const MCPhysReg *
199 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
201 return CSR_SystemZ_NoRegs_SaveList;
203 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
204 : CSR_SystemZ_AllRegs_SaveList;
207 Attribute::SwiftError))
208 return CSR_SystemZ_SwiftError_SaveList;
209 return CSR_SystemZ_ELF_SaveList;
210}
211
212const uint32_t *
214 CallingConv::ID CC) const {
215 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
216 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask
217 : CSR_SystemZ_XPLINK64_RegMask;
218}
219
220const uint32_t *
222 CallingConv::ID CC) const {
223 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
224 if (CC == CallingConv::GHC)
225 return CSR_SystemZ_NoRegs_RegMask;
226 if (CC == CallingConv::AnyReg)
227 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
228 : CSR_SystemZ_AllRegs_RegMask;
231 Attribute::SwiftError))
232 return CSR_SystemZ_SwiftError_RegMask;
233 return CSR_SystemZ_ELF_RegMask;
234}
235
238
239const MCPhysReg *
241
242 const SystemZSubtarget *Subtarget = &MF->getSubtarget<SystemZSubtarget>();
244
245 return Regs->getCalleeSavedRegs(MF);
246}
247
248const uint32_t *
250 CallingConv::ID CC) const {
251
252 const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
254 return Regs->getCallPreservedMask(MF, CC);
255}
256
259 BitVector Reserved(getNumRegs());
260 const SystemZFrameLowering *TFI = getFrameLowering(MF);
261 const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
263 if (TFI->hasFP(MF))
264 // The frame pointer. Reserve all aliases.
265 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true);
266 AI.isValid(); ++AI)
267 Reserved.set(*AI);
268
269 // Reserve all aliases for the stack pointer.
270 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true);
271 AI.isValid(); ++AI)
272 Reserved.set(*AI);
273
274 // A0 and A1 hold the thread pointer.
275 Reserved.set(SystemZ::A0);
276 Reserved.set(SystemZ::A1);
277
278 // FPC is the floating-point control register.
279 Reserved.set(SystemZ::FPC);
280
281 return Reserved;
282}
283
284bool
286 int SPAdj, unsigned FIOperandNum,
287 RegScavenger *RS) const {
288 assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
289
290 MachineBasicBlock &MBB = *MI->getParent();
292 auto *TII = MF.getSubtarget<SystemZSubtarget>().getInstrInfo();
293 const SystemZFrameLowering *TFI = getFrameLowering(MF);
294 DebugLoc DL = MI->getDebugLoc();
295
296 // Decompose the frame index into a base and offset.
297 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
298 Register BasePtr;
299 int64_t Offset =
300 (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed() +
301 MI->getOperand(FIOperandNum + 1).getImm());
302
303 // Special handling of dbg_value instructions.
304 if (MI->isDebugValue()) {
305 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
306 if (MI->isNonListDebugValue()) {
307 MI->getDebugOffset().ChangeToImmediate(Offset);
308 } else {
309 unsigned OpIdx = MI->getDebugOperandIndex(&MI->getOperand(FIOperandNum));
312 Ops, TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed());
313 MI->getDebugExpressionOp().setMetadata(
314 DIExpression::appendOpsToArg(MI->getDebugExpression(), Ops, OpIdx));
315 }
316 return false;
317 }
318
319 // See if the offset is in range, or if an equivalent instruction that
320 // accepts the offset exists.
321 unsigned Opcode = MI->getOpcode();
322 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset, &*MI);
323 if (OpcodeForOffset) {
324 if (OpcodeForOffset == SystemZ::LE &&
325 MF.getSubtarget<SystemZSubtarget>().hasVector()) {
326 // If LE is ok for offset, use LDE instead on z13.
327 OpcodeForOffset = SystemZ::LDE32;
328 }
329 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
330 }
331 else {
332 // Create an anchor point that is in range. Start at 0xffff so that
333 // can use LLILH to load the immediate.
334 int64_t OldOffset = Offset;
335 int64_t Mask = 0xffff;
336 do {
337 Offset = OldOffset & Mask;
338 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
339 Mask >>= 1;
340 assert(Mask && "One offset must be OK");
341 } while (!OpcodeForOffset);
342
343 Register ScratchReg =
344 MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
345 int64_t HighOffset = OldOffset - Offset;
346
347 if (MI->getDesc().TSFlags & SystemZII::HasIndex
348 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
349 // Load the offset into the scratch register and use it as an index.
350 // The scratch register then dies here.
351 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
352 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
353 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
354 false, false, true);
355 } else {
356 // Load the anchor address into a scratch register.
357 unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
358 if (LAOpcode)
359 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
360 .addReg(BasePtr).addImm(HighOffset).addReg(0);
361 else {
362 // Load the high offset into the scratch register and use it as
363 // an index.
364 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
365 BuildMI(MBB, MI, DL, TII->get(SystemZ::LA), ScratchReg)
366 .addReg(BasePtr, RegState::Kill).addImm(0).addReg(ScratchReg);
367 }
368
369 // Use the scratch register as the base. It then dies here.
370 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
371 false, false, true);
372 }
373 }
374 MI->setDesc(TII->get(OpcodeForOffset));
375 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
376 return false;
377}
378
380 const TargetRegisterClass *SrcRC,
381 unsigned SubReg,
382 const TargetRegisterClass *DstRC,
383 unsigned DstSubReg,
384 const TargetRegisterClass *NewRC,
385 LiveIntervals &LIS) const {
386 assert (MI->isCopy() && "Only expecting COPY instructions");
387
388 // Coalesce anything which is not a COPY involving a subreg to/from GR128.
389 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
390 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64) &&
391 !MI->getOperand(1).isUndef()))
392 return true;
393
394 // Allow coalescing of a GR128 subreg COPY only if the subreg liverange is
395 // local to one MBB with not too many interferring physreg clobbers. Otherwise
396 // regalloc may run out of registers.
397 unsigned SubregOpIdx = getRegSizeInBits(*SrcRC) == 128 ? 0 : 1;
398 LiveInterval &LI = LIS.getInterval(MI->getOperand(SubregOpIdx).getReg());
399
400 // Check that the subreg is local to MBB.
401 MachineBasicBlock *MBB = MI->getParent();
404 if (!FirstMI || FirstMI->getParent() != MBB ||
405 !LastMI || LastMI->getParent() != MBB)
406 return false;
407
408 // Check if coalescing seems safe by finding the set of clobbered physreg
409 // pairs in the region.
410 BitVector PhysClobbered(getNumRegs());
411 for (MachineBasicBlock::iterator MII = FirstMI,
412 MEE = std::next(LastMI->getIterator());
413 MII != MEE; ++MII)
414 for (const MachineOperand &MO : MII->operands())
415 if (MO.isReg() && MO.getReg().isPhysical()) {
416 for (MCPhysReg SI : superregs_inclusive(MO.getReg()))
417 if (NewRC->contains(SI)) {
418 PhysClobbered.set(SI);
419 break;
420 }
421 }
422
423 // Demand an arbitrary margin of free regs.
424 unsigned const DemandedFreeGR128 = 3;
425 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
426 return false;
427
428 return true;
429}
430
433 const SystemZFrameLowering *TFI = getFrameLowering(MF);
434 const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
436
437 return TFI->hasFP(MF) ? Regs->getFramePointerRegister()
438 : Regs->getStackPointerRegister();
439}
440
443 if (RC == &SystemZ::CCRRegClass)
444 return &SystemZ::GR32BitRegClass;
445 return RC;
446}
447
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Live Register Matrix
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file defines the SmallSet class.
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
static void addHints(ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const TargetRegisterClass *RC, const MachineRegisterInfo *MRI)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:162
BitVector & set()
Definition: BitVector.h:351
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
A debug info location.
Definition: DebugLoc.h:33
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:264
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:340
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
LiveInterval & getInterval(Register Reg)
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:385
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:392
MCRegAliasIterator enumerates all registers aliasing Reg.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:343
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
static StackOffset getFixed(int64_t Fixed)
Definition: TypeSize.h:42
A SystemZ-specific class detailing special use registers particular for calling conventions.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const =0
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const final
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const final
SystemZCallingConventionRegisters * getSpecialRegisters() const
const SystemZRegisterInfo * getRegisterInfo() const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const final
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const final
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
unsigned getNumRegs() const
Return the number of registers in this class.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual const TargetLowering * getTargetLowering() const
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:99
self_iterator getIterator()
Definition: ilist_node.h:132
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
Definition: CallingConv.h:60
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
@ Kill
The last use of a register.
int getTwoOperandOpcode(uint16_t Opcode)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1879
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Register getFrameRegister(const MachineFunction &MF) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...