LLVM 19.0.0git
CSKYFrameLowering.cpp
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1//===-- CSKYFrameLowering.cpp - CSKY Frame Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the CSKY implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "CSKYFrameLowering.h"
15#include "CSKYSubtarget.h"
23#include "llvm/MC/MCDwarf.h"
24
25using namespace llvm;
26
27#define DEBUG_TYPE "csky-frame-lowering"
28
29// Returns the register used to hold the frame pointer.
30static Register getFPReg(const CSKYSubtarget &STI) { return CSKY::R8; }
31
32// To avoid the BP value clobbered by a function call, we need to choose a
33// callee saved register to save the value.
34static Register getBPReg(const CSKYSubtarget &STI) { return CSKY::R7; }
35
37 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
38
39 const MachineFrameInfo &MFI = MF.getFrameInfo();
41 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
43}
44
46 const MachineFrameInfo &MFI = MF.getFrameInfo();
47
48 return MFI.hasVarSizedObjects();
49}
50
51// Determines the size of the frame and maximum call frame size.
52void CSKYFrameLowering::determineFrameLayout(MachineFunction &MF) const {
54 const CSKYRegisterInfo *RI = STI.getRegisterInfo();
55
56 // Get the number of bytes to allocate from the FrameInfo.
57 uint64_t FrameSize = MFI.getStackSize();
58
59 // Get the alignment.
60 Align StackAlign = getStackAlign();
61 if (RI->hasStackRealignment(MF)) {
62 Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());
63 FrameSize += (MaxStackAlign.value() - StackAlign.value());
64 StackAlign = MaxStackAlign;
65 }
66
67 // Set Max Call Frame Size
68 uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign);
69 MFI.setMaxCallFrameSize(MaxCallSize);
70
71 // Make sure the frame is aligned.
72 FrameSize = alignTo(FrameSize, StackAlign);
73
74 // Update frame info.
75 MFI.setStackSize(FrameSize);
76}
77
79 MachineBasicBlock &MBB) const {
82 const CSKYRegisterInfo *RI = STI.getRegisterInfo();
83 const CSKYInstrInfo *TII = STI.getInstrInfo();
87
88 Register FPReg = getFPReg(STI);
89 Register SPReg = CSKY::R14;
90 Register BPReg = getBPReg(STI);
91
92 // Debug location must be unknown since the first debug location is used
93 // to determine the end of the prologue.
95
96 if (MF.getFunction().hasFnAttribute("interrupt"))
97 BuildMI(MBB, MBBI, DL, TII->get(CSKY::NIE));
98
99 // Determine the correct frame layout
100 determineFrameLayout(MF);
101
102 // FIXME (note copied from Lanai): This appears to be overallocating. Needs
103 // investigation. Get the number of bytes to allocate from the FrameInfo.
104 uint64_t StackSize = MFI.getStackSize();
105
106 // Early exit if there is no need to allocate on the stack
107 if (StackSize == 0 && !MFI.adjustsStack())
108 return;
109
110 const auto &CSI = MFI.getCalleeSavedInfo();
111
112 unsigned spillAreaSize = CFI->getCalleeSaveAreaSize();
113
114 uint64_t ActualSize = spillAreaSize + CFI->getVarArgsSaveSize();
115
116 // First part stack allocation.
117 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(ActualSize)),
119
120 // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount"
121 unsigned CFIIndex =
122 MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, ActualSize));
123 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
124 .addCFIIndex(CFIIndex);
125
126 // The frame pointer is callee-saved, and code has been generated for us to
127 // save it to the stack. We need to skip over the storing of callee-saved
128 // registers as the frame pointer must be modified after it has been saved
129 // to the stack, not before.
130 // FIXME: assumes exactly one instruction is used to save each callee-saved
131 // register.
132 std::advance(MBBI, CSI.size());
133
134 // Iterate over list of callee-saved registers and emit .cfi_offset
135 // directives.
136 for (const auto &Entry : CSI) {
137 int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());
138 Register Reg = Entry.getReg();
139
140 unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32;
141 for (unsigned i = 0; i < Num; i++) {
142 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
143 nullptr, RI->getDwarfRegNum(Reg, true) + i, Offset + i * 4));
144 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
145 .addCFIIndex(CFIIndex);
146 }
147 }
148
149 // Generate new FP.
150 if (hasFP(MF)) {
151 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), FPReg)
152 .addReg(SPReg)
154
155 // Emit ".cfi_def_cfa_register $fp"
157 nullptr, RI->getDwarfRegNum(FPReg, true)));
158 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
159 .addCFIIndex(CFIIndex);
160
161 // Second part stack allocation.
162 adjustReg(MBB, MBBI, DL, SPReg, SPReg,
163 -(static_cast<int64_t>(StackSize - ActualSize)),
165
166 // Realign Stack
167 const CSKYRegisterInfo *RI = STI.getRegisterInfo();
168 if (RI->hasStackRealignment(MF)) {
169 Align MaxAlignment = MFI.getMaxAlign();
170
171 const CSKYInstrInfo *TII = STI.getInstrInfo();
172 if (STI.hasE2() && isUInt<12>(~(-(int)MaxAlignment.value()))) {
173 BuildMI(MBB, MBBI, DL, TII->get(CSKY::ANDNI32), SPReg)
174 .addReg(SPReg)
175 .addImm(~(-(int)MaxAlignment.value()));
176 } else {
177 unsigned ShiftAmount = Log2(MaxAlignment);
178
179 if (STI.hasE2()) {
180 Register VR =
181 MF.getRegInfo().createVirtualRegister(&CSKY::GPRRegClass);
182 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI32), VR)
183 .addReg(SPReg)
184 .addImm(ShiftAmount);
185 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI32), SPReg)
186 .addReg(VR)
187 .addImm(ShiftAmount);
188 } else {
189 Register VR =
190 MF.getRegInfo().createVirtualRegister(&CSKY::mGPRRegClass);
191 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), VR).addReg(SPReg);
192 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI16), VR)
193 .addReg(VR)
194 .addImm(ShiftAmount);
195 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI16), VR)
196 .addReg(VR)
197 .addImm(ShiftAmount);
198 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), SPReg).addReg(VR);
199 }
200 }
201 }
202
203 // FP will be used to restore the frame in the epilogue, so we need
204 // another base register BP to record SP after re-alignment. SP will
205 // track the current stack after allocating variable sized objects.
206 if (hasBP(MF)) {
207 // move BP, SP
208 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), BPReg).addReg(SPReg);
209 }
210
211 } else {
212 adjustReg(MBB, MBBI, DL, SPReg, SPReg,
213 -(static_cast<int64_t>(StackSize - ActualSize)),
215 // Emit ".cfi_def_cfa_offset StackSize"
216 unsigned CFIIndex = MF.addFrameInst(
217 MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));
218 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
219 .addCFIIndex(CFIIndex);
220 }
221}
222
224 MachineBasicBlock &MBB) const {
226
227 MachineFrameInfo &MFI = MF.getFrameInfo();
228 Register FPReg = getFPReg(STI);
229 Register SPReg = CSKY::R14;
230
231 // Get the insert location for the epilogue. If there were no terminators in
232 // the block, get the last instruction.
234 DebugLoc DL;
235 if (!MBB.empty()) {
237 if (MBBI == MBB.end())
239 DL = MBBI->getDebugLoc();
240
241 // If this is not a terminator, the actual insert location should be after
242 // the last instruction.
243 if (!MBBI->isTerminator())
244 MBBI = std::next(MBBI);
245 }
246
247 const auto &CSI = MFI.getCalleeSavedInfo();
248 uint64_t StackSize = MFI.getStackSize();
249
250 uint64_t ActualSize =
252
253 // Skip to before the restores of callee-saved registers
254 // FIXME: assumes exactly one instruction is used to restore each
255 // callee-saved register.
256 auto LastFrameDestroy = MBBI;
257 if (!CSI.empty())
258 LastFrameDestroy = std::prev(MBBI, CSI.size());
259
260 if (hasFP(MF)) {
261 const CSKYInstrInfo *TII = STI.getInstrInfo();
262 BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::COPY), SPReg)
263 .addReg(FPReg)
265 } else {
266 adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, (StackSize - ActualSize),
268 }
269
270 adjustReg(MBB, MBBI, DL, SPReg, SPReg, ActualSize,
272}
273
275 const CSKYInstrInfo &TII) {
276 unsigned FnSize = 0;
277 for (auto &MBB : MF) {
278 for (auto &MI : MBB)
279 FnSize += TII.getInstSizeInBytes(MI);
280 }
281 FnSize += MF.getConstantPool()->getConstants().size() * 4;
282 return FnSize;
283}
284
286 const CSKYSubtarget &STI) {
287 unsigned Limit = (1 << 12) - 1;
288
289 for (auto &MBB : MF) {
290 for (auto &MI : MBB) {
291 if (MI.isDebugInstr())
292 continue;
293
294 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
295 if (!MI.getOperand(i).isFI())
296 continue;
297
298 if (MI.getOpcode() == CSKY::SPILL_CARRY ||
299 MI.getOpcode() == CSKY::RESTORE_CARRY ||
300 MI.getOpcode() == CSKY::STORE_PAIR ||
301 MI.getOpcode() == CSKY::LOAD_PAIR) {
302 Limit = std::min(Limit, ((1U << 12) - 1) * 4);
303 break;
304 }
305
306 if (MI.getOpcode() == CSKY::ADDI32) {
307 Limit = std::min(Limit, (1U << 12));
308 break;
309 }
310
311 if (MI.getOpcode() == CSKY::ADDI16XZ) {
312 Limit = std::min(Limit, (1U << 3));
313 break;
314 }
315
316 // ADDI16 will not require an extra register,
317 // it can reuse the destination.
318 if (MI.getOpcode() == CSKY::ADDI16)
319 break;
320
321 // Otherwise check the addressing mode.
322 switch (MI.getDesc().TSFlags & CSKYII::AddrModeMask) {
323 default:
324 LLVM_DEBUG(MI.dump());
326 "Unhandled addressing mode in stack size limit calculation");
328 Limit = std::min(Limit, (1U << 12) - 1);
329 break;
331 Limit = std::min(Limit, ((1U << 12) - 1) * 2);
332 break;
334 Limit = std::min(Limit, ((1U << 12) - 1) * 4);
335 break;
337 Limit = std::min(Limit, (1U << 5) - 1);
338 break;
340 Limit = std::min(Limit, ((1U << 5) - 1) * 2);
341 break;
343 Limit = std::min(Limit, ((1U << 5) - 1) * 4);
344 break;
346 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
347 break;
348 }
349 break; // At most one FI per instruction
350 }
351 }
352 }
353
354 return Limit;
355}
356
358 BitVector &SavedRegs,
359 RegScavenger *RS) const {
361
364 const CSKYInstrInfo *TII = STI.getInstrInfo();
365 const MachineRegisterInfo &MRI = MF.getRegInfo();
366 MachineFrameInfo &MFI = MF.getFrameInfo();
367
368 if (hasFP(MF))
369 SavedRegs.set(CSKY::R8);
370
371 // Mark BP as used if function has dedicated base pointer.
372 if (hasBP(MF))
373 SavedRegs.set(CSKY::R7);
374
375 // If interrupt is enabled and there are calls in the handler,
376 // unconditionally save all Caller-saved registers and
377 // all FP registers, regardless whether they are used.
378 if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
379
380 static const MCPhysReg CSRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3,
381 CSKY::R12, CSKY::R13, 0};
382
383 for (unsigned i = 0; CSRegs[i]; ++i)
384 SavedRegs.set(CSRegs[i]);
385
386 if (STI.hasHighRegisters()) {
387
388 static const MCPhysReg CSHRegs[] = {CSKY::R18, CSKY::R19, CSKY::R20,
389 CSKY::R21, CSKY::R22, CSKY::R23,
390 CSKY::R24, CSKY::R25, 0};
391
392 for (unsigned i = 0; CSHRegs[i]; ++i)
393 SavedRegs.set(CSHRegs[i]);
394 }
395
396 static const MCPhysReg CSF32Regs[] = {
397 CSKY::F8_32, CSKY::F9_32, CSKY::F10_32,
398 CSKY::F11_32, CSKY::F12_32, CSKY::F13_32,
399 CSKY::F14_32, CSKY::F15_32, 0};
400 static const MCPhysReg CSF64Regs[] = {
401 CSKY::F8_64, CSKY::F9_64, CSKY::F10_64,
402 CSKY::F11_64, CSKY::F12_64, CSKY::F13_64,
403 CSKY::F14_64, CSKY::F15_64, 0};
404
405 const MCPhysReg *FRegs = NULL;
406 if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat())
407 FRegs = CSF64Regs;
408 else if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat())
409 FRegs = CSF32Regs;
410
411 if (FRegs != NULL) {
412 const MCPhysReg *Regs = MF.getRegInfo().getCalleeSavedRegs();
413
414 for (unsigned i = 0; Regs[i]; ++i)
415 if (CSKY::FPR32RegClass.contains(Regs[i]) ||
416 CSKY::FPR64RegClass.contains(Regs[i])) {
417 unsigned x = 0;
418 for (; FRegs[x]; ++x)
419 if (FRegs[x] == Regs[i])
420 break;
421 if (FRegs[x] == 0)
422 SavedRegs.set(Regs[i]);
423 }
424 }
425 }
426
427 unsigned CSStackSize = 0;
428 for (unsigned Reg : SavedRegs.set_bits()) {
429 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;
430 CSStackSize += RegSize;
431 }
432
433 CFI->setCalleeSaveAreaSize(CSStackSize);
434
435 uint64_t Limit = estimateRSStackSizeLimit(MF, STI);
436
437 bool BigFrame = (MFI.estimateStackSize(MF) + CSStackSize >= Limit);
438
439 if (BigFrame || CFI->isCRSpilled() || !STI.hasE2()) {
440 const TargetRegisterClass *RC = &CSKY::GPRRegClass;
441 unsigned size = TRI->getSpillSize(*RC);
442 Align align = TRI->getSpillAlign(*RC);
443
444 RS->addScavengingFrameIndex(MFI.CreateStackObject(size, align, false));
445 }
446
447 unsigned FnSize = EstimateFunctionSizeInBytes(MF, *TII);
448 // Force R15 to be spilled if the function size is > 65534. This enables
449 // use of BSR to implement far jump.
450 if (FnSize >= ((1 << (16 - 1)) * 2))
451 SavedRegs.set(CSKY::R15);
452
453 CFI->setLRIsSpilled(SavedRegs.test(CSKY::R15));
454}
455
456// Not preserve stack space within prologue for outgoing variables when the
457// function contains variable size objects and let eliminateCallFramePseudoInstr
458// preserve stack space for it.
460 return !MF.getFrameInfo().hasVarSizedObjects();
461}
462
466 if (CSI.empty())
467 return true;
468
471 DebugLoc DL;
472 if (MI != MBB.end() && !MI->isDebugInstr())
473 DL = MI->getDebugLoc();
474
475 for (auto &CS : CSI) {
476 // Insert the spill to the stack frame.
477 Register Reg = CS.getReg();
478 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
479 TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI,
480 Register());
481 }
482
483 return true;
484}
485
489 if (CSI.empty())
490 return true;
491
494 DebugLoc DL;
495 if (MI != MBB.end() && !MI->isDebugInstr())
496 DL = MI->getDebugLoc();
497
498 for (auto &CS : reverse(CSI)) {
499 Register Reg = CS.getReg();
500 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
501 TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI,
502 Register());
503 assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
504 }
505
506 return true;
507}
508
509// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
513 Register SPReg = CSKY::R14;
514 DebugLoc DL = MI->getDebugLoc();
515
516 if (!hasReservedCallFrame(MF)) {
517 // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
518 // ADJCALLSTACKUP must be converted to instructions manipulating the stack
519 // pointer. This is necessary when there is a variable length stack
520 // allocation (e.g. alloca), which means it's not possible to allocate
521 // space for outgoing arguments from within the function prologue.
522 int64_t Amount = MI->getOperand(0).getImm();
523
524 if (Amount != 0) {
525 // Ensure the stack remains aligned after adjustment.
526 Amount = alignSPAdjust(Amount);
527
528 if (MI->getOpcode() == CSKY::ADJCALLSTACKDOWN)
529 Amount = -Amount;
530
531 adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
532 }
533 }
534
535 return MBB.erase(MI);
536}
537
538void CSKYFrameLowering::adjustReg(MachineBasicBlock &MBB,
540 const DebugLoc &DL, Register DestReg,
541 Register SrcReg, int64_t Val,
542 MachineInstr::MIFlag Flag) const {
543 const CSKYInstrInfo *TII = STI.getInstrInfo();
544
545 if (DestReg == SrcReg && Val == 0)
546 return;
547
548 // TODO: Add 16-bit instruction support with immediate num
549 if (STI.hasE2() && isUInt<12>(std::abs(Val) - 1)) {
550 BuildMI(MBB, MBBI, DL, TII->get(Val < 0 ? CSKY::SUBI32 : CSKY::ADDI32),
551 DestReg)
552 .addReg(SrcReg)
553 .addImm(std::abs(Val))
554 .setMIFlag(Flag);
555 } else if (!STI.hasE2() && isShiftedUInt<7, 2>(std::abs(Val))) {
556 BuildMI(MBB, MBBI, DL,
557 TII->get(Val < 0 ? CSKY::SUBI16SPSP : CSKY::ADDI16SPSP), CSKY::R14)
558 .addReg(CSKY::R14, RegState::Kill)
559 .addImm(std::abs(Val))
560 .setMIFlag(Flag);
561 } else {
562
563 unsigned Op = 0;
564
565 if (STI.hasE2()) {
566 Op = Val < 0 ? CSKY::SUBU32 : CSKY::ADDU32;
567 } else {
568 assert(SrcReg == DestReg);
569 Op = Val < 0 ? CSKY::SUBU16XZ : CSKY::ADDU16XZ;
570 }
571
572 Register ScratchReg = TII->movImm(MBB, MBBI, DL, std::abs(Val), Flag);
573
574 BuildMI(MBB, MBBI, DL, TII->get(Op), DestReg)
575 .addReg(SrcReg)
576 .addReg(ScratchReg, RegState::Kill)
577 .setMIFlag(Flag);
578 }
579}
580
583 Register &FrameReg) const {
585 const MachineFrameInfo &MFI = MF.getFrameInfo();
587 const auto &CSI = MFI.getCalleeSavedInfo();
588
589 int MinCSFI = 0;
590 int MaxCSFI = -1;
591
592 int Offset = MFI.getObjectOffset(FI) + MFI.getOffsetAdjustment();
593
594 if (CSI.size()) {
595 MinCSFI = CSI[0].getFrameIdx();
596 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
597 }
598
599 if (FI >= MinCSFI && FI <= MaxCSFI) {
600 FrameReg = CSKY::R14;
602 } else if (RI->hasStackRealignment(MF)) {
603 assert(hasFP(MF));
604 if (!MFI.isFixedObjectIndex(FI)) {
605 FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14;
606 Offset += MFI.getStackSize();
607 } else {
608 FrameReg = getFPReg(STI);
610 }
611 } else {
612 if (MFI.isFixedObjectIndex(FI) && hasFP(MF)) {
613 FrameReg = getFPReg(STI);
615 } else {
616 FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14;
617 Offset += MFI.getStackSize();
618 }
619 }
620
622}
unsigned const MachineRegisterInfo * MRI
static unsigned estimateRSStackSizeLimit(MachineFunction &MF)
Look at each instruction that references stack frames and return the stack size limit beyond which so...
unsigned RegSize
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF, const ARMBaseInstrInfo &TII)
static Register getBPReg(const CSKYSubtarget &STI)
static Register getFPReg(const CSKYSubtarget &STI)
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
bool test(unsigned Idx) const
Definition: BitVector.h:461
BitVector & set()
Definition: BitVector.h:351
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool hasBP(const MachineFunction &MF) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasHighRegisters() const
bool hasFPUv2SingleFloat() const
bool hasFPUv3SingleFloat() const
const CSKYRegisterInfo * getRegisterInfo() const override
bool hasE2() const
bool hasFPUv2DoubleFloat() const
bool hasFPUv3DoubleFloat() const
const CSKYInstrInfo * getInstrInfo() const override
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:683
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:548
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:583
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:556
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const std::vector< MachineConstantPoolEntry > & getConstants() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
void setMaxCallFrameSize(unsigned S)
void setStackSize(uint64_t Size)
Set the size of the stack.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
void dump() const
Definition: Pass.cpp:136
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
TargetInstrInfo - Interface to description of machine instruction set.
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1680
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:419
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:208
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85