23#include "llvm/IR/IntrinsicsSPIRV.h"
26#define DEBUG_TYPE "spirv-prelegalizer"
51 cast<Constant>(cast<ConstantAsMetadata>(
52 MI.getOperand(3).getMetadata()->getOperand(0))
54 if (
auto *GV = dyn_cast<GlobalValue>(Const)) {
57 GR->
add(GV, &MF,
MI.getOperand(2).getReg());
59 RegsAlreadyAddedToDT[&
MI] = Reg;
63 if (
auto *ConstVec = dyn_cast<ConstantDataVector>(Const)) {
64 auto *BuildVec =
MRI.getVRegDef(
MI.getOperand(2).getReg());
66 BuildVec->getOpcode() == TargetOpcode::G_BUILD_VECTOR);
67 for (
unsigned i = 0; i < ConstVec->getNumElements(); ++i)
68 GR->
add(ConstVec->getElementAsConstant(i), &MF,
69 BuildVec->getOperand(1 + i).getReg());
71 GR->
add(Const, &MF,
MI.getOperand(2).getReg());
73 RegsAlreadyAddedToDT[&
MI] = Reg;
76 assert(
MI.getOperand(2).isReg() &&
"Reg operand is expected");
78 if (SrcMI &&
isSpvIntrinsic(*SrcMI, Intrinsic::spv_const_composite))
86 if (RegsAlreadyAddedToDT.
find(
MI) != RegsAlreadyAddedToDT.
end())
87 Reg = RegsAlreadyAddedToDT[
MI];
88 auto *RC =
MRI.getRegClassOrNull(
MI->getOperand(0).getReg());
89 if (!
MRI.getRegClassOrNull(Reg) && RC)
90 MRI.setRegClass(Reg, RC);
91 MRI.replaceRegWith(
MI->getOperand(0).getReg(), Reg);
92 MI->eraseFromParent();
95 MI->eraseFromParent();
101 const unsigned AssignNameOperandShift = 2;
106 unsigned NumOp =
MI.getNumExplicitDefs() + AssignNameOperandShift;
107 while (
MI.getOperand(NumOp).isReg()) {
111 MI.removeOperand(NumOp);
120 MI->eraseFromParent();
137 MI->eraseFromParent();
152 assert(
MI &&
"Machine instr is expected");
153 if (
MI->getOperand(0).isReg()) {
157 switch (
MI->getOpcode()) {
158 case TargetOpcode::G_CONSTANT: {
160 Type *Ty =
MI->getOperand(1).getCImm()->getType();
164 case TargetOpcode::G_GLOBAL_VALUE: {
166 Type *Ty =
MI->getOperand(1).getGlobal()->getType();
170 case TargetOpcode::G_TRUNC:
171 case TargetOpcode::G_ADDRSPACE_CAST:
172 case TargetOpcode::G_PTR_ADD:
173 case TargetOpcode::COPY: {
175 MachineInstr *Def = Op.isReg() ?
MRI.getVRegDef(Op.getReg()) :
nullptr;
185 if (!
MRI.getRegClassOrNull(Reg))
186 MRI.setRegClass(Reg, &SPIRV::IDRegClass);
202 assert((Ty || SpirvTy) &&
"Either LLVM or SPIRV type is expected.");
204 (Def->getNextNode() ? Def->getNextNode()->getIterator()
205 : Def->getParent()->end()));
206 Register NewReg =
MRI.createGenericVirtualRegister(
MRI.getType(Reg));
207 if (
auto *RC =
MRI.getRegClassOrNull(Reg)) {
208 MRI.setRegClass(NewReg, RC);
210 MRI.setRegClass(NewReg, &SPIRV::IDRegClass);
211 MRI.setRegClass(Reg, &SPIRV::IDRegClass);
226 Def->getOperand(0).setReg(NewReg);
240 bool ReachedBegin =
false;
249 assert(Def &&
"Expecting an instruction that defines the register");
251 if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE)
254 }
else if (
MI.getOpcode() == TargetOpcode::G_CONSTANT ||
255 MI.getOpcode() == TargetOpcode::G_FCONSTANT ||
256 MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
263 if (
MRI.hasOneUse(Reg)) {
270 if (
MI.getOpcode() == TargetOpcode::G_CONSTANT)
271 Ty =
MI.getOperand(1).getCImm()->getType();
272 else if (
MI.getOpcode() == TargetOpcode::G_FCONSTANT)
273 Ty =
MI.getOperand(1).getFPImm()->getType();
275 assert(
MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
276 Type *ElemTy =
nullptr;
280 if (ElemMI->
getOpcode() == TargetOpcode::G_CONSTANT)
282 else if (ElemMI->
getOpcode() == TargetOpcode::G_FCONSTANT)
287 MI.getNumExplicitOperands() -
MI.getNumExplicitDefs();
288 Ty = VectorType::get(ElemTy, NumElts,
false);
291 }
else if (
MI.getOpcode() == TargetOpcode::G_TRUNC ||
292 MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
293 MI.getOpcode() == TargetOpcode::COPY ||
294 MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) {
305 MI->eraseFromParent();
308static std::pair<Register, unsigned>
313 assert(SpvType &&
"VReg is expected to have SPIRV type");
314 bool IsFloat = SpvType->
getOpcode() == SPIRV::OpTypeFloat;
316 SpvType->
getOpcode() == SPIRV::OpTypeVector &&
319 IsFloat |= IsVectorFloat;
320 auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
321 auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
322 if (
MRI.getType(ValReg).isPointer()) {
324 GetIdOp = SPIRV::GET_pID;
325 DstClass = &SPIRV::pIDRegClass;
326 }
else if (
MRI.getType(ValReg).isVector()) {
328 GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
329 DstClass = IsFloat ? &SPIRV::vfIDRegClass : &SPIRV::vIDRegClass;
331 Register IdReg =
MRI.createGenericVirtualRegister(NewT);
332 MRI.setRegClass(IdReg, DstClass);
333 return {IdReg, GetIdOp};
338 unsigned Opc =
MI.getOpcode();
339 assert(
MI.getNumDefs() > 0 &&
MRI.hasOneUse(
MI.getOperand(0).getReg()));
341 *(
MRI.use_instr_begin(
MI.getOperand(0).getReg()));
344 MI.getOperand(0).setReg(NewReg);
346 (
MI.getNextNode() ?
MI.getNextNode()->getIterator()
347 :
MI.getParent()->end()));
348 for (
auto &Op :
MI.operands()) {
349 if (!Op.isReg() || Op.isDef())
353 Op.setReg(IdOpInfo.first);
375 if (
MI.getOpcode() != SPIRV::ASSIGN_TYPE)
378 unsigned Opcode =
MRI.getVRegDef(SrcReg)->getOpcode();
382 if (
MRI.getType(DstReg).isVector())
383 MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
386 if (Opcode == TargetOpcode::G_CONSTANT &&
MRI.hasOneUse(DstReg)) {
388 if (
UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
431 std::vector<MachineInstr *> RelevantInsts;
435 std::vector<MachineInstr *> PostUpdateArtifacts;
445 CompareRegs.
insert(
MI.getOperand(1).getReg());
446 RelevantInsts.push_back(&
MI);
451 if (
MI.getOpcode() == TargetOpcode::G_SUB &&
MI.getOperand(1).isReg() &&
452 CompareRegs.
contains(
MI.getOperand(1).getReg())) {
453 assert(
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg());
456 PostUpdateArtifacts.push_back(&
MI);
460 if (
MI.getOpcode() == TargetOpcode::G_ICMP &&
MI.getOperand(2).isReg() &&
461 CompareRegs.
contains(
MI.getOperand(2).getReg())) {
463 RelevantInsts.push_back(&
MI);
464 PostUpdateArtifacts.push_back(&
MI);
467 PostUpdateArtifacts.push_back(CBr);
470 PostUpdateArtifacts.push_back(Br);
476 for (
auto i = RelevantInsts.begin(); i != RelevantInsts.end(); i++) {
490 Register CompareReg = Switch->getOperand(1).getReg();
491 for (
auto j = i + 1; j != RelevantInsts.end(); j++) {
493 (*j)->getOperand(1).getReg() == CompareReg)
496 if (!((*j)->getOpcode() == TargetOpcode::G_ICMP &&
497 (*j)->getOperand(2).getReg() == CompareReg))
501 Register Dst = ICMP->getOperand(0).getReg();
505 MRI.hasOneUse(Dst) &&
MRI.hasOneDef(CompareReg));
515 Switch->getParent()->addSuccessor(
MBB);
528 DefaultMBB = NextMBB;
529 Switch->getParent()->addSuccessor(DefaultMBB);
537 for (
unsigned k = 2; k < Switch->getNumExplicitOperands(); k++) {
538 Register CReg = Switch->getOperand(k).getReg();
541 if (!ValuesToMBBs[Val])
548 for (
unsigned k = Switch->getNumExplicitOperands() - 1; k > 1; k--)
549 Switch->removeOperand(k);
552 for (
unsigned k = 0; k < Values.
size(); k++) {
560 MI->eraseFromParent();
565 if (ParentMBB->
empty()) {
567 (*ParentMBB->
pred_begin())->removeSuccessor(ParentMBB);
581 GR->setCurrentFunc(MF);
596char SPIRVPreLegalizer::
ID = 0;
599 return new SPIRVPreLegalizer();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isTypeFoldingSupported(unsigned Opcode)
static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)
static void processInstrsWithTypeFolding(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
static SPIRVType * propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR, MachineRegisterInfo &MRI, MachineIRBuilder &MIB)
static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
static std::pair< Register, unsigned > createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, const SPIRVGlobalRegistry &GR)
static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR)
static void foldConstantsIntoIntrinsics(MachineFunction &MF)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ ICMP_ULE
unsigned less or equal
IntegerType * getType() const
getType - Specialize the getType() method to always return an IntegerType, which reduces the amount o...
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
iterator find(const_arg_type_t< KeyT > Val)
Implements a dense probed hash-table based set.
FunctionPass class - This class is used to implement most global optimizations.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
succ_iterator succ_begin()
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
pred_iterator pred_begin()
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
static MachineOperand CreateCImm(const ConstantInt *CI)
void setReg(Register Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
unsigned getPredicate() const
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
void add(const Constant *C, MachineFunction *MF, Register R)
SPIRVType * getSPIRVTypeForVReg(Register VReg) const
Register find(const Constant *C, MachineFunction *MF)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createSPIRVPreLegalizerPass()
Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI)
Helper external function for inserting ASSIGN_TYPE instuction between Reg and its definition,...
iterator_range< po_iterator< T > > post_order(const T &G)
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID)
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
void initializeSPIRVPreLegalizerPass(PassRegistry &)