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AArch64PreLegalizerCombiner.cpp
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1 //=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass does combining of machine instructions at the generic MI level,
10 // before the legalizer.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64TargetMachine.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/Support/Debug.h"
28 
29 #define DEBUG_TYPE "aarch64-prelegalizer-combiner"
30 
31 using namespace llvm;
32 using namespace MIPatternMatch;
33 
34 /// Return true if a G_FCONSTANT instruction is known to be better-represented
35 /// as a G_CONSTANT.
38  assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
39  Register DstReg = MI.getOperand(0).getReg();
40  const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
41  if (DstSize != 32 && DstSize != 64)
42  return false;
43 
44  // When we're storing a value, it doesn't matter what register bank it's on.
45  // Since not all floating point constants can be materialized using a fmov,
46  // it makes more sense to just use a GPR.
47  return all_of(MRI.use_nodbg_instructions(DstReg),
48  [](const MachineInstr &Use) { return Use.mayStore(); });
49 }
50 
51 /// Change a G_FCONSTANT into a G_CONSTANT.
53  assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
54  MachineIRBuilder MIB(MI);
55  const APFloat &ImmValAPF = MI.getOperand(1).getFPImm()->getValueAPF();
56  MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt());
57  MI.eraseFromParent();
58 }
59 
60 /// Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits
61 /// are sign bits. In this case, we can transform the G_ICMP to directly compare
62 /// the wide value with a zero.
64  GISelKnownBits *KB, Register &MatchInfo) {
65  assert(MI.getOpcode() == TargetOpcode::G_ICMP && KB);
66 
67  auto Pred = (CmpInst::Predicate)MI.getOperand(1).getPredicate();
68  if (!ICmpInst::isEquality(Pred))
69  return false;
70 
71  Register LHS = MI.getOperand(2).getReg();
72  LLT LHSTy = MRI.getType(LHS);
73  if (!LHSTy.isScalar())
74  return false;
75 
76  Register RHS = MI.getOperand(3).getReg();
77  Register WideReg;
78 
79  if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) ||
80  !mi_match(RHS, MRI, m_SpecificICst(0)))
81  return false;
82 
83  LLT WideTy = MRI.getType(WideReg);
84  if (KB->computeNumSignBits(WideReg) <=
85  WideTy.getSizeInBits() - LHSTy.getSizeInBits())
86  return false;
87 
88  MatchInfo = WideReg;
89  return true;
90 }
91 
94  GISelChangeObserver &Observer,
95  Register &WideReg) {
96  assert(MI.getOpcode() == TargetOpcode::G_ICMP);
97 
98  LLT WideTy = MRI.getType(WideReg);
99  // We're going to directly use the wide register as the LHS, and then use an
100  // equivalent size zero for RHS.
101  Builder.setInstrAndDebugLoc(MI);
102  auto WideZero = Builder.buildConstant(WideTy, 0);
103  Observer.changingInstr(MI);
104  MI.getOperand(2).setReg(WideReg);
105  MI.getOperand(3).setReg(WideZero.getReg(0));
106  Observer.changedInstr(MI);
107  return true;
108 }
109 
110 /// \returns true if it is possible to fold a constant into a G_GLOBAL_VALUE.
111 ///
112 /// e.g.
113 ///
114 /// %g = G_GLOBAL_VALUE @x -> %g = G_GLOBAL_VALUE @x + cst
116  std::pair<uint64_t, uint64_t> &MatchInfo) {
117  assert(MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
118  MachineFunction &MF = *MI.getMF();
119  auto &GlobalOp = MI.getOperand(1);
120  auto *GV = GlobalOp.getGlobal();
121 
122  // Don't allow anything that could represent offsets etc.
124  GV, MF.getTarget()) != AArch64II::MO_NO_FLAG)
125  return false;
126 
127  // Look for a G_GLOBAL_VALUE only used by G_PTR_ADDs against constants:
128  //
129  // %g = G_GLOBAL_VALUE @x
130  // %ptr1 = G_PTR_ADD %g, cst1
131  // %ptr2 = G_PTR_ADD %g, cst2
132  // ...
133  // %ptrN = G_PTR_ADD %g, cstN
134  //
135  // Identify the *smallest* constant. We want to be able to form this:
136  //
137  // %offset_g = G_GLOBAL_VALUE @x + min_cst
138  // %g = G_PTR_ADD %offset_g, -min_cst
139  // %ptr1 = G_PTR_ADD %g, cst1
140  // ...
141  Register Dst = MI.getOperand(0).getReg();
142  uint64_t MinOffset = -1ull;
143  for (auto &UseInstr : MRI.use_nodbg_instructions(Dst)) {
144  if (UseInstr.getOpcode() != TargetOpcode::G_PTR_ADD)
145  return false;
146  auto Cst =
147  getConstantVRegValWithLookThrough(UseInstr.getOperand(2).getReg(), MRI);
148  if (!Cst)
149  return false;
150  MinOffset = std::min(MinOffset, Cst->Value.getZExtValue());
151  }
152 
153  // Require that the new offset is larger than the existing one to avoid
154  // infinite loops.
155  uint64_t CurrOffset = GlobalOp.getOffset();
156  uint64_t NewOffset = MinOffset + CurrOffset;
157  if (NewOffset <= CurrOffset)
158  return false;
159 
160  // Check whether folding this offset is legal. It must not go out of bounds of
161  // the referenced object to avoid violating the code model, and must be
162  // smaller than 2^21 because this is the largest offset expressible in all
163  // object formats.
164  //
165  // This check also prevents us from folding negative offsets, which will end
166  // up being treated in the same way as large positive ones. They could also
167  // cause code model violations, and aren't really common enough to matter.
168  if (NewOffset >= (1 << 21))
169  return false;
170 
171  Type *T = GV->getValueType();
172  if (!T->isSized() ||
173  NewOffset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
174  return false;
175  MatchInfo = std::make_pair(NewOffset, MinOffset);
176  return true;
177 }
178 
181  GISelChangeObserver &Observer,
182  std::pair<uint64_t, uint64_t> &MatchInfo) {
183  // Change:
184  //
185  // %g = G_GLOBAL_VALUE @x
186  // %ptr1 = G_PTR_ADD %g, cst1
187  // %ptr2 = G_PTR_ADD %g, cst2
188  // ...
189  // %ptrN = G_PTR_ADD %g, cstN
190  //
191  // To:
192  //
193  // %offset_g = G_GLOBAL_VALUE @x + min_cst
194  // %g = G_PTR_ADD %offset_g, -min_cst
195  // %ptr1 = G_PTR_ADD %g, cst1
196  // ...
197  // %ptrN = G_PTR_ADD %g, cstN
198  //
199  // Then, the original G_PTR_ADDs should be folded later on so that they look
200  // like this:
201  //
202  // %ptrN = G_PTR_ADD %offset_g, cstN - min_cst
203  uint64_t Offset, MinOffset;
204  std::tie(Offset, MinOffset) = MatchInfo;
205  B.setInstrAndDebugLoc(MI);
206  Observer.changingInstr(MI);
207  auto &GlobalOp = MI.getOperand(1);
208  auto *GV = GlobalOp.getGlobal();
209  GlobalOp.ChangeToGA(GV, Offset, GlobalOp.getTargetFlags());
210  Register Dst = MI.getOperand(0).getReg();
211  Register NewGVDst = MRI.cloneVirtualRegister(Dst);
212  MI.getOperand(0).setReg(NewGVDst);
213  Observer.changedInstr(MI);
214  B.buildPtrAdd(
215  Dst, NewGVDst,
216  B.buildConstant(LLT::scalar(64), -static_cast<int64_t>(MinOffset)));
217  return true;
218 }
219 
220 /// Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is
221 /// supported and beneficial to do so.
222 ///
223 /// \note This only applies on Darwin.
224 ///
225 /// \returns true if \p MI was replaced with a G_BZERO.
226 static bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
227  bool MinSize) {
228  assert(MI.getOpcode() == TargetOpcode::G_MEMSET);
229  MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
230  auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
231  if (!TLI.getLibcallName(RTLIB::BZERO))
232  return false;
233  auto Zero = getConstantVRegValWithLookThrough(MI.getOperand(1).getReg(), MRI);
234  if (!Zero || Zero->Value.getSExtValue() != 0)
235  return false;
236 
237  // It's not faster to use bzero rather than memset for sizes <= 256.
238  // However, it *does* save us a mov from wzr, so if we're going for
239  // minsize, use bzero even if it's slower.
240  if (!MinSize) {
241  // If the size is known, check it. If it is not known, assume using bzero is
242  // better.
243  if (auto Size =
244  getConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI)) {
245  if (Size->Value.getSExtValue() <= 256)
246  return false;
247  }
248  }
249 
250  MIRBuilder.setInstrAndDebugLoc(MI);
251  MIRBuilder
252  .buildInstr(TargetOpcode::G_BZERO, {},
253  {MI.getOperand(0), MI.getOperand(2)})
254  .addImm(MI.getOperand(3).getImm())
255  .addMemOperand(*MI.memoperands_begin());
256  MI.eraseFromParent();
257  return true;
258 }
259 
261 protected:
263 
264 public:
266  : Helper(Helper) {}
267 };
268 
269 #define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
270 #include "AArch64GenPreLegalizeGICombiner.inc"
271 #undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
272 
273 namespace {
274 #define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
275 #include "AArch64GenPreLegalizeGICombiner.inc"
276 #undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
277 
278 class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
279  GISelKnownBits *KB;
281  AArch64GenPreLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
282 
283 public:
284  AArch64PreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
286  : CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
287  /*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
288  KB(KB), MDT(MDT) {
289  if (!GeneratedRuleCfg.parseCommandLineOption())
290  report_fatal_error("Invalid rule identifier");
291  }
292 
293  virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
294  MachineIRBuilder &B) const override;
295 };
296 
298  MachineInstr &MI,
299  MachineIRBuilder &B) const {
300  CombinerHelper Helper(Observer, B, KB, MDT);
301  AArch64GenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
302 
303  if (Generated.tryCombineAll(Observer, MI, B))
304  return true;
305 
306  unsigned Opc = MI.getOpcode();
307  switch (Opc) {
308  case TargetOpcode::G_CONCAT_VECTORS:
309  return Helper.tryCombineConcatVectors(MI);
310  case TargetOpcode::G_SHUFFLE_VECTOR:
311  return Helper.tryCombineShuffleVector(MI);
312  case TargetOpcode::G_MEMCPY:
313  case TargetOpcode::G_MEMMOVE:
314  case TargetOpcode::G_MEMSET: {
315  // If we're at -O0 set a maxlen of 32 to inline, otherwise let the other
316  // heuristics decide.
317  unsigned MaxLen = EnableOpt ? 0 : 32;
318  // Try to inline memcpy type calls if optimizations are enabled.
319  if (!EnableMinSize && Helper.tryCombineMemCpyFamily(MI, MaxLen))
320  return true;
321  if (Opc == TargetOpcode::G_MEMSET)
322  return tryEmitBZero(MI, B, EnableMinSize);
323  return false;
324  }
325  }
326 
327  return false;
328 }
329 
330 #define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
331 #include "AArch64GenPreLegalizeGICombiner.inc"
332 #undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
333 
334 // Pass boilerplate
335 // ================
336 
337 class AArch64PreLegalizerCombiner : public MachineFunctionPass {
338 public:
339  static char ID;
340 
341  AArch64PreLegalizerCombiner(bool IsOptNone = false);
342 
343  StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
344 
345  bool runOnMachineFunction(MachineFunction &MF) override;
346 
347  void getAnalysisUsage(AnalysisUsage &AU) const override;
348 private:
349  bool IsOptNone;
350 };
351 } // end anonymous namespace
352 
353 void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
355  AU.setPreservesCFG();
359  if (!IsOptNone) {
362  }
366 }
367 
368 AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner(bool IsOptNone)
369  : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
370  initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
371 }
372 
373 bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
374  if (MF.getProperties().hasProperty(
375  MachineFunctionProperties::Property::FailedISel))
376  return false;
377  auto &TPC = getAnalysis<TargetPassConfig>();
378 
379  // Enable CSE.
381  getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
382  auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig());
383 
384  const Function &F = MF.getFunction();
385  bool EnableOpt =
386  MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
387  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
388  MachineDominatorTree *MDT =
389  IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
390  AArch64PreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
391  F.hasMinSize(), KB, MDT);
392  Combiner C(PCInfo, &TPC);
393  return C.combineMachineInstrs(MF, CSEInfo);
394 }
395 
397 INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
398  "Combine AArch64 machine instrs before legalization",
399  false, false)
403 INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
404  "Combine AArch64 machine instrs before legalization", false,
405  false)
406 
407 
408 namespace llvm {
410  return new AArch64PreLegalizerCombiner(IsOptNone);
411 }
412 } // end namespace llvm
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Returns the optimization level: None, Less, Default, or Aggressive.
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Definition: PassAnalysisSupport.h:47
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Get the function properties.
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virtual void changingInstr(MachineInstr &MI)=0
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Definition: TargetPassConfig.h:84
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virtual void changedInstr(MachineInstr &MI)=0
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Definition: MachineIRBuilder.h:220
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Definition: AArch64PreLegalizerCombiner.cpp:404
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Definition: AArch64PreLegalizerCombiner.cpp:36
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unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:260
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
applyFConstantToConstant
static void applyFConstantToConstant(MachineInstr &MI)
Change a G_FCONSTANT into a G_CONSTANT.
Definition: AArch64PreLegalizerCombiner.cpp:52
matchICmpRedundantTrunc
static bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, GISelKnownBits *KB, Register &MatchInfo)
Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits are sign bits.
Definition: AArch64PreLegalizerCombiner.cpp:63
llvm::GISelCSEAnalysisWrapper
Simple wrapper that does the following.
Definition: CSEInfo.h:202
llvm::createAArch64PreLegalizerCombiner
FunctionPass * createAArch64PreLegalizerCombiner(bool IsOptNone)
Definition: AArch64PreLegalizerCombiner.cpp:409
AArch64PreLegalizerCombinerHelperState::Helper
CombinerHelper & Helper
Definition: AArch64PreLegalizerCombiner.cpp:262
Instructions.h
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:96
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:172
applyICmpRedundantTrunc
static bool applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &Builder, GISelChangeObserver &Observer, Register &WideReg)
Definition: AArch64PreLegalizerCombiner.cpp:92
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:24
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
MachineFunction.h
combine
vector combine
Definition: VectorCombine.cpp:833
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
Debug.h
llvm::getConstantVRegValWithLookThrough
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...
Definition: Utils.cpp:289
machine
coro Split coroutine into a set of functions driving its state machine
Definition: CoroSplit.cpp:2246
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
MachineDominators.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:40