LLVM  15.0.0git
MipsCallLowering.cpp
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1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsCallLowering.h"
16 #include "MipsCCState.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/CodeGen/Analysis.h"
22 
23 using namespace llvm;
24 
26  : CallLowering(&TLI) {}
27 
28 namespace {
29 struct MipsOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
30  /// This is the name of the function being called
31  /// FIXME: Relying on this is unsound
32  const char *Func = nullptr;
33 
34  /// Is this a return value, or an outgoing call operand.
35  bool IsReturn;
36 
37  MipsOutgoingValueAssigner(CCAssignFn *AssignFn_, const char *Func,
38  bool IsReturn)
39  : OutgoingValueAssigner(AssignFn_), Func(Func), IsReturn(IsReturn) {}
40 
41  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
42  CCValAssign::LocInfo LocInfo,
44  CCState &State_) override {
45  MipsCCState &State = static_cast<MipsCCState &>(State_);
46 
47  if (IsReturn)
49  else
50  State.PreAnalyzeCallOperand(Info.Ty, Info.IsFixed, Func);
51 
53  ValNo, OrigVT, ValVT, LocVT, LocInfo, Info, Flags, State);
54  }
55 };
56 
57 struct MipsIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
58  /// This is the name of the function being called
59  /// FIXME: Relying on this is unsound
60  const char *Func = nullptr;
61 
62  /// Is this a call return value, or an incoming function argument.
63  bool IsReturn;
64 
65  MipsIncomingValueAssigner(CCAssignFn *AssignFn_, const char *Func,
66  bool IsReturn)
67  : IncomingValueAssigner(AssignFn_), Func(Func), IsReturn(IsReturn) {}
68 
69  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
70  CCValAssign::LocInfo LocInfo,
72  CCState &State_) override {
73  MipsCCState &State = static_cast<MipsCCState &>(State_);
74 
75  if (IsReturn)
76  State.PreAnalyzeCallResult(Info.Ty, Func);
77  else
78  State.PreAnalyzeFormalArgument(Info.Ty, Flags);
79 
81  ValNo, OrigVT, ValVT, LocVT, LocInfo, Info, Flags, State);
82  }
83 };
84 
85 class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler {
86  const MipsSubtarget &STI;
87 
88 public:
89  MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder,
91  : IncomingValueHandler(MIRBuilder, MRI),
92  STI(MIRBuilder.getMF().getSubtarget<MipsSubtarget>()) {}
93 
94 private:
95  void assignValueToReg(Register ValVReg, Register PhysReg,
96  CCValAssign VA) override;
97 
98  Register getStackAddress(uint64_t Size, int64_t Offset,
99  MachinePointerInfo &MPO,
100  ISD::ArgFlagsTy Flags) override;
101  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
102  MachinePointerInfo &MPO, CCValAssign &VA) override;
103 
104  unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
106  std::function<void()> *Thunk = nullptr) override;
107 
108  virtual void markPhysRegUsed(unsigned PhysReg) {
109  MIRBuilder.getMRI()->addLiveIn(PhysReg);
110  MIRBuilder.getMBB().addLiveIn(PhysReg);
111  }
112 };
113 
114 class CallReturnHandler : public MipsIncomingValueHandler {
115 public:
117  MachineInstrBuilder &MIB)
118  : MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
119 
120 private:
121  void markPhysRegUsed(unsigned PhysReg) override {
122  MIB.addDef(PhysReg, RegState::Implicit);
123  }
124 
125  MachineInstrBuilder &MIB;
126 };
127 
128 } // end anonymous namespace
129 
130 void MipsIncomingValueHandler::assignValueToReg(Register ValVReg,
131  Register PhysReg,
132  CCValAssign VA) {
133  markPhysRegUsed(PhysReg);
134  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
135 }
136 
137 Register MipsIncomingValueHandler::getStackAddress(uint64_t Size,
138  int64_t Offset,
139  MachinePointerInfo &MPO,
140  ISD::ArgFlagsTy Flags) {
141 
142  MachineFunction &MF = MIRBuilder.getMF();
143  MachineFrameInfo &MFI = MF.getFrameInfo();
144 
145  // FIXME: This should only be immutable for non-byval memory arguments.
146  int FI = MFI.CreateFixedObject(Size, Offset, true);
147  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
148 
149  return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
150 }
151 
152 void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
153  Register Addr, LLT MemTy,
154  MachinePointerInfo &MPO,
155  CCValAssign &VA) {
156  MachineFunction &MF = MIRBuilder.getMF();
157  auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
158  inferAlignFromPtrInfo(MF, MPO));
159  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
160 }
161 
162 /// Handle cases when f64 is split into 2 32-bit GPRs. This is a custom
163 /// assignment because generic code assumes getNumRegistersForCallingConv is
164 /// accurate. In this case it is not because the type/number are context
165 /// dependent on other arguments.
166 unsigned
167 MipsIncomingValueHandler::assignCustomValue(CallLowering::ArgInfo &Arg,
169  std::function<void()> *Thunk) {
170  const CCValAssign &VALo = VAs[0];
171  const CCValAssign &VAHi = VAs[1];
172 
173  assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
174  VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
175  "unexpected custom value");
176 
177  auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg());
178  auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg());
179  if (!STI.isLittle())
180  std::swap(CopyLo, CopyHi);
181 
182  Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end());
183  Arg.Regs = { CopyLo.getReg(0), CopyHi.getReg(0) };
184  MIRBuilder.buildMerge(Arg.OrigRegs[0], {CopyLo, CopyHi});
185 
186  markPhysRegUsed(VALo.getLocReg());
187  markPhysRegUsed(VAHi.getLocReg());
188  return 2;
189 }
190 
191 namespace {
192 class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
193  const MipsSubtarget &STI;
194 
195 public:
196  MipsOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
198  : OutgoingValueHandler(MIRBuilder, MRI),
199  STI(MIRBuilder.getMF().getSubtarget<MipsSubtarget>()), MIB(MIB) {}
200 
201 private:
202  void assignValueToReg(Register ValVReg, Register PhysReg,
203  CCValAssign VA) override;
204 
205  Register getStackAddress(uint64_t Size, int64_t Offset,
206  MachinePointerInfo &MPO,
207  ISD::ArgFlagsTy Flags) override;
208 
209  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
210  MachinePointerInfo &MPO, CCValAssign &VA) override;
211  unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
213  std::function<void()> *Thunk) override;
214 
215  MachineInstrBuilder &MIB;
216 };
217 } // end anonymous namespace
218 
219 void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg,
220  Register PhysReg,
221  CCValAssign VA) {
222  Register ExtReg = extendRegister(ValVReg, VA);
223  MIRBuilder.buildCopy(PhysReg, ExtReg);
224  MIB.addUse(PhysReg, RegState::Implicit);
225 }
226 
227 Register MipsOutgoingValueHandler::getStackAddress(uint64_t Size,
228  int64_t Offset,
229  MachinePointerInfo &MPO,
230  ISD::ArgFlagsTy Flags) {
231  MachineFunction &MF = MIRBuilder.getMF();
232  MPO = MachinePointerInfo::getStack(MF, Offset);
233 
234  LLT p0 = LLT::pointer(0, 32);
235  LLT s32 = LLT::scalar(32);
236  auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP));
237 
238  auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
239  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
240  return AddrReg.getReg(0);
241 }
242 
243 void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
244  Register Addr, LLT MemTy,
245  MachinePointerInfo &MPO,
246  CCValAssign &VA) {
247  MachineFunction &MF = MIRBuilder.getMF();
248  uint64_t LocMemOffset = VA.getLocMemOffset();
249 
250  auto MMO = MF.getMachineMemOperand(
251  MPO, MachineMemOperand::MOStore, MemTy,
252  commonAlignment(STI.getStackAlignment(), LocMemOffset));
253 
254  Register ExtReg = extendRegister(ValVReg, VA);
255  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
256 }
257 
258 unsigned
259 MipsOutgoingValueHandler::assignCustomValue(CallLowering::ArgInfo &Arg,
261  std::function<void()> *Thunk) {
262  const CCValAssign &VALo = VAs[0];
263  const CCValAssign &VAHi = VAs[1];
264 
265  assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
266  VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
267  "unexpected custom value");
268 
269  auto Unmerge =
270  MIRBuilder.buildUnmerge({LLT::scalar(32), LLT::scalar(32)}, Arg.Regs[0]);
271  Register Lo = Unmerge.getReg(0);
272  Register Hi = Unmerge.getReg(1);
273 
274  Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end());
275  Arg.Regs = { Lo, Hi };
276  if (!STI.isLittle())
277  std::swap(Lo, Hi);
278 
279  // If we can return a thunk, just include the register copies. The unmerge can
280  // be emitted earlier.
281  if (Thunk) {
282  *Thunk = [=]() {
283  MIRBuilder.buildCopy(VALo.getLocReg(), Lo);
284  MIRBuilder.buildCopy(VAHi.getLocReg(), Hi);
285  };
286  return 2;
287  }
288  MIRBuilder.buildCopy(VALo.getLocReg(), Lo);
289  MIRBuilder.buildCopy(VAHi.getLocReg(), Hi);
290  return 2;
291 }
292 
293 static bool isSupportedArgumentType(Type *T) {
294  if (T->isIntegerTy())
295  return true;
296  if (T->isPointerTy())
297  return true;
298  if (T->isFloatingPointTy())
299  return true;
300  return false;
301 }
302 
303 static bool isSupportedReturnType(Type *T) {
304  if (T->isIntegerTy())
305  return true;
306  if (T->isPointerTy())
307  return true;
308  if (T->isFloatingPointTy())
309  return true;
310  if (T->isAggregateType())
311  return true;
312  return false;
313 }
314 
316  const Value *Val, ArrayRef<Register> VRegs,
317  FunctionLoweringInfo &FLI) const {
318 
319  MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
320 
321  if (Val != nullptr && !isSupportedReturnType(Val->getType()))
322  return false;
323 
324  if (!VRegs.empty()) {
325  MachineFunction &MF = MIRBuilder.getMF();
326  const Function &F = MF.getFunction();
327  const DataLayout &DL = MF.getDataLayout();
328  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
329 
330  SmallVector<ArgInfo, 8> RetInfos;
331 
332  ArgInfo ArgRetInfo(VRegs, *Val, 0);
334  splitToValueTypes(ArgRetInfo, RetInfos, DL, F.getCallingConv());
335 
338 
339  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
340  F.getContext());
341 
342  MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
343  std::string FuncName = F.getName().str();
344  MipsOutgoingValueAssigner Assigner(TLI.CCAssignFnForReturn(),
345  FuncName.c_str(), /*IsReturn*/ true);
346 
347  if (!determineAssignments(Assigner, RetInfos, CCInfo))
348  return false;
349 
350  if (!handleAssignments(RetHandler, RetInfos, CCInfo, ArgLocs, MIRBuilder))
351  return false;
352  }
353 
354  MIRBuilder.insertInstr(Ret);
355  return true;
356 }
357 
359  const Function &F,
361  FunctionLoweringInfo &FLI) const {
362 
363  // Quick exit if there aren't any args.
364  if (F.arg_empty())
365  return true;
366 
367  for (auto &Arg : F.args()) {
368  if (!isSupportedArgumentType(Arg.getType()))
369  return false;
370  }
371 
372  MachineFunction &MF = MIRBuilder.getMF();
373  const DataLayout &DL = MF.getDataLayout();
374  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
375 
376  SmallVector<ArgInfo, 8> ArgInfos;
377  unsigned i = 0;
378  for (auto &Arg : F.args()) {
379  ArgInfo AInfo(VRegs[i], Arg, i);
381 
382  splitToValueTypes(AInfo, ArgInfos, DL, F.getCallingConv());
383  ++i;
384  }
385 
387 
389  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
390  F.getContext());
391 
392  const MipsTargetMachine &TM =
393  static_cast<const MipsTargetMachine &>(MF.getTarget());
394  const MipsABIInfo &ABI = TM.getABI();
395  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
396  Align(1));
397 
398  const std::string FuncName = F.getName().str();
399  MipsIncomingValueAssigner Assigner(TLI.CCAssignFnForCall(), FuncName.c_str(),
400  /*IsReturn*/ false);
401  if (!determineAssignments(Assigner, ArgInfos, CCInfo))
402  return false;
403 
404  MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
405  if (!handleAssignments(Handler, ArgInfos, CCInfo, ArgLocs, MIRBuilder))
406  return false;
407 
408  if (F.isVarArg()) {
409  ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
410  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
411 
412  int VaArgOffset;
413  unsigned RegSize = 4;
414  if (ArgRegs.size() == Idx)
415  VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
416  else {
417  VaArgOffset =
418  (int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
419  (int)(RegSize * (ArgRegs.size() - Idx));
420  }
421 
422  MachineFrameInfo &MFI = MF.getFrameInfo();
423  int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
424  MF.getInfo<MipsFunctionInfo>()->setVarArgsFrameIndex(FI);
425 
426  for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
427  MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
428  LLT RegTy = LLT::scalar(RegSize * 8);
429  MachineInstrBuilder Copy =
430  MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I]));
431  FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
433 
434  const LLT PtrTy = LLT::pointer(MPO.getAddrSpace(), 32);
435  auto FrameIndex = MIRBuilder.buildFrameIndex(PtrTy, FI);
438  MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
439  }
440  }
441 
442  return true;
443 }
444 
446  CallLoweringInfo &Info) const {
447 
448  if (Info.CallConv != CallingConv::C)
449  return false;
450 
451  for (auto &Arg : Info.OrigArgs) {
452  if (!isSupportedArgumentType(Arg.Ty))
453  return false;
454  if (Arg.Flags[0].isByVal())
455  return false;
456  if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy())
457  return false;
458  }
459 
460  if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty))
461  return false;
462 
463  MachineFunction &MF = MIRBuilder.getMF();
464  const Function &F = MF.getFunction();
465  const DataLayout &DL = MF.getDataLayout();
466  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
467  const MipsTargetMachine &TM =
468  static_cast<const MipsTargetMachine &>(MF.getTarget());
469  const MipsABIInfo &ABI = TM.getABI();
470 
471  MachineInstrBuilder CallSeqStart =
472  MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
473 
474  const bool IsCalleeGlobalPIC =
475  Info.Callee.isGlobal() && TM.isPositionIndependent();
476 
477  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
478  Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
479  MIB.addDef(Mips::SP, RegState::Implicit);
480  if (IsCalleeGlobalPIC) {
481  Register CalleeReg =
483  MachineInstr *CalleeGlobalValue =
484  MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal());
485  if (!Info.Callee.getGlobal()->hasLocalLinkage())
486  CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
487  MIB.addUse(CalleeReg);
488  } else
489  MIB.add(Info.Callee);
491  MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
492 
493  TargetLowering::ArgListTy FuncOrigArgs;
494  FuncOrigArgs.reserve(Info.OrigArgs.size());
495 
496  SmallVector<ArgInfo, 8> ArgInfos;
497  for (auto &Arg : Info.OrigArgs)
498  splitToValueTypes(Arg, ArgInfos, DL, Info.CallConv);
499 
501  bool IsCalleeVarArg = false;
502  if (Info.Callee.isGlobal()) {
503  const Function *CF = static_cast<const Function *>(Info.Callee.getGlobal());
504  IsCalleeVarArg = CF->isVarArg();
505  }
506 
507  // FIXME: Should use MipsCCState::getSpecialCallingConvForCallee, but it
508  // depends on looking directly at the call target.
509  MipsCCState CCInfo(Info.CallConv, IsCalleeVarArg, MF, ArgLocs,
510  F.getContext());
511 
512  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv),
513  Align(1));
514 
515  const char *Call =
516  Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr;
517 
518  MipsOutgoingValueAssigner Assigner(TLI.CCAssignFnForCall(), Call,
519  /*IsReturn*/ false);
520  if (!determineAssignments(Assigner, ArgInfos, CCInfo))
521  return false;
522 
523  MipsOutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), MIB);
524  if (!handleAssignments(ArgHandler, ArgInfos, CCInfo, ArgLocs, MIRBuilder))
525  return false;
526 
527  unsigned NextStackOffset = CCInfo.getNextStackOffset();
528  unsigned StackAlignment = F.getParent()->getOverrideStackAlignment();
529  if (!StackAlignment) {
531  StackAlignment = TFL->getStackAlignment();
532  }
533  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
534  CallSeqStart.addImm(NextStackOffset).addImm(0);
535 
536  if (IsCalleeGlobalPIC) {
537  MIRBuilder.buildCopy(
538  Register(Mips::GP),
540  MIB.addDef(Mips::GP, RegState::Implicit);
541  }
542  MIRBuilder.insertInstr(MIB);
543  if (MIB->getOpcode() == Mips::JALRPseudo) {
544  const MipsSubtarget &STI =
545  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
546  MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
547  *STI.getRegBankInfo());
548  }
549 
550  if (!Info.OrigRet.Ty->isVoidTy()) {
551  ArgInfos.clear();
552 
553  CallLowering::splitToValueTypes(Info.OrigRet, ArgInfos, DL,
554  F.getCallingConv());
555 
556  const std::string FuncName = F.getName().str();
559  MipsIncomingValueAssigner Assigner(TLI.CCAssignFnForReturn(),
560  FuncName.c_str(),
561  /*IsReturn*/ true);
562  CallReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
563 
564  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
565  F.getContext());
566 
567  if (!determineAssignments(Assigner, ArgInfos, CCInfo))
568  return false;
569 
570  if (!handleAssignments(RetHandler, ArgInfos, CCInfo, ArgLocs, MIRBuilder))
571  return false;
572  }
573 
574  MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
575 
576  return true;
577 }
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm::MipsCCState::PreAnalyzeReturnValue
void PreAnalyzeReturnValue(EVT ArgVT)
Definition: MipsCCState.cpp:129
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:144
llvm::MipsCCState::PreAnalyzeFormalArgument
void PreAnalyzeFormalArgument(const Type *ArgTy, ISD::ArgFlagsTy Flags)
Definition: MipsCCState.cpp:157
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:126
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::MipsCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: MipsCallLowering.cpp:358
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::MipsCallLowering::MipsCallLowering
MipsCallLowering(const MipsTargetLowering &TLI)
Definition: MipsCallLowering.cpp:25
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:330
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:235
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:38
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
MachineIRBuilder.h
llvm::MipsSubtarget::getStackAlignment
Align getStackAlignment() const
Definition: MipsSubtarget.h:363
isSupportedReturnType
static bool isSupportedReturnType(Type *T)
Definition: MipsCallLowering.cpp:303
MipsTargetMachine.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::MipsSubtarget::getRegisterInfo
const MipsRegisterInfo * getRegisterInfo() const override
Definition: MipsSubtarget.h:389
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:95
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
MipsCallLowering.h
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:62
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MipsSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: MipsSubtarget.cpp:294
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:220
llvm::CallLowering::determineAssignments
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
Definition: CallLowering.cpp:557
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:269
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:315
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:223
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MipsCCState::PreAnalyzeCallResult
void PreAnalyzeCallResult(const Type *RetTy, const char *Func)
Definition: MipsCCState.h:145
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::MipsSubtarget::isLittle
bool isLittle() const
Definition: MipsSubtarget.h:284
llvm::MipsII::MO_GOT_CALL
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:411
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::MipsTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall() const
Definition: MipsISelLowering.cpp:3002
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:696
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:561
I
#define I(x, y, z)
Definition: MD5.cpp:58
Analysis.h
MipsMachineFunction.h
llvm::MipsCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: MipsCallLowering.cpp:445
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:257
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:294
llvm::pdb::PDB_SymType::Thunk
@ Thunk
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineInstrBuilder::constrainAllUses
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Definition: MachineInstrBuilder.h:320
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:374
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MipsFunctionInfo::getGlobalBaseRegForGlobalISel
Register getGlobalBaseRegForGlobalISel(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:54
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:43
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:278
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::ifs::IFSSymbolType::Func
@ Func
llvm::MipsTargetLowering
Definition: MipsISelLowering.h:264
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:981
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:310
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:376
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:135
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::CCState::getFirstUnallocated
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
Definition: CallingConvLower.h:334
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:228
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
MachineFrameInfo.h
llvm::CallLowering::handleAssignments
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=None) const
Use Handler to insert code to handle the argument/return values represented by Args.
Definition: CallLowering.cpp:618
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:214
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:423
MipsCCState.h
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:262
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:102
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:591
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:263
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:227
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:188
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
isSupportedArgumentType
static bool isSupportedArgumentType(Type *T)
Definition: MipsCallLowering.cpp:293
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:287
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallReturnHandler
Definition: M68kCallLowering.h:71
llvm::MipsCCState
Definition: MipsCCState.h:20
llvm::CallLowering::ValueAssigner::assignArg
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
Definition: CallLowering.h:182
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:415
llvm::MipsCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: MipsCallLowering.cpp:315
llvm::MipsCCState::PreAnalyzeCallOperand
void PreAnalyzeCallOperand(const Type *ArgTy, bool IsFixed, const char *Func)
Definition: MipsCCState.cpp:133
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::CallReturnHandler::CallReturnHandler
CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
Definition: M68kCallLowering.h:72
llvm::CallLowering
Definition: CallLowering.h:44
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1019
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:413
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
llvm::MipsTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn() const
Definition: MipsISelLowering.cpp:3006
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:177