LLVM  13.0.0git
MipsCallLowering.cpp
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1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsCallLowering.h"
16 #include "MipsCCState.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/CodeGen/Analysis.h"
21 
22 using namespace llvm;
23 
25  : CallLowering(&TLI) {}
26 
27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
28  const EVT &VT) {
29  if (VA.isRegLoc()) {
30  assignValueToReg(VReg, VA, VT);
31  } else if (VA.isMemLoc()) {
32  assignValueToAddress(VReg, VA);
33  } else {
34  return false;
35  }
36  return true;
37 }
38 
40  ArrayRef<CCValAssign> ArgLocs,
41  unsigned ArgLocsStartIndex,
42  const EVT &VT) {
43  for (unsigned i = 0; i < VRegs.size(); ++i)
44  if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
45  return false;
46  return true;
47 }
48 
51  if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
52  std::reverse(VRegs.begin(), VRegs.end());
53 }
54 
58  unsigned SplitLength;
59  const Function &F = MIRBuilder.getMF().getFunction();
60  const DataLayout &DL = F.getParent()->getDataLayout();
61  const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
62  MIRBuilder.getMF().getSubtarget().getTargetLowering());
63 
64  for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
65  ++ArgsIndex, ArgLocsIndex += SplitLength) {
66  EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
67  SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
68  F.getCallingConv(), VT);
69  assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet");
70 
71  if (SplitLength > 1) {
72  VRegs.clear();
73  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
74  F.getContext(), F.getCallingConv(), VT);
75  for (unsigned i = 0; i < SplitLength; ++i)
76  VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
77 
78  if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
79  VT))
80  return false;
81  } else {
82  if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
83  return false;
84  }
85  }
86  return true;
87 }
88 
89 namespace {
90 class MipsIncomingValueHandler : public MipsCallLowering::MipsHandler {
91 public:
92  MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder,
94  : MipsHandler(MIRBuilder, MRI) {}
95 
96 private:
97  void assignValueToReg(Register ValVReg, const CCValAssign &VA,
98  const EVT &VT) override;
99 
100  Register getStackAddress(const CCValAssign &VA,
101  MachineMemOperand *&MMO) override;
102 
103  void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
104 
105  bool handleSplit(SmallVectorImpl<Register> &VRegs,
106  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
107  Register ArgsReg, const EVT &VT) override;
108 
109  virtual void markPhysRegUsed(unsigned PhysReg) {
110  MIRBuilder.getMRI()->addLiveIn(PhysReg);
111  MIRBuilder.getMBB().addLiveIn(PhysReg);
112  }
113 
114  MachineInstrBuilder buildLoad(const DstOp &Res, const CCValAssign &VA) {
115  MachineMemOperand *MMO;
116  Register Addr = getStackAddress(VA, MMO);
117  return MIRBuilder.buildLoad(Res, Addr, *MMO);
118  }
119 };
120 
121 class CallReturnHandler : public MipsIncomingValueHandler {
122 public:
123  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
124  MachineInstrBuilder &MIB)
125  : MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
126 
127 private:
128  void markPhysRegUsed(unsigned PhysReg) override {
129  MIB.addDef(PhysReg, RegState::Implicit);
130  }
131 
132  MachineInstrBuilder &MIB;
133 };
134 
135 } // end anonymous namespace
136 
137 void MipsIncomingValueHandler::assignValueToReg(Register ValVReg,
138  const CCValAssign &VA,
139  const EVT &VT) {
140  Register PhysReg = VA.getLocReg();
141  if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
142  const MipsSubtarget &STI =
143  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
144  bool IsEL = STI.isLittle();
145  LLT s32 = LLT::scalar(32);
146  auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1)));
147  auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0)));
148  MIRBuilder.buildMerge(ValVReg, {Lo, Hi});
149  markPhysRegUsed(PhysReg);
150  markPhysRegUsed(PhysReg + 1);
151  } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
152  MIRBuilder.buildCopy(ValVReg, PhysReg);
153  markPhysRegUsed(PhysReg);
154  } else {
155  switch (VA.getLocInfo()) {
156  case CCValAssign::LocInfo::SExt:
157  case CCValAssign::LocInfo::ZExt:
158  case CCValAssign::LocInfo::AExt: {
159  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
160  MIRBuilder.buildTrunc(ValVReg, Copy);
161  break;
162  }
163  default:
164  MIRBuilder.buildCopy(ValVReg, PhysReg);
165  break;
166  }
167  markPhysRegUsed(PhysReg);
168  }
169 }
170 
171 Register MipsIncomingValueHandler::getStackAddress(const CCValAssign &VA,
172  MachineMemOperand *&MMO) {
173  MachineFunction &MF = MIRBuilder.getMF();
174  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
175  unsigned Offset = VA.getLocMemOffset();
176  MachineFrameInfo &MFI = MF.getFrameInfo();
177 
178  // FIXME: This should only be immutable for non-byval memory arguments.
179  int FI = MFI.CreateFixedObject(Size, Offset, true);
180  MachinePointerInfo MPO =
181  MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
182 
184  Align Alignment = commonAlignment(TFL->getStackAlign(), Offset);
185  MMO =
187 
188  return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
189 }
190 
191 void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
192  const CCValAssign &VA) {
193  if (VA.getLocInfo() == CCValAssign::SExt ||
194  VA.getLocInfo() == CCValAssign::ZExt ||
195  VA.getLocInfo() == CCValAssign::AExt) {
196  auto Load = buildLoad(LLT::scalar(32), VA);
197  MIRBuilder.buildTrunc(ValVReg, Load);
198  } else
199  buildLoad(ValVReg, VA);
200 }
201 
202 bool MipsIncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
203  ArrayRef<CCValAssign> ArgLocs,
204  unsigned ArgLocsStartIndex,
205  Register ArgsReg, const EVT &VT) {
206  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
207  return false;
208  setLeastSignificantFirst(VRegs);
209  MIRBuilder.buildMerge(ArgsReg, VRegs);
210  return true;
211 }
212 
213 namespace {
214 class MipsOutgoingValueHandler : public MipsCallLowering::MipsHandler {
215 public:
216  MipsOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
218  : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
219 
220 private:
221  void assignValueToReg(Register ValVReg, const CCValAssign &VA,
222  const EVT &VT) override;
223 
224  Register getStackAddress(const CCValAssign &VA,
225  MachineMemOperand *&MMO) override;
226 
227  void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
228 
229  bool handleSplit(SmallVectorImpl<Register> &VRegs,
230  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
231  Register ArgsReg, const EVT &VT) override;
232 
233  Register extendRegister(Register ValReg, const CCValAssign &VA);
234 
235  MachineInstrBuilder &MIB;
236 };
237 } // end anonymous namespace
238 
239 void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg,
240  const CCValAssign &VA,
241  const EVT &VT) {
242  Register PhysReg = VA.getLocReg();
243  if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
244  const MipsSubtarget &STI =
245  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
246  bool IsEL = STI.isLittle();
247  auto Unmerge = MIRBuilder.buildUnmerge(LLT::scalar(32), ValVReg);
248  MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 0 : 1)), Unmerge.getReg(0));
249  MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 1 : 0)), Unmerge.getReg(1));
250  } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
251  MIRBuilder.buildCopy(PhysReg, ValVReg);
252  } else {
253  Register ExtReg = extendRegister(ValVReg, VA);
254  MIRBuilder.buildCopy(PhysReg, ExtReg);
255  MIB.addUse(PhysReg, RegState::Implicit);
256  }
257 }
258 
259 Register MipsOutgoingValueHandler::getStackAddress(const CCValAssign &VA,
260  MachineMemOperand *&MMO) {
261  MachineFunction &MF = MIRBuilder.getMF();
263 
264  LLT p0 = LLT::pointer(0, 32);
265  LLT s32 = LLT::scalar(32);
266  auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP));
267 
268  unsigned Offset = VA.getLocMemOffset();
269  auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
270 
271  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
272 
273  MachinePointerInfo MPO =
274  MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
275  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
276  Align Alignment = commonAlignment(TFL->getStackAlign(), Offset);
277  MMO =
279 
280  return AddrReg.getReg(0);
281 }
282 
283 void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
284  const CCValAssign &VA) {
285  MachineMemOperand *MMO;
286  Register Addr = getStackAddress(VA, MMO);
287  Register ExtReg = extendRegister(ValVReg, VA);
288  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
289 }
290 
291 Register MipsOutgoingValueHandler::extendRegister(Register ValReg,
292  const CCValAssign &VA) {
293  LLT LocTy{VA.getLocVT()};
294  switch (VA.getLocInfo()) {
295  case CCValAssign::SExt: {
296  return MIRBuilder.buildSExt(LocTy, ValReg).getReg(0);
297  }
298  case CCValAssign::ZExt: {
299  return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0);
300  }
301  case CCValAssign::AExt: {
302  return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0);
303  }
304  // TODO : handle upper extends
305  case CCValAssign::Full:
306  return ValReg;
307  default:
308  break;
309  }
310  llvm_unreachable("unable to extend register");
311 }
312 
313 bool MipsOutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
314  ArrayRef<CCValAssign> ArgLocs,
315  unsigned ArgLocsStartIndex,
316  Register ArgsReg, const EVT &VT) {
317  MIRBuilder.buildUnmerge(VRegs, ArgsReg);
318  setLeastSignificantFirst(VRegs);
319  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
320  return false;
321 
322  return true;
323 }
324 
325 static bool isSupportedArgumentType(Type *T) {
326  if (T->isIntegerTy())
327  return true;
328  if (T->isPointerTy())
329  return true;
330  if (T->isFloatingPointTy())
331  return true;
332  return false;
333 }
334 
335 static bool isSupportedReturnType(Type *T) {
336  if (T->isIntegerTy())
337  return true;
338  if (T->isPointerTy())
339  return true;
340  if (T->isFloatingPointTy())
341  return true;
342  if (T->isAggregateType())
343  return true;
344  return false;
345 }
346 
347 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
348  const ISD::ArgFlagsTy &Flags) {
349  // > does not mean loss of information as type RegisterVT can't hold type VT,
350  // it means that type VT is split into multiple registers of type RegisterVT
351  if (VT.getFixedSizeInBits() >= RegisterVT.getFixedSizeInBits())
353  if (Flags.isSExt())
354  return CCValAssign::LocInfo::SExt;
355  if (Flags.isZExt())
356  return CCValAssign::LocInfo::ZExt;
357  return CCValAssign::LocInfo::AExt;
358 }
359 
360 template <typename T>
362  const SmallVectorImpl<T> &Arguments) {
363  for (unsigned i = 0; i < ArgLocs.size(); ++i) {
364  const CCValAssign &VA = ArgLocs[i];
366  Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
367  if (VA.isMemLoc())
368  ArgLocs[i] =
370  VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
371  else
372  ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
373  VA.getLocReg(), VA.getLocVT(), LocInfo);
374  }
375 }
376 
378  const Value *Val, ArrayRef<Register> VRegs,
379  FunctionLoweringInfo &FLI) const {
380 
381  MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
382 
383  if (Val != nullptr && !isSupportedReturnType(Val->getType()))
384  return false;
385 
386  if (!VRegs.empty()) {
387  MachineFunction &MF = MIRBuilder.getMF();
388  const Function &F = MF.getFunction();
389  const DataLayout &DL = MF.getDataLayout();
390  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
391 
392  SmallVector<ArgInfo, 8> RetInfos;
393  SmallVector<unsigned, 8> OrigArgIndices;
394 
395  ArgInfo ArgRetInfo(VRegs, Val->getType());
397  splitToValueTypes(DL, ArgRetInfo, 0, RetInfos, OrigArgIndices);
398 
400  subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
401 
403  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
404  F.getContext());
405  CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
406  setLocInfo(ArgLocs, Outs);
407 
408  MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
409  if (!RetHandler.handle(ArgLocs, RetInfos)) {
410  return false;
411  }
412  }
413  MIRBuilder.insertInstr(Ret);
414  return true;
415 }
416 
418  const Function &F,
420  FunctionLoweringInfo &FLI) const {
421 
422  // Quick exit if there aren't any args.
423  if (F.arg_empty())
424  return true;
425 
426  for (auto &Arg : F.args()) {
427  if (!isSupportedArgumentType(Arg.getType()))
428  return false;
429  }
430 
431  MachineFunction &MF = MIRBuilder.getMF();
432  const DataLayout &DL = MF.getDataLayout();
433  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
434 
435  SmallVector<ArgInfo, 8> ArgInfos;
436  SmallVector<unsigned, 8> OrigArgIndices;
437  unsigned i = 0;
438  for (auto &Arg : F.args()) {
439  ArgInfo AInfo(VRegs[i], Arg.getType());
441  ArgInfos.push_back(AInfo);
442  OrigArgIndices.push_back(i);
443  ++i;
444  }
445 
447  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
448 
450  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
451  F.getContext());
452 
453  const MipsTargetMachine &TM =
454  static_cast<const MipsTargetMachine &>(MF.getTarget());
455  const MipsABIInfo &ABI = TM.getABI();
456  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
457  Align(1));
459  setLocInfo(ArgLocs, Ins);
460 
461  MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
462  if (!Handler.handle(ArgLocs, ArgInfos))
463  return false;
464 
465  if (F.isVarArg()) {
466  ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
467  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
468 
469  int VaArgOffset;
470  unsigned RegSize = 4;
471  if (ArgRegs.size() == Idx)
472  VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
473  else {
474  VaArgOffset =
475  (int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
476  (int)(RegSize * (ArgRegs.size() - Idx));
477  }
478 
479  MachineFrameInfo &MFI = MF.getFrameInfo();
480  int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
481  MF.getInfo<MipsFunctionInfo>()->setVarArgsFrameIndex(FI);
482 
483  for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
484  MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
485 
486  MachineInstrBuilder Copy =
487  MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
488  FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
491  MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI);
493  MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize));
494  MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
495  }
496  }
497 
498  return true;
499 }
500 
502  CallLoweringInfo &Info) const {
503 
504  if (Info.CallConv != CallingConv::C)
505  return false;
506 
507  for (auto &Arg : Info.OrigArgs) {
508  if (!isSupportedArgumentType(Arg.Ty))
509  return false;
510  if (Arg.Flags[0].isByVal())
511  return false;
512  if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy())
513  return false;
514  }
515 
516  if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty))
517  return false;
518 
519  MachineFunction &MF = MIRBuilder.getMF();
520  const Function &F = MF.getFunction();
521  const DataLayout &DL = MF.getDataLayout();
522  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
523  const MipsTargetMachine &TM =
524  static_cast<const MipsTargetMachine &>(MF.getTarget());
525  const MipsABIInfo &ABI = TM.getABI();
526 
527  MachineInstrBuilder CallSeqStart =
528  MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
529 
530  const bool IsCalleeGlobalPIC =
531  Info.Callee.isGlobal() && TM.isPositionIndependent();
532 
533  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
534  Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
535  MIB.addDef(Mips::SP, RegState::Implicit);
536  if (IsCalleeGlobalPIC) {
537  Register CalleeReg =
539  MachineInstr *CalleeGlobalValue =
540  MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal());
541  if (!Info.Callee.getGlobal()->hasLocalLinkage())
542  CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
543  MIB.addUse(CalleeReg);
544  } else
545  MIB.add(Info.Callee);
547  MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
548 
549  TargetLowering::ArgListTy FuncOrigArgs;
550  FuncOrigArgs.reserve(Info.OrigArgs.size());
551 
552  SmallVector<ArgInfo, 8> ArgInfos;
553  SmallVector<unsigned, 8> OrigArgIndices;
554  unsigned i = 0;
555  for (auto &Arg : Info.OrigArgs) {
556 
558  Entry.Ty = Arg.Ty;
559  FuncOrigArgs.push_back(Entry);
560 
561  ArgInfos.push_back(Arg);
562  OrigArgIndices.push_back(i);
563  ++i;
564  }
565 
567  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
568 
570  bool IsCalleeVarArg = false;
571  if (Info.Callee.isGlobal()) {
572  const Function *CF = static_cast<const Function *>(Info.Callee.getGlobal());
573  IsCalleeVarArg = CF->isVarArg();
574  }
575  MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs,
576  F.getContext());
577 
578  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv),
579  Align(1));
580  const char *Call =
581  Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr;
582  CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
583  setLocInfo(ArgLocs, Outs);
584 
585  MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
586  if (!RetHandler.handle(ArgLocs, ArgInfos)) {
587  return false;
588  }
589 
590  unsigned NextStackOffset = CCInfo.getNextStackOffset();
592  unsigned StackAlignment = TFL->getStackAlignment();
593  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
594  CallSeqStart.addImm(NextStackOffset).addImm(0);
595 
596  if (IsCalleeGlobalPIC) {
597  MIRBuilder.buildCopy(
598  Register(Mips::GP),
600  MIB.addDef(Mips::GP, RegState::Implicit);
601  }
602  MIRBuilder.insertInstr(MIB);
603  if (MIB->getOpcode() == Mips::JALRPseudo) {
604  const MipsSubtarget &STI =
605  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
606  MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
607  *STI.getRegBankInfo());
608  }
609 
610  if (!Info.OrigRet.Ty->isVoidTy()) {
611  ArgInfos.clear();
612  SmallVector<unsigned, 8> OrigRetIndices;
613 
614  splitToValueTypes(DL, Info.OrigRet, 0, ArgInfos, OrigRetIndices);
615 
617  subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
618 
620  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
621  F.getContext());
622 
623  CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty,
624  Call);
625  setLocInfo(ArgLocs, Ins);
626 
627  CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
628  if (!Handler.handle(ArgLocs, ArgInfos))
629  return false;
630  }
631 
632  MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
633 
634  return true;
635 }
636 
637 template <typename T>
638 void MipsCallLowering::subTargetRegTypeForCallingConv(
640  ArrayRef<unsigned> OrigArgIndices, SmallVectorImpl<T> &ISDArgs) const {
641  const DataLayout &DL = F.getParent()->getDataLayout();
642  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
643 
644  unsigned ArgNo = 0;
645  for (auto &Arg : Args) {
646 
647  EVT VT = TLI.getValueType(DL, Arg.Ty);
648  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
649  F.getCallingConv(), VT);
650  unsigned NumRegs = TLI.getNumRegistersForCallingConv(
651  F.getContext(), F.getCallingConv(), VT);
652 
653  for (unsigned i = 0; i < NumRegs; ++i) {
654  ISD::ArgFlagsTy Flags = Arg.Flags[0];
655 
656  if (i == 0)
658  else
659  Flags.setOrigAlign(Align(1));
660 
661  ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
662  0);
663  }
664  ++ArgNo;
665  }
666 }
667 
668 // FIXME: This should be removed and the generic version used
669 void MipsCallLowering::splitToValueTypes(
670  const DataLayout &DL, const ArgInfo &OrigArg, unsigned OriginalIndex,
671  SmallVectorImpl<ArgInfo> &SplitArgs,
672  SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
673 
674  SmallVector<EVT, 4> SplitEVTs;
675  SmallVector<Register, 4> SplitVRegs;
676  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
677  LLVMContext &Ctx = OrigArg.Ty->getContext();
678 
679  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitEVTs);
680 
681  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
682  ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
683  Info.Flags = OrigArg.Flags;
684  SplitArgs.push_back(Info);
685  SplitArgsOrigIndices.push_back(OriginalIndex);
686  }
687 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MipsCallLowering::MipsHandler::assignVRegs
bool assignVRegs(ArrayRef< Register > VRegs, ArrayRef< CCValAssign > ArgLocs, unsigned ArgLocsStartIndex, const EVT &VT)
Definition: MipsCallLowering.cpp:39
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:158
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
llvm::MipsTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: MipsISelLowering.cpp:111
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1000
llvm::MipsCCState::AnalyzeCallOperands
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn, std::vector< TargetLowering::ArgListEntry > &FuncArgs, const char *Func)
Definition: MipsCCState.h:89
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:42
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::EVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: ValueTypes.h:341
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Function
Definition: Function.h:61
llvm::MipsTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: MipsISelLowering.cpp:121
setLocInfo
static void setLocInfo(SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< T > &Arguments)
Definition: MipsCallLowering.cpp:361
llvm::MipsCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: MipsCallLowering.cpp:417
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::MipsCallLowering::MipsCallLowering
MipsCallLowering(const MipsTargetLowering &TLI)
Definition: MipsCallLowering.cpp:24
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:71
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:338
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
MachineIRBuilder.h
isSupportedReturnType
static bool isSupportedReturnType(Type *T)
Definition: MipsCallLowering.cpp:335
MipsTargetMachine.h
llvm::JumpTable::Full
@ Full
Definition: TargetOptions.h:50
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::MipsSubtarget::getRegisterInfo
const MipsRegisterInfo * getRegisterInfo() const override
Definition: MipsSubtarget.h:386
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:117
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:94
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
MipsCallLowering.h
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:150
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:99
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MipsSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: MipsSubtarget.cpp:289
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:221
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:47
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:145
llvm::MipsCallLowering::MipsHandler::setLeastSignificantFirst
void setLeastSignificantFirst(SmallVectorImpl< Register > &VRegs)
Definition: MipsCallLowering.cpp:49
llvm::MipsCCState::AnalyzeFormalArguments
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
Definition: MipsCCState.h:110
llvm::MipsSubtarget::isLittle
bool isLittle() const
Definition: MipsSubtarget.h:281
llvm::MipsII::MO_GOT_CALL
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:388
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MipsTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall() const
Definition: MipsISelLowering.cpp:2984
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::codeview::FrameCookieKind::Copy
@ Copy
I
#define I(x, y, z)
Definition: MD5.cpp:59
Analysis.h
MipsMachineFunction.h
llvm::MipsCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: MipsCallLowering.cpp:501
llvm::MipsTargetLowering::getABIAlignmentForCallingConv
Align getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
Definition: MipsISelLowering.h:305
llvm::ISD::ArgFlagsTy::setOrigAlign
void setOrigAlign(Align A)
Definition: TargetCallingConv.h:159
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:102
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:259
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:815
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:270
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:295
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::MipsCallLowering::MipsHandler
Definition: MipsCallLowering.h:27
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:124
llvm::MachineInstrBuilder::constrainAllUses
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Definition: MachineInstrBuilder.h:321
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:375
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:142
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:198
llvm::MipsCCState::AnalyzeCallResult
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:119
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::MipsFunctionInfo::getGlobalBaseRegForGlobalISel
Register getGlobalBaseRegForGlobalISel(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:54
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:478
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsTargetLowering
Definition: MipsISelLowering.h:261
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:970
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:300
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::CCState::getFirstUnallocated
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
Definition: CallingConvLower.h:336
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:146
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:221
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
determineLocInfo
static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, const ISD::ArgFlagsTy &Flags)
Definition: MipsCallLowering.cpp:347
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:74
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:425
MipsCCState.h
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:95
Arguments
AMDGPU Lower Kernel Arguments
Definition: AMDGPULowerKernelArguments.cpp:243
llvm::MipsCallLowering::MipsHandler::handle
bool handle(ArrayRef< CCValAssign > ArgLocs, ArrayRef< CallLowering::ArgInfo > Args)
Definition: MipsCallLowering.cpp:55
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::MipsCCState::AnalyzeReturn
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: MipsCCState.h:130
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:264
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:178
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
isSupportedArgumentType
static bool isSupportedArgumentType(Type *T)
Definition: MipsCallLowering.cpp:325
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:79
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MipsCCState
Definition: MipsCCState.h:20
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:388
llvm::MipsCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: MipsCallLowering.cpp:377
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1382
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::CallLowering
Definition: CallLowering.h:43
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:52
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1008
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:390
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:471
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::MipsTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn() const
Definition: MipsISelLowering.cpp:2988
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:150