LLVM 18.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {
38 initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry());
39 }
40
41 bool runOnMachineFunction(MachineFunction &MF) override;
42
43 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
44
45private:
46 bool expandMBB(MachineBasicBlock &MBB);
47 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
50 MachineBasicBlock::iterator &NextMBBI);
51 bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
52 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI, unsigned Opcode);
54 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MBBI);
56 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator MBBI);
58#ifndef NDEBUG
59 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
60 unsigned Size = 0;
61 for (auto &MBB : MF)
62 for (auto &MI : MBB)
63 Size += TII->getInstSizeInBytes(MI);
64 return Size;
65 }
66#endif
67};
68
69char RISCVExpandPseudo::ID = 0;
70
71bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
72 STI = &MF.getSubtarget<RISCVSubtarget>();
73 TII = STI->getInstrInfo();
74
75#ifndef NDEBUG
76 const unsigned OldSize = getInstSizeInBytes(MF);
77#endif
78
79 bool Modified = false;
80 for (auto &MBB : MF)
81 Modified |= expandMBB(MBB);
82
83#ifndef NDEBUG
84 const unsigned NewSize = getInstSizeInBytes(MF);
85 assert(OldSize >= NewSize);
86#endif
87 return Modified;
88}
89
90bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
91 bool Modified = false;
92
93 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
94 while (MBBI != E) {
95 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
96 Modified |= expandMI(MBB, MBBI, NMBBI);
97 MBBI = NMBBI;
98 }
99
100 return Modified;
101}
102
103bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator MBBI,
105 MachineBasicBlock::iterator &NextMBBI) {
106 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
107 // expanded instructions for each pseudo is correct in the Size field of the
108 // tablegen definition for the pseudo.
109 switch (MBBI->getOpcode()) {
110 case RISCV::PseudoRV32ZdinxSD:
111 return expandRV32ZdinxStore(MBB, MBBI);
112 case RISCV::PseudoRV32ZdinxLD:
113 return expandRV32ZdinxLoad(MBB, MBBI);
114 case RISCV::PseudoCCMOVGPR:
115 case RISCV::PseudoCCADD:
116 case RISCV::PseudoCCSUB:
117 case RISCV::PseudoCCAND:
118 case RISCV::PseudoCCOR:
119 case RISCV::PseudoCCXOR:
120 case RISCV::PseudoCCADDW:
121 case RISCV::PseudoCCSUBW:
122 case RISCV::PseudoCCSLL:
123 case RISCV::PseudoCCSRL:
124 case RISCV::PseudoCCSRA:
125 case RISCV::PseudoCCADDI:
126 case RISCV::PseudoCCSLLI:
127 case RISCV::PseudoCCSRLI:
128 case RISCV::PseudoCCSRAI:
129 case RISCV::PseudoCCANDI:
130 case RISCV::PseudoCCORI:
131 case RISCV::PseudoCCXORI:
132 case RISCV::PseudoCCSLLW:
133 case RISCV::PseudoCCSRLW:
134 case RISCV::PseudoCCSRAW:
135 case RISCV::PseudoCCADDIW:
136 case RISCV::PseudoCCSLLIW:
137 case RISCV::PseudoCCSRLIW:
138 case RISCV::PseudoCCSRAIW:
139 return expandCCOp(MBB, MBBI, NextMBBI);
140 case RISCV::PseudoVSETVLI:
141 case RISCV::PseudoVSETVLIX0:
142 case RISCV::PseudoVSETIVLI:
143 return expandVSetVL(MBB, MBBI);
144 case RISCV::PseudoVMCLR_M_B1:
145 case RISCV::PseudoVMCLR_M_B2:
146 case RISCV::PseudoVMCLR_M_B4:
147 case RISCV::PseudoVMCLR_M_B8:
148 case RISCV::PseudoVMCLR_M_B16:
149 case RISCV::PseudoVMCLR_M_B32:
150 case RISCV::PseudoVMCLR_M_B64:
151 // vmclr.m vd => vmxor.mm vd, vd, vd
152 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
153 case RISCV::PseudoVMSET_M_B1:
154 case RISCV::PseudoVMSET_M_B2:
155 case RISCV::PseudoVMSET_M_B4:
156 case RISCV::PseudoVMSET_M_B8:
157 case RISCV::PseudoVMSET_M_B16:
158 case RISCV::PseudoVMSET_M_B32:
159 case RISCV::PseudoVMSET_M_B64:
160 // vmset.m vd => vmxnor.mm vd, vd, vd
161 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
162 }
163
164 return false;
165}
166
167bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
168 MachineBasicBlock::iterator MBBI,
169 MachineBasicBlock::iterator &NextMBBI) {
170
171 MachineFunction *MF = MBB.getParent();
172 MachineInstr &MI = *MBBI;
173 DebugLoc DL = MI.getDebugLoc();
174
175 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
176 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
177
178 MF->insert(++MBB.getIterator(), TrueBB);
179 MF->insert(++TrueBB->getIterator(), MergeBB);
180
181 // We want to copy the "true" value when the condition is true which means
182 // we need to invert the branch condition to jump over TrueBB when the
183 // condition is false.
184 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
185 CC = RISCVCC::getOppositeBranchCondition(CC);
186
187 // Insert branch instruction.
188 BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
189 .addReg(MI.getOperand(1).getReg())
190 .addReg(MI.getOperand(2).getReg())
191 .addMBB(MergeBB);
192
193 Register DestReg = MI.getOperand(0).getReg();
194 assert(MI.getOperand(4).getReg() == DestReg);
195
196 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR) {
197 // Add MV.
198 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
199 .add(MI.getOperand(5))
200 .addImm(0);
201 } else {
202 unsigned NewOpc;
203 switch (MI.getOpcode()) {
204 default:
205 llvm_unreachable("Unexpected opcode!");
206 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
207 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
208 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
209 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
210 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
211 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
212 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
213 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
214 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
215 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
216 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
217 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
218 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
219 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
220 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
221 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
222 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
223 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
224 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
225 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
226 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
227 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
228 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
229 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
230 }
231 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
232 .add(MI.getOperand(5))
233 .add(MI.getOperand(6));
234 }
235
236 TrueBB->addSuccessor(MergeBB);
237
238 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
239 MergeBB->transferSuccessors(&MBB);
240
241 MBB.addSuccessor(TrueBB);
242 MBB.addSuccessor(MergeBB);
243
244 NextMBBI = MBB.end();
245 MI.eraseFromParent();
246
247 // Make sure live-ins are correctly attached to this new basic block.
248 LivePhysRegs LiveRegs;
249 computeAndAddLiveIns(LiveRegs, *TrueBB);
250 computeAndAddLiveIns(LiveRegs, *MergeBB);
251
252 return true;
253}
254
255bool RISCVExpandPseudo::expandVSetVL(MachineBasicBlock &MBB,
256 MachineBasicBlock::iterator MBBI) {
257 assert(MBBI->getNumExplicitOperands() == 3 && MBBI->getNumOperands() >= 5 &&
258 "Unexpected instruction format");
259
260 DebugLoc DL = MBBI->getDebugLoc();
261
262 assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
263 MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
264 MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&
265 "Unexpected pseudo instruction");
266 unsigned Opcode;
267 if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI)
268 Opcode = RISCV::VSETIVLI;
269 else
270 Opcode = RISCV::VSETVLI;
271 const MCInstrDesc &Desc = TII->get(Opcode);
272 assert(Desc.getNumOperands() == 3 && "Unexpected instruction format");
273
274 Register DstReg = MBBI->getOperand(0).getReg();
275 bool DstIsDead = MBBI->getOperand(0).isDead();
276 BuildMI(MBB, MBBI, DL, Desc)
277 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
278 .add(MBBI->getOperand(1)) // VL
279 .add(MBBI->getOperand(2)); // VType
280
281 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
282 return true;
283}
284
285bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MBBI,
287 unsigned Opcode) {
288 DebugLoc DL = MBBI->getDebugLoc();
289 Register DstReg = MBBI->getOperand(0).getReg();
290 const MCInstrDesc &Desc = TII->get(Opcode);
291 BuildMI(MBB, MBBI, DL, Desc, DstReg)
292 .addReg(DstReg, RegState::Undef)
293 .addReg(DstReg, RegState::Undef);
294 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
295 return true;
296}
297
298// This function expands the PseudoRV32ZdinxSD for storing a double-precision
299// floating-point value into memory by generating an equivalent instruction
300// sequence for RV32.
301bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
302 MachineBasicBlock::iterator MBBI) {
303 DebugLoc DL = MBBI->getDebugLoc();
304 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
305 Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
306 Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
307 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
308 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
309 .addReg(MBBI->getOperand(1).getReg())
310 .add(MBBI->getOperand(2));
311 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
312 // FIXME: Zdinx RV32 can not work on unaligned scalar memory.
313 assert(!STI->enableUnalignedScalarMem());
314
315 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
316 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
317 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
318 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
319 .add(MBBI->getOperand(1))
320 .add(MBBI->getOperand(2));
321 } else {
322 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
323 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
324 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
325 .add(MBBI->getOperand(1))
326 .addImm(MBBI->getOperand(2).getImm() + 4);
327 }
328 MBBI->eraseFromParent();
329 return true;
330}
331
332// This function expands PseudoRV32ZdinxLoad for loading a double-precision
333// floating-point value from memory into an equivalent instruction sequence for
334// RV32.
335bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
336 MachineBasicBlock::iterator MBBI) {
337 DebugLoc DL = MBBI->getDebugLoc();
338 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
339 Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
340 Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
341
342 // If the register of operand 1 is equal to the Lo register, then swap the
343 // order of loading the Lo and Hi statements.
344 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
345 // Order: Lo, Hi
346 if (!IsOp1EqualToLo) {
347 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
348 .addReg(MBBI->getOperand(1).getReg())
349 .add(MBBI->getOperand(2));
350 }
351
352 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
353 auto Offset = MBBI->getOperand(2).getOffset();
354 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
355 MBBI->getOperand(2).setOffset(Offset + 4);
356 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
357 .addReg(MBBI->getOperand(1).getReg())
358 .add(MBBI->getOperand(2));
359 MBBI->getOperand(2).setOffset(Offset);
360 } else {
361 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
362 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
363 .addReg(MBBI->getOperand(1).getReg())
364 .addImm(MBBI->getOperand(2).getImm() + 4);
365 }
366
367 // Order: Hi, Lo
368 if (IsOp1EqualToLo) {
369 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
370 .addReg(MBBI->getOperand(1).getReg())
371 .add(MBBI->getOperand(2));
372 }
373
374 MBBI->eraseFromParent();
375 return true;
376}
377
378class RISCVPreRAExpandPseudo : public MachineFunctionPass {
379public:
380 const RISCVSubtarget *STI;
381 const RISCVInstrInfo *TII;
382 static char ID;
383
384 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {
385 initializeRISCVPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
386 }
387
388 bool runOnMachineFunction(MachineFunction &MF) override;
389
390 void getAnalysisUsage(AnalysisUsage &AU) const override {
391 AU.setPreservesCFG();
392 MachineFunctionPass::getAnalysisUsage(AU);
393 }
394 StringRef getPassName() const override {
395 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
396 }
397
398private:
399 bool expandMBB(MachineBasicBlock &MBB);
400 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
401 MachineBasicBlock::iterator &NextMBBI);
402 bool expandAuipcInstPair(MachineBasicBlock &MBB,
403 MachineBasicBlock::iterator MBBI,
404 MachineBasicBlock::iterator &NextMBBI,
405 unsigned FlagsHi, unsigned SecondOpcode);
406 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
407 MachineBasicBlock::iterator MBBI,
408 MachineBasicBlock::iterator &NextMBBI);
409 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
410 MachineBasicBlock::iterator MBBI,
411 MachineBasicBlock::iterator &NextMBBI);
412 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
413 MachineBasicBlock::iterator MBBI,
414 MachineBasicBlock::iterator &NextMBBI);
415 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator MBBI,
417 MachineBasicBlock::iterator &NextMBBI);
418#ifndef NDEBUG
419 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
420 unsigned Size = 0;
421 for (auto &MBB : MF)
422 for (auto &MI : MBB)
423 Size += TII->getInstSizeInBytes(MI);
424 return Size;
425 }
426#endif
427};
428
429char RISCVPreRAExpandPseudo::ID = 0;
430
431bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
432 STI = &MF.getSubtarget<RISCVSubtarget>();
433 TII = STI->getInstrInfo();
434
435#ifndef NDEBUG
436 const unsigned OldSize = getInstSizeInBytes(MF);
437#endif
438
439 bool Modified = false;
440 for (auto &MBB : MF)
441 Modified |= expandMBB(MBB);
442
443#ifndef NDEBUG
444 const unsigned NewSize = getInstSizeInBytes(MF);
445 assert(OldSize >= NewSize);
446#endif
447 return Modified;
448}
449
450bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
451 bool Modified = false;
452
453 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
454 while (MBBI != E) {
455 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
456 Modified |= expandMI(MBB, MBBI, NMBBI);
457 MBBI = NMBBI;
458 }
459
460 return Modified;
461}
462
463bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
464 MachineBasicBlock::iterator MBBI,
465 MachineBasicBlock::iterator &NextMBBI) {
466
467 switch (MBBI->getOpcode()) {
468 case RISCV::PseudoLLA:
469 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
470 case RISCV::PseudoLGA:
471 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
472 case RISCV::PseudoLA_TLS_IE:
473 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
474 case RISCV::PseudoLA_TLS_GD:
475 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
476 }
477 return false;
478}
479
480bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
481 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
482 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
483 unsigned SecondOpcode) {
484 MachineFunction *MF = MBB.getParent();
485 MachineInstr &MI = *MBBI;
486 DebugLoc DL = MI.getDebugLoc();
487
488 Register DestReg = MI.getOperand(0).getReg();
489 Register ScratchReg =
490 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
491
492 MachineOperand &Symbol = MI.getOperand(1);
493 Symbol.setTargetFlags(FlagsHi);
494 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
495
496 MachineInstr *MIAUIPC =
497 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
498 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
499
500 MachineInstr *SecondMI =
501 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
502 .addReg(ScratchReg)
503 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
504
505 if (MI.hasOneMemOperand())
506 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
507
508 MI.eraseFromParent();
509 return true;
510}
511
512bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
513 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
514 MachineBasicBlock::iterator &NextMBBI) {
515 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
516 RISCV::ADDI);
517}
518
519bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
520 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
521 MachineBasicBlock::iterator &NextMBBI) {
522 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
523 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
524 SecondOpcode);
525}
526
527bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
528 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
529 MachineBasicBlock::iterator &NextMBBI) {
530 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
531 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
532 SecondOpcode);
533}
534
535bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
536 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
537 MachineBasicBlock::iterator &NextMBBI) {
538 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
539 RISCV::ADDI);
540}
541
542} // end of anonymous namespace
543
544INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
545 RISCV_EXPAND_PSEUDO_NAME, false, false)
546
547INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
548 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
549
550namespace llvm {
551
552FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
553FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
554
555} // end of namespace llvm
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition: GlobPattern.cpp:21
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1868
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition: RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition: RISCVExpandPseudoInsts.cpp:26
pseudo
riscv prera expand pseudo
Definition: RISCVExpandPseudoInsts.cpp:547
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition: SystemZLongBranch.cpp:214
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::MCContext::createNamedTempSymbol
MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition: MCContext.cpp:324
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineBasicBlock::transferSuccessors
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition: MachineBasicBlock.cpp:907
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:222
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:788
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1433
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:274
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1043
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
llvm::MachineFunctionPass::runOnMachineFunction
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:454
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:708
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:660
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:718
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:931
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:268
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:147
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:68
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:467
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:373
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:157
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::Pass::getPassName
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
INITIALIZE_PASS
TargetPassConfig.
Definition: TargetPassConfig.cpp:358
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVCC::getOppositeBranchCondition
CondCode getOppositeBranchCondition(CondCode)
Definition: RISCVInstrInfo.cpp:835
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:45
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:53
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:440
llvm::initializeRISCVExpandPseudoPass
void initializeRISCVExpandPseudoPass(PassRegistry &)
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:363
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:540
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:537
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition: LivePhysRegs.cpp:336
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:552
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:553
llvm::initializeRISCVPreRAExpandPseudoPass
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
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