LLVM 22.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOpToCMov(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI);
51 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI);
63#ifndef NDEBUG
64 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
65 unsigned Size = 0;
66 for (auto &MBB : MF)
67 for (auto &MI : MBB)
68 Size += TII->getInstSizeInBytes(MI);
69 return Size;
70 }
71#endif
72};
73
74char RISCVExpandPseudo::ID = 0;
75
76bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
77 STI = &MF.getSubtarget<RISCVSubtarget>();
78 TII = STI->getInstrInfo();
79
80#ifndef NDEBUG
81 const unsigned OldSize = getInstSizeInBytes(MF);
82#endif
83
84 bool Modified = false;
85 for (auto &MBB : MF)
86 Modified |= expandMBB(MBB);
87
88#ifndef NDEBUG
89 const unsigned NewSize = getInstSizeInBytes(MF);
90 assert(OldSize >= NewSize);
91#endif
92 return Modified;
93}
94
95bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
96 bool Modified = false;
97
98 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
99 while (MBBI != E) {
100 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
101 Modified |= expandMI(MBB, MBBI, NMBBI);
102 MBBI = NMBBI;
103 }
104
105 return Modified;
106}
107
108bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MBBI,
110 MachineBasicBlock::iterator &NextMBBI) {
111 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
112 // expanded instructions for each pseudo is correct in the Size field of the
113 // tablegen definition for the pseudo.
114 switch (MBBI->getOpcode()) {
115 case RISCV::PseudoMV_FPR16INX:
116 return expandMV_FPR16INX(MBB, MBBI);
117 case RISCV::PseudoMV_FPR32INX:
118 return expandMV_FPR32INX(MBB, MBBI);
119 case RISCV::PseudoRV32ZdinxSD:
120 return expandRV32ZdinxStore(MBB, MBBI);
121 case RISCV::PseudoRV32ZdinxLD:
122 return expandRV32ZdinxLoad(MBB, MBBI);
123 case RISCV::PseudoCCMOVGPRNoX0:
124 case RISCV::PseudoCCMOVGPR:
125 case RISCV::PseudoCCADD:
126 case RISCV::PseudoCCSUB:
127 case RISCV::PseudoCCAND:
128 case RISCV::PseudoCCOR:
129 case RISCV::PseudoCCXOR:
130 case RISCV::PseudoCCMAX:
131 case RISCV::PseudoCCMAXU:
132 case RISCV::PseudoCCMIN:
133 case RISCV::PseudoCCMINU:
134 case RISCV::PseudoCCMUL:
135 case RISCV::PseudoCCLUI:
136 case RISCV::PseudoCCQC_E_LB:
137 case RISCV::PseudoCCQC_E_LH:
138 case RISCV::PseudoCCQC_E_LW:
139 case RISCV::PseudoCCQC_E_LHU:
140 case RISCV::PseudoCCQC_E_LBU:
141 case RISCV::PseudoCCLB:
142 case RISCV::PseudoCCLH:
143 case RISCV::PseudoCCLW:
144 case RISCV::PseudoCCLHU:
145 case RISCV::PseudoCCLBU:
146 case RISCV::PseudoCCLWU:
147 case RISCV::PseudoCCLD:
148 case RISCV::PseudoCCQC_LI:
149 case RISCV::PseudoCCQC_E_LI:
150 case RISCV::PseudoCCADDW:
151 case RISCV::PseudoCCSUBW:
152 case RISCV::PseudoCCSLL:
153 case RISCV::PseudoCCSRL:
154 case RISCV::PseudoCCSRA:
155 case RISCV::PseudoCCADDI:
156 case RISCV::PseudoCCSLLI:
157 case RISCV::PseudoCCSRLI:
158 case RISCV::PseudoCCSRAI:
159 case RISCV::PseudoCCANDI:
160 case RISCV::PseudoCCORI:
161 case RISCV::PseudoCCXORI:
162 case RISCV::PseudoCCSLLW:
163 case RISCV::PseudoCCSRLW:
164 case RISCV::PseudoCCSRAW:
165 case RISCV::PseudoCCADDIW:
166 case RISCV::PseudoCCSLLIW:
167 case RISCV::PseudoCCSRLIW:
168 case RISCV::PseudoCCSRAIW:
169 case RISCV::PseudoCCANDN:
170 case RISCV::PseudoCCORN:
171 case RISCV::PseudoCCXNOR:
172 case RISCV::PseudoCCNDS_BFOS:
173 case RISCV::PseudoCCNDS_BFOZ:
174 return expandCCOp(MBB, MBBI, NextMBBI);
175 case RISCV::PseudoVMCLR_M_B1:
176 case RISCV::PseudoVMCLR_M_B2:
177 case RISCV::PseudoVMCLR_M_B4:
178 case RISCV::PseudoVMCLR_M_B8:
179 case RISCV::PseudoVMCLR_M_B16:
180 case RISCV::PseudoVMCLR_M_B32:
181 case RISCV::PseudoVMCLR_M_B64:
182 // vmclr.m vd => vmxor.mm vd, vd, vd
183 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
184 case RISCV::PseudoVMSET_M_B1:
185 case RISCV::PseudoVMSET_M_B2:
186 case RISCV::PseudoVMSET_M_B4:
187 case RISCV::PseudoVMSET_M_B8:
188 case RISCV::PseudoVMSET_M_B16:
189 case RISCV::PseudoVMSET_M_B32:
190 case RISCV::PseudoVMSET_M_B64:
191 // vmset.m vd => vmxnor.mm vd, vd, vd
192 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
193 case RISCV::PseudoReadVLENBViaVSETVLIX0:
194 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
195 }
196
197 return false;
198}
199
200bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MBBI,
202 MachineBasicBlock::iterator &NextMBBI) {
203 // First try expanding to a Conditional Move rather than a branch+mv
204 if (expandCCOpToCMov(MBB, MBBI))
205 return true;
206
207 MachineFunction *MF = MBB.getParent();
208 MachineInstr &MI = *MBBI;
209 DebugLoc DL = MI.getDebugLoc();
210
211 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
212 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
213
214 MF->insert(++MBB.getIterator(), TrueBB);
215 MF->insert(++TrueBB->getIterator(), MergeBB);
216
217 // We want to copy the "true" value when the condition is true which means
218 // we need to invert the branch condition to jump over TrueBB when the
219 // condition is false.
220 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
221 CC = RISCVCC::getInverseBranchCondition(CC);
222
223 // Insert branch instruction.
224 BuildMI(MBB, MBBI, DL, TII->get(RISCVCC::getBrCond(CC)))
225 .addReg(MI.getOperand(1).getReg())
226 .addReg(MI.getOperand(2).getReg())
227 .addMBB(MergeBB);
228
229 Register DestReg = MI.getOperand(0).getReg();
230 assert(MI.getOperand(4).getReg() == DestReg);
231
232 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
233 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
234 // Add MV.
235 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
236 .add(MI.getOperand(5))
237 .addImm(0);
238 } else {
239 unsigned NewOpc;
240 // clang-format off
241 switch (MI.getOpcode()) {
242 default:
243 llvm_unreachable("Unexpected opcode!");
244 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
245 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
246 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
247 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
248 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
249 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
250 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
251 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
252 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
253 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
254 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
255 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
256 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
257 case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
258 case RISCV::PseudoCCQC_E_LB: NewOpc = RISCV::QC_E_LB; break;
259 case RISCV::PseudoCCQC_E_LH: NewOpc = RISCV::QC_E_LH; break;
260 case RISCV::PseudoCCQC_E_LW: NewOpc = RISCV::QC_E_LW; break;
261 case RISCV::PseudoCCQC_E_LHU: NewOpc = RISCV::QC_E_LHU; break;
262 case RISCV::PseudoCCQC_E_LBU: NewOpc = RISCV::QC_E_LBU; break;
263 case RISCV::PseudoCCLB: NewOpc = RISCV::LB; break;
264 case RISCV::PseudoCCLH: NewOpc = RISCV::LH; break;
265 case RISCV::PseudoCCLW: NewOpc = RISCV::LW; break;
266 case RISCV::PseudoCCLHU: NewOpc = RISCV::LHU; break;
267 case RISCV::PseudoCCLBU: NewOpc = RISCV::LBU; break;
268 case RISCV::PseudoCCLWU: NewOpc = RISCV::LWU; break;
269 case RISCV::PseudoCCLD: NewOpc = RISCV::LD; break;
270 case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
271 case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
272 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
273 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
274 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
275 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
276 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
277 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
278 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
279 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
280 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
281 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
282 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
283 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
284 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
285 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
286 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
287 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
288 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
289 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
290 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
291 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
292 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
293 }
294 // clang-format on
295
296 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
297 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
298 .add(MI.getOperand(5))
299 .add(MI.getOperand(6))
300 .add(MI.getOperand(7));
301 } else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
302 NewOpc == RISCV::QC_E_LI) {
303 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(5));
304 } else {
305 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
306 .add(MI.getOperand(5))
307 .add(MI.getOperand(6));
308 }
309 }
310
311 TrueBB->addSuccessor(MergeBB);
312
313 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
314 MergeBB->transferSuccessors(&MBB);
315
316 MBB.addSuccessor(TrueBB);
317 MBB.addSuccessor(MergeBB);
318
319 NextMBBI = MBB.end();
320 MI.eraseFromParent();
321
322 // Make sure live-ins are correctly attached to this new basic block.
323 LivePhysRegs LiveRegs;
324 computeAndAddLiveIns(LiveRegs, *TrueBB);
325 computeAndAddLiveIns(LiveRegs, *MergeBB);
326
327 return true;
328}
329
330bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
331 MachineBasicBlock::iterator MBBI) {
332 MachineInstr &MI = *MBBI;
333 DebugLoc DL = MI.getDebugLoc();
334
335 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
336 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
337 return false;
338
339 if (!STI->hasVendorXqcicm())
340 return false;
341
342 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
343 if (MI.getOperand(1).getReg() == RISCV::X0 ||
344 MI.getOperand(4).getReg() == RISCV::X0 ||
345 MI.getOperand(5).getReg() == RISCV::X0)
346 return false;
347
348 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
349
350 unsigned CMovOpcode, CMovIOpcode;
351 switch (CC) {
352 default:
353 llvm_unreachable("Unhandled CC");
354 case RISCVCC::COND_EQ:
355 CMovOpcode = RISCV::QC_MVEQ;
356 CMovIOpcode = RISCV::QC_MVEQI;
357 break;
358 case RISCVCC::COND_NE:
359 CMovOpcode = RISCV::QC_MVNE;
360 CMovIOpcode = RISCV::QC_MVNEI;
361 break;
362 case RISCVCC::COND_LT:
363 CMovOpcode = RISCV::QC_MVLT;
364 CMovIOpcode = RISCV::QC_MVLTI;
365 break;
366 case RISCVCC::COND_GE:
367 CMovOpcode = RISCV::QC_MVGE;
368 CMovIOpcode = RISCV::QC_MVGEI;
369 break;
370 case RISCVCC::COND_LTU:
371 CMovOpcode = RISCV::QC_MVLTU;
372 CMovIOpcode = RISCV::QC_MVLTUI;
373 break;
374 case RISCVCC::COND_GEU:
375 CMovOpcode = RISCV::QC_MVGEU;
376 CMovIOpcode = RISCV::QC_MVGEUI;
377 break;
378 }
379
380 if (MI.getOperand(2).getReg() == RISCV::X0) {
381 // $dst = PseudoCCMOVGPR $lhs, X0, $cc, $falsev (=$dst), $truev
382 // $dst = PseudoCCMOVGPRNoX0 $lhs, X0, $cc, $falsev (=$dst), $truev
383 // =>
384 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
385 BuildMI(MBB, MBBI, DL, TII->get(CMovIOpcode))
386 .addDef(MI.getOperand(0).getReg())
387 .addReg(MI.getOperand(4).getReg())
388 .addReg(MI.getOperand(1).getReg())
389 .addImm(0)
390 .addReg(MI.getOperand(5).getReg());
391
392 MI.eraseFromParent();
393 return true;
394 }
395
396 // $dst = PseudoCCMOVGPR $lhs, $rhs, $cc, $falsev (=$dst), $truev
397 // $dst = PseudoCCMOVGPRNoX0 $lhs, $rhs, $cc, $falsev (=$dst), $truev
398 // =>
399 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
400 BuildMI(MBB, MBBI, DL, TII->get(CMovOpcode))
401 .addDef(MI.getOperand(0).getReg())
402 .addReg(MI.getOperand(4).getReg())
403 .addReg(MI.getOperand(1).getReg())
404 .addReg(MI.getOperand(2).getReg())
405 .addReg(MI.getOperand(5).getReg());
406 MI.eraseFromParent();
407 return true;
408}
409
410bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
411 MachineBasicBlock::iterator MBBI,
412 unsigned Opcode) {
413 DebugLoc DL = MBBI->getDebugLoc();
414 Register DstReg = MBBI->getOperand(0).getReg();
415 const MCInstrDesc &Desc = TII->get(Opcode);
416 BuildMI(MBB, MBBI, DL, Desc, DstReg)
417 .addReg(DstReg, RegState::Undef)
418 .addReg(DstReg, RegState::Undef);
419 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
420 return true;
421}
422
423bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
424 MachineBasicBlock::iterator MBBI) {
425 DebugLoc DL = MBBI->getDebugLoc();
426 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
427 Register DstReg = TRI->getMatchingSuperReg(
428 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
429 Register SrcReg = TRI->getMatchingSuperReg(
430 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
431
432 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
433 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
434 .addImm(0);
435
436 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
437 return true;
438}
439
440bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
441 MachineBasicBlock::iterator MBBI) {
442 DebugLoc DL = MBBI->getDebugLoc();
443 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
444 Register DstReg = TRI->getMatchingSuperReg(
445 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
446 Register SrcReg = TRI->getMatchingSuperReg(
447 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
448
449 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
450 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
451 .addImm(0);
452
453 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
454 return true;
455}
456
457// This function expands the PseudoRV32ZdinxSD for storing a double-precision
458// floating-point value into memory by generating an equivalent instruction
459// sequence for RV32.
460bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MBBI) {
462 DebugLoc DL = MBBI->getDebugLoc();
463 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
464 Register Lo =
465 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
466 Register Hi =
467 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
468 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
469 Hi = RISCV::X0;
470
471 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
472 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
473 .addReg(MBBI->getOperand(1).getReg())
474 .add(MBBI->getOperand(2));
475
476 MachineInstrBuilder MIBHi;
477 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
478 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
479 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
480 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
481 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
482 .add(MBBI->getOperand(1))
483 .add(MBBI->getOperand(2));
484 } else {
485 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
486 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
487 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
488 .add(MBBI->getOperand(1))
489 .addImm(MBBI->getOperand(2).getImm() + 4);
490 }
491
492 MachineFunction *MF = MBB.getParent();
493 SmallVector<MachineMemOperand *> NewLoMMOs;
494 SmallVector<MachineMemOperand *> NewHiMMOs;
495 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
496 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
497 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
498 }
499 MIBLo.setMemRefs(NewLoMMOs);
500 MIBHi.setMemRefs(NewHiMMOs);
501
502 MBBI->eraseFromParent();
503 return true;
504}
505
506// This function expands PseudoRV32ZdinxLoad for loading a double-precision
507// floating-point value from memory into an equivalent instruction sequence for
508// RV32.
509bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
510 MachineBasicBlock::iterator MBBI) {
511 DebugLoc DL = MBBI->getDebugLoc();
512 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
513 Register Lo =
514 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
515 Register Hi =
516 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
517 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
518
519 MachineInstrBuilder MIBLo, MIBHi;
520
521 // If the register of operand 1 is equal to the Lo register, then swap the
522 // order of loading the Lo and Hi statements.
523 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
524 // Order: Lo, Hi
525 if (!IsOp1EqualToLo) {
526 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
527 .addReg(MBBI->getOperand(1).getReg())
528 .add(MBBI->getOperand(2));
529 }
530
531 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
532 auto Offset = MBBI->getOperand(2).getOffset();
533 assert(Offset % 8 == 0);
534 MBBI->getOperand(2).setOffset(Offset + 4);
535 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
536 .addReg(MBBI->getOperand(1).getReg())
537 .add(MBBI->getOperand(2));
538 MBBI->getOperand(2).setOffset(Offset);
539 } else {
540 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
541 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
542 .addReg(MBBI->getOperand(1).getReg())
543 .addImm(MBBI->getOperand(2).getImm() + 4);
544 }
545
546 // Order: Hi, Lo
547 if (IsOp1EqualToLo) {
548 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
549 .addReg(MBBI->getOperand(1).getReg())
550 .add(MBBI->getOperand(2));
551 }
552
553 MachineFunction *MF = MBB.getParent();
554 SmallVector<MachineMemOperand *> NewLoMMOs;
555 SmallVector<MachineMemOperand *> NewHiMMOs;
556 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
557 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
558 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
559 }
560 MIBLo.setMemRefs(NewLoMMOs);
561 MIBHi.setMemRefs(NewHiMMOs);
562
563 MBBI->eraseFromParent();
564 return true;
565}
566
567bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
568 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
569 DebugLoc DL = MBBI->getDebugLoc();
570 Register Dst = MBBI->getOperand(0).getReg();
571 unsigned Mul = MBBI->getOperand(1).getImm();
572 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
573 unsigned VTypeImm = RISCVVType::encodeVTYPE(
574 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
575
576 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
577 .addReg(Dst, RegState::Define)
578 .addReg(RISCV::X0, RegState::Kill)
579 .addImm(VTypeImm);
580
581 MBBI->eraseFromParent();
582 return true;
583}
584
585class RISCVPreRAExpandPseudo : public MachineFunctionPass {
586public:
587 const RISCVSubtarget *STI;
588 const RISCVInstrInfo *TII;
589 static char ID;
590
591 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
592
593 bool runOnMachineFunction(MachineFunction &MF) override;
594
595 void getAnalysisUsage(AnalysisUsage &AU) const override {
596 AU.setPreservesCFG();
597 MachineFunctionPass::getAnalysisUsage(AU);
598 }
599 StringRef getPassName() const override {
600 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
601 }
602
603private:
604 bool expandMBB(MachineBasicBlock &MBB);
605 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
606 MachineBasicBlock::iterator &NextMBBI);
607 bool expandAuipcInstPair(MachineBasicBlock &MBB,
608 MachineBasicBlock::iterator MBBI,
609 MachineBasicBlock::iterator &NextMBBI,
610 unsigned FlagsHi, unsigned SecondOpcode);
611 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
612 MachineBasicBlock::iterator MBBI,
613 MachineBasicBlock::iterator &NextMBBI);
614 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
615 MachineBasicBlock::iterator MBBI,
616 MachineBasicBlock::iterator &NextMBBI);
617 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
618 MachineBasicBlock::iterator MBBI,
619 MachineBasicBlock::iterator &NextMBBI);
620 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
621 MachineBasicBlock::iterator MBBI,
622 MachineBasicBlock::iterator &NextMBBI);
623 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
624 MachineBasicBlock::iterator MBBI,
625 MachineBasicBlock::iterator &NextMBBI);
626
627#ifndef NDEBUG
628 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
629 unsigned Size = 0;
630 for (auto &MBB : MF)
631 for (auto &MI : MBB)
632 Size += TII->getInstSizeInBytes(MI);
633 return Size;
634 }
635#endif
636};
637
638char RISCVPreRAExpandPseudo::ID = 0;
639
640bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
641 STI = &MF.getSubtarget<RISCVSubtarget>();
642 TII = STI->getInstrInfo();
643
644#ifndef NDEBUG
645 const unsigned OldSize = getInstSizeInBytes(MF);
646#endif
647
648 bool Modified = false;
649 for (auto &MBB : MF)
650 Modified |= expandMBB(MBB);
651
652#ifndef NDEBUG
653 const unsigned NewSize = getInstSizeInBytes(MF);
654 assert(OldSize >= NewSize);
655#endif
656 return Modified;
657}
658
659bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
660 bool Modified = false;
661
662 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
663 while (MBBI != E) {
664 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
665 Modified |= expandMI(MBB, MBBI, NMBBI);
666 MBBI = NMBBI;
667 }
668
669 return Modified;
670}
671
672bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
673 MachineBasicBlock::iterator MBBI,
674 MachineBasicBlock::iterator &NextMBBI) {
675
676 switch (MBBI->getOpcode()) {
677 case RISCV::PseudoLLA:
678 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
679 case RISCV::PseudoLGA:
680 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
681 case RISCV::PseudoLA_TLS_IE:
682 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
683 case RISCV::PseudoLA_TLS_GD:
684 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
685 case RISCV::PseudoLA_TLSDESC:
686 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
687 }
688 return false;
689}
690
691bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
692 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
693 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
694 unsigned SecondOpcode) {
695 MachineFunction *MF = MBB.getParent();
696 MachineInstr &MI = *MBBI;
697 DebugLoc DL = MI.getDebugLoc();
698
699 Register DestReg = MI.getOperand(0).getReg();
700 Register ScratchReg =
701 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
702
703 MachineOperand &Symbol = MI.getOperand(1);
704 Symbol.setTargetFlags(FlagsHi);
705 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
706
707 MachineInstr *MIAUIPC =
708 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
709 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
710
711 MachineInstr *SecondMI =
712 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
713 .addReg(ScratchReg)
714 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
715
716 if (MI.hasOneMemOperand())
717 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
718
719 MI.eraseFromParent();
720 return true;
721}
722
723bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
724 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
725 MachineBasicBlock::iterator &NextMBBI) {
726 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
727 RISCV::ADDI);
728}
729
730bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
731 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
732 MachineBasicBlock::iterator &NextMBBI) {
733 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
734 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
735 SecondOpcode);
736}
737
738bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
739 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
740 MachineBasicBlock::iterator &NextMBBI) {
741 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
742 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
743 SecondOpcode);
744}
745
746bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
747 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
748 MachineBasicBlock::iterator &NextMBBI) {
749 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
750 RISCV::ADDI);
751}
752
753bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
754 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
755 MachineBasicBlock::iterator &NextMBBI) {
756 MachineFunction *MF = MBB.getParent();
757 MachineInstr &MI = *MBBI;
758 DebugLoc DL = MI.getDebugLoc();
759
760 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
761 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
762
763 Register FinalReg = MI.getOperand(0).getReg();
764 Register DestReg =
765 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
766 Register ScratchReg =
767 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
768
769 MachineOperand &Symbol = MI.getOperand(1);
770 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
771 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
772
773 MachineInstr *MIAUIPC =
774 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
775 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
776
777 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
778 .addReg(ScratchReg)
779 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
780
781 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
782 .addReg(ScratchReg)
783 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
784
785 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
786 .addReg(DestReg)
787 .addImm(0)
788 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
789
790 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
791 .addReg(RISCV::X10)
792 .addReg(RISCV::X4);
793
794 MI.eraseFromParent();
795 return true;
796}
797
798} // end of anonymous namespace
799
800INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
801 RISCV_EXPAND_PSEUDO_NAME, false, false)
802
803INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
804 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
805
806namespace llvm {
807
808FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
809FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
810
811} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2118
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:26
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition SystemZLongBranch.cpp:211
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:270
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:123
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition MCContext.cpp:395
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:199
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:935
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:816
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1156
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:341
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:184
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:762
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:536
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition MachineFunction.h:719
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:772
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:499
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1003
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:252
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:175
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:268
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition MachineInstrBuilder.h:315
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:141
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:190
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:160
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:72
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition MachineInstr.cpp:480
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition MachineInstr.cpp:385
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:141
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:140
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:417
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1203
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:242
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition TargetPassConfig.cpp:388
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::RISCVCC::getInverseBranchCondition
CondCode getInverseBranchCondition(CondCode)
Definition RISCVInstrInfo.cpp:1258
llvm::RISCVCC::getBrCond
unsigned getBrCond(CondCode CC, unsigned SelectOpc=0)
Definition RISCVInstrInfo.cpp:1147
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:113
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:161
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:47
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:51
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:55
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Offset
@ Offset
Definition DWP.cpp:532
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:391
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:165
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:23
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1070
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition MachineInstrBuilder.h:565
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:808
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:809
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