26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
69char RISCVExpandPseudo::ID = 0;
73 TII = STI->getInstrInfo();
85 assert(OldSize >= NewSize);
109 switch (
MBBI->getOpcode()) {
110 case RISCV::PseudoRV32ZdinxSD:
111 return expandRV32ZdinxStore(
MBB,
MBBI);
112 case RISCV::PseudoRV32ZdinxLD:
113 return expandRV32ZdinxLoad(
MBB,
MBBI);
114 case RISCV::PseudoCCMOVGPR:
115 case RISCV::PseudoCCADD:
116 case RISCV::PseudoCCSUB:
117 case RISCV::PseudoCCAND:
118 case RISCV::PseudoCCOR:
119 case RISCV::PseudoCCXOR:
120 case RISCV::PseudoCCADDW:
121 case RISCV::PseudoCCSUBW:
122 case RISCV::PseudoCCSLL:
123 case RISCV::PseudoCCSRL:
124 case RISCV::PseudoCCSRA:
125 case RISCV::PseudoCCADDI:
126 case RISCV::PseudoCCSLLI:
127 case RISCV::PseudoCCSRLI:
128 case RISCV::PseudoCCSRAI:
129 case RISCV::PseudoCCANDI:
130 case RISCV::PseudoCCORI:
131 case RISCV::PseudoCCXORI:
132 case RISCV::PseudoCCSLLW:
133 case RISCV::PseudoCCSRLW:
134 case RISCV::PseudoCCSRAW:
135 case RISCV::PseudoCCADDIW:
136 case RISCV::PseudoCCSLLIW:
137 case RISCV::PseudoCCSRLIW:
138 case RISCV::PseudoCCSRAIW:
139 return expandCCOp(
MBB,
MBBI, NextMBBI);
140 case RISCV::PseudoVSETVLI:
141 case RISCV::PseudoVSETVLIX0:
142 case RISCV::PseudoVSETIVLI:
143 return expandVSetVL(
MBB,
MBBI);
144 case RISCV::PseudoVMCLR_M_B1:
145 case RISCV::PseudoVMCLR_M_B2:
146 case RISCV::PseudoVMCLR_M_B4:
147 case RISCV::PseudoVMCLR_M_B8:
148 case RISCV::PseudoVMCLR_M_B16:
149 case RISCV::PseudoVMCLR_M_B32:
150 case RISCV::PseudoVMCLR_M_B64:
152 return expandVMSET_VMCLR(
MBB,
MBBI, RISCV::VMXOR_MM);
153 case RISCV::PseudoVMSET_M_B1:
154 case RISCV::PseudoVMSET_M_B2:
155 case RISCV::PseudoVMSET_M_B4:
156 case RISCV::PseudoVMSET_M_B8:
157 case RISCV::PseudoVMSET_M_B16:
158 case RISCV::PseudoVMSET_M_B32:
159 case RISCV::PseudoVMSET_M_B64:
161 return expandVMSET_VMCLR(
MBB,
MBBI, RISCV::VMXNOR_MM);
194 assert(
MI.getOperand(4).getReg() == DestReg);
196 if (
MI.getOpcode() == RISCV::PseudoCCMOVGPR) {
199 .
add(
MI.getOperand(5))
203 switch (
MI.getOpcode()) {
206 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD;
break;
207 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB;
break;
208 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL;
break;
209 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL;
break;
210 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA;
break;
211 case RISCV::PseudoCCAND: NewOpc = RISCV::AND;
break;
212 case RISCV::PseudoCCOR: NewOpc = RISCV::OR;
break;
213 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR;
break;
214 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI;
break;
215 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI;
break;
216 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI;
break;
217 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI;
break;
218 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI;
break;
219 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI;
break;
220 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI;
break;
221 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW;
break;
222 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW;
break;
223 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW;
break;
224 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW;
break;
225 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW;
break;
226 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW;
break;
227 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW;
break;
228 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW;
break;
229 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW;
break;
232 .
add(
MI.getOperand(5))
233 .
add(
MI.getOperand(6));
245 MI.eraseFromParent();
257 assert(
MBBI->getNumExplicitOperands() == 3 &&
MBBI->getNumOperands() >= 5 &&
258 "Unexpected instruction format");
262 assert((
MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
263 MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
264 MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&
265 "Unexpected pseudo instruction");
267 if (
MBBI->getOpcode() == RISCV::PseudoVSETIVLI)
268 Opcode = RISCV::VSETIVLI;
270 Opcode = RISCV::VSETVLI;
272 assert(
Desc.getNumOperands() == 3 &&
"Unexpected instruction format");
275 bool DstIsDead =
MBBI->getOperand(0).isDead();
311 if (
MBBI->getOperand(2).isGlobal() ||
MBBI->getOperand(2).isCPI()) {
313 assert(!STI->enableUnalignedScalarMem());
315 assert(
MBBI->getOperand(2).getOffset() % 8 == 0);
316 MBBI->getOperand(2).setOffset(
MBBI->getOperand(2).getOffset() + 4);
322 assert(isInt<12>(
MBBI->getOperand(2).getImm() + 4));
344 bool IsOp1EqualToLo =
Lo ==
MBBI->getOperand(1).getReg();
346 if (!IsOp1EqualToLo) {
352 if (
MBBI->getOperand(2).isGlobal() ||
MBBI->getOperand(2).isCPI()) {
353 auto Offset =
MBBI->getOperand(2).getOffset();
354 assert(
MBBI->getOperand(2).getOffset() % 8 == 0);
361 assert(isInt<12>(
MBBI->getOperand(2).getImm() + 4));
368 if (IsOp1EqualToLo) {
405 unsigned FlagsHi,
unsigned SecondOpcode);
429char RISCVPreRAExpandPseudo::ID = 0;
431bool RISCVPreRAExpandPseudo::runOnMachineFunction(
MachineFunction &MF) {
433 TII = STI->getInstrInfo();
445 assert(OldSize >= NewSize);
467 switch (
MBBI->getOpcode()) {
468 case RISCV::PseudoLLA:
469 return expandLoadLocalAddress(
MBB,
MBBI, NextMBBI);
470 case RISCV::PseudoLGA:
471 return expandLoadGlobalAddress(
MBB,
MBBI, NextMBBI);
472 case RISCV::PseudoLA_TLS_IE:
473 return expandLoadTLSIEAddress(
MBB,
MBBI, NextMBBI);
474 case RISCV::PseudoLA_TLS_GD:
475 return expandLoadTLSGDAddress(
MBB,
MBBI, NextMBBI);
480bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
483 unsigned SecondOpcode) {
493 Symbol.setTargetFlags(FlagsHi);
505 if (
MI.hasOneMemOperand())
508 MI.eraseFromParent();
512bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
519bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
522 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
527bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
530 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
535bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static Expected< BitVector > expand(StringRef S, StringRef Original)
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
riscv prera expand pseudo
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Describe properties that are true of each instruction in the target description file.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
MachineOperand class - Representation of each machine instruction operand.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
CondCode getOppositeBranchCondition(CondCode)
@ Define
Register definition.
@ Undef
Value of the register doesn't matter.
This is an optimization pass for GlobalISel generic memory operations.
void initializeRISCVExpandPseudoPass(PassRegistry &)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getDeadRegState(bool B)
unsigned getKillRegState(bool B)
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
Description of the encoding of one expression Op.