LLVM  14.0.0git
MachineVerifier.cpp
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1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled with the command-line option
20 // -verify-machineinstrs.
21 //===----------------------------------------------------------------------===//
22 
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/StringRef.h"
33 #include "llvm/ADT/Twine.h"
52 #include "llvm/CodeGen/StackMaps.h"
57 #include "llvm/IR/BasicBlock.h"
58 #include "llvm/IR/Function.h"
59 #include "llvm/IR/InlineAsm.h"
60 #include "llvm/IR/Instructions.h"
61 #include "llvm/InitializePasses.h"
62 #include "llvm/MC/LaneBitmask.h"
63 #include "llvm/MC/MCAsmInfo.h"
64 #include "llvm/MC/MCInstrDesc.h"
65 #include "llvm/MC/MCRegisterInfo.h"
67 #include "llvm/Pass.h"
68 #include "llvm/Support/Casting.h"
74 #include <algorithm>
75 #include <cassert>
76 #include <cstddef>
77 #include <cstdint>
78 #include <iterator>
79 #include <string>
80 #include <utility>
81 
82 using namespace llvm;
83 
84 namespace {
85 
86  struct MachineVerifier {
87  MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
88 
89  unsigned verify(const MachineFunction &MF);
90 
91  Pass *const PASS;
92  const char *Banner;
93  const MachineFunction *MF;
94  const TargetMachine *TM;
95  const TargetInstrInfo *TII;
96  const TargetRegisterInfo *TRI;
97  const MachineRegisterInfo *MRI;
98 
99  unsigned foundErrors;
100 
101  // Avoid querying the MachineFunctionProperties for each operand.
102  bool isFunctionRegBankSelected;
103  bool isFunctionSelected;
104 
105  using RegVector = SmallVector<Register, 16>;
106  using RegMaskVector = SmallVector<const uint32_t *, 4>;
107  using RegSet = DenseSet<Register>;
110 
111  const MachineInstr *FirstNonPHI;
112  const MachineInstr *FirstTerminator;
113  BlockSet FunctionBlocks;
114 
115  BitVector regsReserved;
116  RegSet regsLive;
117  RegVector regsDefined, regsDead, regsKilled;
118  RegMaskVector regMasks;
119 
120  SlotIndex lastIndex;
121 
122  // Add Reg and any sub-registers to RV
123  void addRegWithSubRegs(RegVector &RV, Register Reg) {
124  RV.push_back(Reg);
125  if (Reg.isPhysical())
126  append_range(RV, TRI->subregs(Reg.asMCReg()));
127  }
128 
129  struct BBInfo {
130  // Is this MBB reachable from the MF entry point?
131  bool reachable = false;
132 
133  // Vregs that must be live in because they are used without being
134  // defined. Map value is the user. vregsLiveIn doesn't include regs
135  // that only are used by PHI nodes.
136  RegMap vregsLiveIn;
137 
138  // Regs killed in MBB. They may be defined again, and will then be in both
139  // regsKilled and regsLiveOut.
140  RegSet regsKilled;
141 
142  // Regs defined in MBB and live out. Note that vregs passing through may
143  // be live out without being mentioned here.
144  RegSet regsLiveOut;
145 
146  // Vregs that pass through MBB untouched. This set is disjoint from
147  // regsKilled and regsLiveOut.
148  RegSet vregsPassed;
149 
150  // Vregs that must pass through MBB because they are needed by a successor
151  // block. This set is disjoint from regsLiveOut.
152  RegSet vregsRequired;
153 
154  // Set versions of block's predecessor and successor lists.
155  BlockSet Preds, Succs;
156 
157  BBInfo() = default;
158 
159  // Add register to vregsRequired if it belongs there. Return true if
160  // anything changed.
161  bool addRequired(Register Reg) {
162  if (!Reg.isVirtual())
163  return false;
164  if (regsLiveOut.count(Reg))
165  return false;
166  return vregsRequired.insert(Reg).second;
167  }
168 
169  // Same for a full set.
170  bool addRequired(const RegSet &RS) {
171  bool Changed = false;
172  for (Register Reg : RS)
173  Changed |= addRequired(Reg);
174  return Changed;
175  }
176 
177  // Same for a full map.
178  bool addRequired(const RegMap &RM) {
179  bool Changed = false;
180  for (const auto &I : RM)
181  Changed |= addRequired(I.first);
182  return Changed;
183  }
184 
185  // Live-out registers are either in regsLiveOut or vregsPassed.
186  bool isLiveOut(Register Reg) const {
187  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
188  }
189  };
190 
191  // Extra register info per MBB.
193 
194  bool isReserved(Register Reg) {
195  return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
196  }
197 
198  bool isAllocatable(Register Reg) const {
199  return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
200  !regsReserved.test(Reg.id());
201  }
202 
203  // Analysis information if available
204  LiveVariables *LiveVars;
205  LiveIntervals *LiveInts;
206  LiveStacks *LiveStks;
207  SlotIndexes *Indexes;
208 
209  void visitMachineFunctionBefore();
210  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
211  void visitMachineBundleBefore(const MachineInstr *MI);
212 
213  bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
214  void verifyPreISelGenericInstruction(const MachineInstr *MI);
215  void visitMachineInstrBefore(const MachineInstr *MI);
216  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
217  void visitMachineBundleAfter(const MachineInstr *MI);
218  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
219  void visitMachineFunctionAfter();
220 
221  void report(const char *msg, const MachineFunction *MF);
222  void report(const char *msg, const MachineBasicBlock *MBB);
223  void report(const char *msg, const MachineInstr *MI);
224  void report(const char *msg, const MachineOperand *MO, unsigned MONum,
225  LLT MOVRegType = LLT{});
226  void report(const Twine &Msg, const MachineInstr *MI);
227 
228  void report_context(const LiveInterval &LI) const;
229  void report_context(const LiveRange &LR, Register VRegUnit,
230  LaneBitmask LaneMask) const;
231  void report_context(const LiveRange::Segment &S) const;
232  void report_context(const VNInfo &VNI) const;
233  void report_context(SlotIndex Pos) const;
234  void report_context(MCPhysReg PhysReg) const;
235  void report_context_liverange(const LiveRange &LR) const;
236  void report_context_lanemask(LaneBitmask LaneMask) const;
237  void report_context_vreg(Register VReg) const;
238  void report_context_vreg_regunit(Register VRegOrUnit) const;
239 
240  void verifyInlineAsm(const MachineInstr *MI);
241 
242  void checkLiveness(const MachineOperand *MO, unsigned MONum);
243  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
244  SlotIndex UseIdx, const LiveRange &LR,
245  Register VRegOrUnit,
246  LaneBitmask LaneMask = LaneBitmask::getNone());
247  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
248  SlotIndex DefIdx, const LiveRange &LR,
249  Register VRegOrUnit, bool SubRangeCheck = false,
250  LaneBitmask LaneMask = LaneBitmask::getNone());
251 
252  void markReachable(const MachineBasicBlock *MBB);
253  void calcRegsPassed();
254  void checkPHIOps(const MachineBasicBlock &MBB);
255 
256  void calcRegsRequired();
257  void verifyLiveVariables();
258  void verifyLiveIntervals();
259  void verifyLiveInterval(const LiveInterval&);
260  void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
261  LaneBitmask);
262  void verifyLiveRangeSegment(const LiveRange &,
264  LaneBitmask);
265  void verifyLiveRange(const LiveRange &, Register,
266  LaneBitmask LaneMask = LaneBitmask::getNone());
267 
268  void verifyStackFrame();
269 
270  void verifySlotIndexes() const;
271  void verifyProperties(const MachineFunction &MF);
272  };
273 
274  struct MachineVerifierPass : public MachineFunctionPass {
275  static char ID; // Pass ID, replacement for typeid
276 
277  const std::string Banner;
278 
279  MachineVerifierPass(std::string banner = std::string())
280  : MachineFunctionPass(ID), Banner(std::move(banner)) {
282  }
283 
284  void getAnalysisUsage(AnalysisUsage &AU) const override {
285  AU.setPreservesAll();
287  }
288 
289  bool runOnMachineFunction(MachineFunction &MF) override {
290  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
291  if (FoundErrors)
292  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
293  return false;
294  }
295  };
296 
297 } // end anonymous namespace
298 
299 char MachineVerifierPass::ID = 0;
300 
301 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
302  "Verify generated machine code", false, false)
303 
305  return new MachineVerifierPass(Banner);
306 }
307 
309  const std::string &Banner,
310  const MachineFunction &MF) {
311  // TODO: Use MFAM after porting below analyses.
312  // LiveVariables *LiveVars;
313  // LiveIntervals *LiveInts;
314  // LiveStacks *LiveStks;
315  // SlotIndexes *Indexes;
316  unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
317  if (FoundErrors)
318  report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
319 }
320 
321 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
322  const {
323  MachineFunction &MF = const_cast<MachineFunction&>(*this);
324  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
325  if (AbortOnErrors && FoundErrors)
326  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
327  return FoundErrors == 0;
328 }
329 
330 void MachineVerifier::verifySlotIndexes() const {
331  if (Indexes == nullptr)
332  return;
333 
334  // Ensure the IdxMBB list is sorted by slot indexes.
335  SlotIndex Last;
337  E = Indexes->MBBIndexEnd(); I != E; ++I) {
338  assert(!Last.isValid() || I->first > Last);
339  Last = I->first;
340  }
341 }
342 
343 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
344  // If a pass has introduced virtual registers without clearing the
345  // NoVRegs property (or set it without allocating the vregs)
346  // then report an error.
347  if (MF.getProperties().hasProperty(
349  MRI->getNumVirtRegs())
350  report("Function has NoVRegs property but there are VReg operands", &MF);
351 }
352 
353 unsigned MachineVerifier::verify(const MachineFunction &MF) {
354  foundErrors = 0;
355 
356  this->MF = &MF;
357  TM = &MF.getTarget();
358  TII = MF.getSubtarget().getInstrInfo();
360  MRI = &MF.getRegInfo();
361 
362  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
364 
365  // If we're mid-GlobalISel and we already triggered the fallback path then
366  // it's expected that the MIR is somewhat broken but that's ok since we'll
367  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
368  if (isFunctionFailedISel)
369  return foundErrors;
370 
371  isFunctionRegBankSelected = MF.getProperties().hasProperty(
373  isFunctionSelected = MF.getProperties().hasProperty(
375 
376  LiveVars = nullptr;
377  LiveInts = nullptr;
378  LiveStks = nullptr;
379  Indexes = nullptr;
380  if (PASS) {
381  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
382  // We don't want to verify LiveVariables if LiveIntervals is available.
383  if (!LiveInts)
384  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
385  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
386  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
387  }
388 
389  verifySlotIndexes();
390 
391  verifyProperties(MF);
392 
393  visitMachineFunctionBefore();
394  for (const MachineBasicBlock &MBB : MF) {
395  visitMachineBasicBlockBefore(&MBB);
396  // Keep track of the current bundle header.
397  const MachineInstr *CurBundle = nullptr;
398  // Do we expect the next instruction to be part of the same bundle?
399  bool InBundle = false;
400 
401  for (const MachineInstr &MI : MBB.instrs()) {
402  if (MI.getParent() != &MBB) {
403  report("Bad instruction parent pointer", &MBB);
404  errs() << "Instruction: " << MI;
405  continue;
406  }
407 
408  // Check for consistent bundle flags.
409  if (InBundle && !MI.isBundledWithPred())
410  report("Missing BundledPred flag, "
411  "BundledSucc was set on predecessor",
412  &MI);
413  if (!InBundle && MI.isBundledWithPred())
414  report("BundledPred flag is set, "
415  "but BundledSucc not set on predecessor",
416  &MI);
417 
418  // Is this a bundle header?
419  if (!MI.isInsideBundle()) {
420  if (CurBundle)
421  visitMachineBundleAfter(CurBundle);
422  CurBundle = &MI;
423  visitMachineBundleBefore(CurBundle);
424  } else if (!CurBundle)
425  report("No bundle header", &MI);
426  visitMachineInstrBefore(&MI);
427  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
428  const MachineOperand &Op = MI.getOperand(I);
429  if (Op.getParent() != &MI) {
430  // Make sure to use correct addOperand / RemoveOperand / ChangeTo
431  // functions when replacing operands of a MachineInstr.
432  report("Instruction has operand with wrong parent set", &MI);
433  }
434 
435  visitMachineOperand(&Op, I);
436  }
437 
438  // Was this the last bundled instruction?
439  InBundle = MI.isBundledWithSucc();
440  }
441  if (CurBundle)
442  visitMachineBundleAfter(CurBundle);
443  if (InBundle)
444  report("BundledSucc flag set on last instruction in block", &MBB.back());
445  visitMachineBasicBlockAfter(&MBB);
446  }
447  visitMachineFunctionAfter();
448 
449  // Clean up.
450  regsLive.clear();
451  regsDefined.clear();
452  regsDead.clear();
453  regsKilled.clear();
454  regMasks.clear();
455  MBBInfoMap.clear();
456 
457  return foundErrors;
458 }
459 
460 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
461  assert(MF);
462  errs() << '\n';
463  if (!foundErrors++) {
464  if (Banner)
465  errs() << "# " << Banner << '\n';
466  if (LiveInts != nullptr)
467  LiveInts->print(errs());
468  else
469  MF->print(errs(), Indexes);
470  }
471  errs() << "*** Bad machine code: " << msg << " ***\n"
472  << "- function: " << MF->getName() << "\n";
473 }
474 
475 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
476  assert(MBB);
477  report(msg, MBB->getParent());
478  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
479  << MBB->getName() << " (" << (const void *)MBB << ')';
480  if (Indexes)
481  errs() << " [" << Indexes->getMBBStartIdx(MBB)
482  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
483  errs() << '\n';
484 }
485 
486 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
487  assert(MI);
488  report(msg, MI->getParent());
489  errs() << "- instruction: ";
490  if (Indexes && Indexes->hasIndex(*MI))
491  errs() << Indexes->getInstructionIndex(*MI) << '\t';
492  MI->print(errs(), /*IsStandalone=*/true);
493 }
494 
495 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
496  unsigned MONum, LLT MOVRegType) {
497  assert(MO);
498  report(msg, MO->getParent());
499  errs() << "- operand " << MONum << ": ";
500  MO->print(errs(), MOVRegType, TRI);
501  errs() << "\n";
502 }
503 
504 void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
505  report(Msg.str().c_str(), MI);
506 }
507 
508 void MachineVerifier::report_context(SlotIndex Pos) const {
509  errs() << "- at: " << Pos << '\n';
510 }
511 
512 void MachineVerifier::report_context(const LiveInterval &LI) const {
513  errs() << "- interval: " << LI << '\n';
514 }
515 
516 void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
517  LaneBitmask LaneMask) const {
518  report_context_liverange(LR);
519  report_context_vreg_regunit(VRegUnit);
520  if (LaneMask.any())
521  report_context_lanemask(LaneMask);
522 }
523 
524 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
525  errs() << "- segment: " << S << '\n';
526 }
527 
528 void MachineVerifier::report_context(const VNInfo &VNI) const {
529  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
530 }
531 
532 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
533  errs() << "- liverange: " << LR << '\n';
534 }
535 
536 void MachineVerifier::report_context(MCPhysReg PReg) const {
537  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
538 }
539 
540 void MachineVerifier::report_context_vreg(Register VReg) const {
541  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
542 }
543 
544 void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
545  if (Register::isVirtualRegister(VRegOrUnit)) {
546  report_context_vreg(VRegOrUnit);
547  } else {
548  errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
549  }
550 }
551 
552 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
553  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
554 }
555 
556 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
557  BBInfo &MInfo = MBBInfoMap[MBB];
558  if (!MInfo.reachable) {
559  MInfo.reachable = true;
560  for (const MachineBasicBlock *Succ : MBB->successors())
561  markReachable(Succ);
562  }
563 }
564 
565 void MachineVerifier::visitMachineFunctionBefore() {
566  lastIndex = SlotIndex();
567  regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
568  : TRI->getReservedRegs(*MF);
569 
570  if (!MF->empty())
571  markReachable(&MF->front());
572 
573  // Build a set of the basic blocks in the function.
574  FunctionBlocks.clear();
575  for (const auto &MBB : *MF) {
576  FunctionBlocks.insert(&MBB);
577  BBInfo &MInfo = MBBInfoMap[&MBB];
578 
579  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
580  if (MInfo.Preds.size() != MBB.pred_size())
581  report("MBB has duplicate entries in its predecessor list.", &MBB);
582 
583  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
584  if (MInfo.Succs.size() != MBB.succ_size())
585  report("MBB has duplicate entries in its successor list.", &MBB);
586  }
587 
588  // Check that the register use lists are sane.
589  MRI->verifyUseLists();
590 
591  if (!MF->empty())
592  verifyStackFrame();
593 }
594 
595 void
596 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
597  FirstTerminator = nullptr;
598  FirstNonPHI = nullptr;
599 
600  if (!MF->getProperties().hasProperty(
602  // If this block has allocatable physical registers live-in, check that
603  // it is an entry block or landing pad.
604  for (const auto &LI : MBB->liveins()) {
605  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
606  MBB->getIterator() != MBB->getParent()->begin()) {
607  report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
608  report_context(LI.PhysReg);
609  }
610  }
611  }
612 
613  // Count the number of landing pad successors.
615  for (const auto *succ : MBB->successors()) {
616  if (succ->isEHPad())
617  LandingPadSuccs.insert(succ);
618  if (!FunctionBlocks.count(succ))
619  report("MBB has successor that isn't part of the function.", MBB);
620  if (!MBBInfoMap[succ].Preds.count(MBB)) {
621  report("Inconsistent CFG", MBB);
622  errs() << "MBB is not in the predecessor list of the successor "
623  << printMBBReference(*succ) << ".\n";
624  }
625  }
626 
627  // Check the predecessor list.
628  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
629  if (!FunctionBlocks.count(Pred))
630  report("MBB has predecessor that isn't part of the function.", MBB);
631  if (!MBBInfoMap[Pred].Succs.count(MBB)) {
632  report("Inconsistent CFG", MBB);
633  errs() << "MBB is not in the successor list of the predecessor "
634  << printMBBReference(*Pred) << ".\n";
635  }
636  }
637 
638  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
639  const BasicBlock *BB = MBB->getBasicBlock();
640  const Function &F = MF->getFunction();
641  if (LandingPadSuccs.size() > 1 &&
642  !(AsmInfo &&
644  BB && isa<SwitchInst>(BB->getTerminator())) &&
645  !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
646  report("MBB has more than one landing pad successor", MBB);
647 
648  // Call analyzeBranch. If it succeeds, there several more conditions to check.
649  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
651  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
652  Cond)) {
653  // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
654  // check whether its answers match up with reality.
655  if (!TBB && !FBB) {
656  // Block falls through to its successor.
657  if (!MBB->empty() && MBB->back().isBarrier() &&
658  !TII->isPredicated(MBB->back())) {
659  report("MBB exits via unconditional fall-through but ends with a "
660  "barrier instruction!", MBB);
661  }
662  if (!Cond.empty()) {
663  report("MBB exits via unconditional fall-through but has a condition!",
664  MBB);
665  }
666  } else if (TBB && !FBB && Cond.empty()) {
667  // Block unconditionally branches somewhere.
668  if (MBB->empty()) {
669  report("MBB exits via unconditional branch but doesn't contain "
670  "any instructions!", MBB);
671  } else if (!MBB->back().isBarrier()) {
672  report("MBB exits via unconditional branch but doesn't end with a "
673  "barrier instruction!", MBB);
674  } else if (!MBB->back().isTerminator()) {
675  report("MBB exits via unconditional branch but the branch isn't a "
676  "terminator instruction!", MBB);
677  }
678  } else if (TBB && !FBB && !Cond.empty()) {
679  // Block conditionally branches somewhere, otherwise falls through.
680  if (MBB->empty()) {
681  report("MBB exits via conditional branch/fall-through but doesn't "
682  "contain any instructions!", MBB);
683  } else if (MBB->back().isBarrier()) {
684  report("MBB exits via conditional branch/fall-through but ends with a "
685  "barrier instruction!", MBB);
686  } else if (!MBB->back().isTerminator()) {
687  report("MBB exits via conditional branch/fall-through but the branch "
688  "isn't a terminator instruction!", MBB);
689  }
690  } else if (TBB && FBB) {
691  // Block conditionally branches somewhere, otherwise branches
692  // somewhere else.
693  if (MBB->empty()) {
694  report("MBB exits via conditional branch/branch but doesn't "
695  "contain any instructions!", MBB);
696  } else if (!MBB->back().isBarrier()) {
697  report("MBB exits via conditional branch/branch but doesn't end with a "
698  "barrier instruction!", MBB);
699  } else if (!MBB->back().isTerminator()) {
700  report("MBB exits via conditional branch/branch but the branch "
701  "isn't a terminator instruction!", MBB);
702  }
703  if (Cond.empty()) {
704  report("MBB exits via conditional branch/branch but there's no "
705  "condition!", MBB);
706  }
707  } else {
708  report("analyzeBranch returned invalid data!", MBB);
709  }
710 
711  // Now check that the successors match up with the answers reported by
712  // analyzeBranch.
713  if (TBB && !MBB->isSuccessor(TBB))
714  report("MBB exits via jump or conditional branch, but its target isn't a "
715  "CFG successor!",
716  MBB);
717  if (FBB && !MBB->isSuccessor(FBB))
718  report("MBB exits via conditional branch, but its target isn't a CFG "
719  "successor!",
720  MBB);
721 
722  // There might be a fallthrough to the next block if there's either no
723  // unconditional true branch, or if there's a condition, and one of the
724  // branches is missing.
725  bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
726 
727  // A conditional fallthrough must be an actual CFG successor, not
728  // unreachable. (Conversely, an unconditional fallthrough might not really
729  // be a successor, because the block might end in unreachable.)
730  if (!Cond.empty() && !FBB) {
732  if (MBBI == MF->end()) {
733  report("MBB conditionally falls through out of function!", MBB);
734  } else if (!MBB->isSuccessor(&*MBBI))
735  report("MBB exits via conditional branch/fall-through but the CFG "
736  "successors don't match the actual successors!",
737  MBB);
738  }
739 
740  // Verify that there aren't any extra un-accounted-for successors.
741  for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
742  // If this successor is one of the branch targets, it's okay.
743  if (SuccMBB == TBB || SuccMBB == FBB)
744  continue;
745  // If we might have a fallthrough, and the successor is the fallthrough
746  // block, that's also ok.
747  if (Fallthrough && SuccMBB == MBB->getNextNode())
748  continue;
749  // Also accept successors which are for exception-handling or might be
750  // inlineasm_br targets.
751  if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
752  continue;
753  report("MBB has unexpected successors which are not branch targets, "
754  "fallthrough, EHPads, or inlineasm_br targets.",
755  MBB);
756  }
757  }
758 
759  regsLive.clear();
760  if (MRI->tracksLiveness()) {
761  for (const auto &LI : MBB->liveins()) {
762  if (!Register::isPhysicalRegister(LI.PhysReg)) {
763  report("MBB live-in list contains non-physical register", MBB);
764  continue;
765  }
766  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
767  regsLive.insert(SubReg);
768  }
769  }
770 
771  const MachineFrameInfo &MFI = MF->getFrameInfo();
772  BitVector PR = MFI.getPristineRegs(*MF);
773  for (unsigned I : PR.set_bits()) {
774  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
775  regsLive.insert(SubReg);
776  }
777 
778  regsKilled.clear();
779  regsDefined.clear();
780 
781  if (Indexes)
782  lastIndex = Indexes->getMBBStartIdx(MBB);
783 }
784 
785 // This function gets called for all bundle headers, including normal
786 // stand-alone unbundled instructions.
787 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
788  if (Indexes && Indexes->hasIndex(*MI)) {
789  SlotIndex idx = Indexes->getInstructionIndex(*MI);
790  if (!(idx > lastIndex)) {
791  report("Instruction index out of order", MI);
792  errs() << "Last instruction was at " << lastIndex << '\n';
793  }
794  lastIndex = idx;
795  }
796 
797  // Ensure non-terminators don't follow terminators.
798  if (MI->isTerminator()) {
799  if (!FirstTerminator)
800  FirstTerminator = MI;
801  } else if (FirstTerminator) {
802  report("Non-terminator instruction after the first terminator", MI);
803  errs() << "First terminator was:\t" << *FirstTerminator;
804  }
805 }
806 
807 // The operands on an INLINEASM instruction must follow a template.
808 // Verify that the flag operands make sense.
809 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
810  // The first two operands on INLINEASM are the asm string and global flags.
811  if (MI->getNumOperands() < 2) {
812  report("Too few operands on inline asm", MI);
813  return;
814  }
815  if (!MI->getOperand(0).isSymbol())
816  report("Asm string must be an external symbol", MI);
817  if (!MI->getOperand(1).isImm())
818  report("Asm flags must be an immediate", MI);
819  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
820  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
821  // and Extra_IsConvergent = 32.
822  if (!isUInt<6>(MI->getOperand(1).getImm()))
823  report("Unknown asm flags", &MI->getOperand(1), 1);
824 
825  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
826 
827  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
828  unsigned NumOps;
829  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
830  const MachineOperand &MO = MI->getOperand(OpNo);
831  // There may be implicit ops after the fixed operands.
832  if (!MO.isImm())
833  break;
834  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
835  }
836 
837  if (OpNo > MI->getNumOperands())
838  report("Missing operands in last group", MI);
839 
840  // An optional MDNode follows the groups.
841  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
842  ++OpNo;
843 
844  // All trailing operands must be implicit registers.
845  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
846  const MachineOperand &MO = MI->getOperand(OpNo);
847  if (!MO.isReg() || !MO.isImplicit())
848  report("Expected implicit register after groups", &MO, OpNo);
849  }
850 }
851 
852 /// Check that types are consistent when two operands need to have the same
853 /// number of vector elements.
854 /// \return true if the types are valid.
855 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
856  const MachineInstr *MI) {
857  if (Ty0.isVector() != Ty1.isVector()) {
858  report("operand types must be all-vector or all-scalar", MI);
859  // Generally we try to report as many issues as possible at once, but in
860  // this case it's not clear what should we be comparing the size of the
861  // scalar with: the size of the whole vector or its lane. Instead of
862  // making an arbitrary choice and emitting not so helpful message, let's
863  // avoid the extra noise and stop here.
864  return false;
865  }
866 
867  if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
868  report("operand types must preserve number of vector elements", MI);
869  return false;
870  }
871 
872  return true;
873 }
874 
875 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
876  if (isFunctionSelected)
877  report("Unexpected generic instruction in a Selected function", MI);
878 
879  const MCInstrDesc &MCID = MI->getDesc();
880  unsigned NumOps = MI->getNumOperands();
881 
882  // Branches must reference a basic block if they are not indirect
883  if (MI->isBranch() && !MI->isIndirectBranch()) {
884  bool HasMBB = false;
885  for (const MachineOperand &Op : MI->operands()) {
886  if (Op.isMBB()) {
887  HasMBB = true;
888  break;
889  }
890  }
891 
892  if (!HasMBB) {
893  report("Branch instruction is missing a basic block operand or "
894  "isIndirectBranch property",
895  MI);
896  }
897  }
898 
899  // Check types.
900  SmallVector<LLT, 4> Types;
901  for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
902  I != E; ++I) {
903  if (!MCID.OpInfo[I].isGenericType())
904  continue;
905  // Generic instructions specify type equality constraints between some of
906  // their operands. Make sure these are consistent.
907  size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
908  Types.resize(std::max(TypeIdx + 1, Types.size()));
909 
910  const MachineOperand *MO = &MI->getOperand(I);
911  if (!MO->isReg()) {
912  report("generic instruction must use register operands", MI);
913  continue;
914  }
915 
916  LLT OpTy = MRI->getType(MO->getReg());
917  // Don't report a type mismatch if there is no actual mismatch, only a
918  // type missing, to reduce noise:
919  if (OpTy.isValid()) {
920  // Only the first valid type for a type index will be printed: don't
921  // overwrite it later so it's always clear which type was expected:
922  if (!Types[TypeIdx].isValid())
923  Types[TypeIdx] = OpTy;
924  else if (Types[TypeIdx] != OpTy)
925  report("Type mismatch in generic instruction", MO, I, OpTy);
926  } else {
927  // Generic instructions must have types attached to their operands.
928  report("Generic instruction is missing a virtual register type", MO, I);
929  }
930  }
931 
932  // Generic opcodes must not have physical register operands.
933  for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
934  const MachineOperand *MO = &MI->getOperand(I);
935  if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
936  report("Generic instruction cannot have physical register", MO, I);
937  }
938 
939  // Avoid out of bounds in checks below. This was already reported earlier.
940  if (MI->getNumOperands() < MCID.getNumOperands())
941  return;
942 
944  if (!TII->verifyInstruction(*MI, ErrorInfo))
945  report(ErrorInfo.data(), MI);
946 
947  // Verify properties of various specific instruction types
948  unsigned Opc = MI->getOpcode();
949  switch (Opc) {
950  case TargetOpcode::G_ASSERT_SEXT:
951  case TargetOpcode::G_ASSERT_ZEXT: {
952  std::string OpcName =
953  Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
954  if (!MI->getOperand(2).isImm()) {
955  report(Twine(OpcName, " expects an immediate operand #2"), MI);
956  break;
957  }
958 
959  Register Dst = MI->getOperand(0).getReg();
960  Register Src = MI->getOperand(1).getReg();
961  LLT SrcTy = MRI->getType(Src);
962  int64_t Imm = MI->getOperand(2).getImm();
963  if (Imm <= 0) {
964  report(Twine(OpcName, " size must be >= 1"), MI);
965  break;
966  }
967 
968  if (Imm >= SrcTy.getScalarSizeInBits()) {
969  report(Twine(OpcName, " size must be less than source bit width"), MI);
970  break;
971  }
972 
973  if (MRI->getRegBankOrNull(Src) != MRI->getRegBankOrNull(Dst)) {
974  report(
975  Twine(OpcName, " source and destination register banks must match"),
976  MI);
977  break;
978  }
979 
980  if (MRI->getRegClassOrNull(Src) != MRI->getRegClassOrNull(Dst))
981  report(
982  Twine(OpcName, " source and destination register classes must match"),
983  MI);
984 
985  break;
986  }
987 
988  case TargetOpcode::G_CONSTANT:
989  case TargetOpcode::G_FCONSTANT: {
990  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
991  if (DstTy.isVector())
992  report("Instruction cannot use a vector result type", MI);
993 
994  if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
995  if (!MI->getOperand(1).isCImm()) {
996  report("G_CONSTANT operand must be cimm", MI);
997  break;
998  }
999 
1000  const ConstantInt *CI = MI->getOperand(1).getCImm();
1001  if (CI->getBitWidth() != DstTy.getSizeInBits())
1002  report("inconsistent constant size", MI);
1003  } else {
1004  if (!MI->getOperand(1).isFPImm()) {
1005  report("G_FCONSTANT operand must be fpimm", MI);
1006  break;
1007  }
1008  const ConstantFP *CF = MI->getOperand(1).getFPImm();
1009 
1011  DstTy.getSizeInBits()) {
1012  report("inconsistent constant size", MI);
1013  }
1014  }
1015 
1016  break;
1017  }
1018  case TargetOpcode::G_LOAD:
1019  case TargetOpcode::G_STORE:
1020  case TargetOpcode::G_ZEXTLOAD:
1021  case TargetOpcode::G_SEXTLOAD: {
1022  LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1023  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1024  if (!PtrTy.isPointer())
1025  report("Generic memory instruction must access a pointer", MI);
1026 
1027  // Generic loads and stores must have a single MachineMemOperand
1028  // describing that access.
1029  if (!MI->hasOneMemOperand()) {
1030  report("Generic instruction accessing memory must have one mem operand",
1031  MI);
1032  } else {
1033  const MachineMemOperand &MMO = **MI->memoperands_begin();
1034  if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1035  MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1036  if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1037  report("Generic extload must have a narrower memory type", MI);
1038  } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1039  if (MMO.getSize() > ValTy.getSizeInBytes())
1040  report("load memory size cannot exceed result size", MI);
1041  } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1042  if (ValTy.getSizeInBytes() < MMO.getSize())
1043  report("store memory size cannot exceed value size", MI);
1044  }
1045  }
1046 
1047  break;
1048  }
1049  case TargetOpcode::G_PHI: {
1050  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1051  if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1052  [this, &DstTy](const MachineOperand &MO) {
1053  if (!MO.isReg())
1054  return true;
1055  LLT Ty = MRI->getType(MO.getReg());
1056  if (!Ty.isValid() || (Ty != DstTy))
1057  return false;
1058  return true;
1059  }))
1060  report("Generic Instruction G_PHI has operands with incompatible/missing "
1061  "types",
1062  MI);
1063  break;
1064  }
1065  case TargetOpcode::G_BITCAST: {
1066  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1067  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1068  if (!DstTy.isValid() || !SrcTy.isValid())
1069  break;
1070 
1071  if (SrcTy.isPointer() != DstTy.isPointer())
1072  report("bitcast cannot convert between pointers and other types", MI);
1073 
1074  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1075  report("bitcast sizes must match", MI);
1076 
1077  if (SrcTy == DstTy)
1078  report("bitcast must change the type", MI);
1079 
1080  break;
1081  }
1082  case TargetOpcode::G_INTTOPTR:
1083  case TargetOpcode::G_PTRTOINT:
1084  case TargetOpcode::G_ADDRSPACE_CAST: {
1085  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1086  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1087  if (!DstTy.isValid() || !SrcTy.isValid())
1088  break;
1089 
1090  verifyVectorElementMatch(DstTy, SrcTy, MI);
1091 
1092  DstTy = DstTy.getScalarType();
1093  SrcTy = SrcTy.getScalarType();
1094 
1095  if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1096  if (!DstTy.isPointer())
1097  report("inttoptr result type must be a pointer", MI);
1098  if (SrcTy.isPointer())
1099  report("inttoptr source type must not be a pointer", MI);
1100  } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1101  if (!SrcTy.isPointer())
1102  report("ptrtoint source type must be a pointer", MI);
1103  if (DstTy.isPointer())
1104  report("ptrtoint result type must not be a pointer", MI);
1105  } else {
1106  assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1107  if (!SrcTy.isPointer() || !DstTy.isPointer())
1108  report("addrspacecast types must be pointers", MI);
1109  else {
1110  if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1111  report("addrspacecast must convert different address spaces", MI);
1112  }
1113  }
1114 
1115  break;
1116  }
1117  case TargetOpcode::G_PTR_ADD: {
1118  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1119  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1120  LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1121  if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1122  break;
1123 
1124  if (!PtrTy.getScalarType().isPointer())
1125  report("gep first operand must be a pointer", MI);
1126 
1127  if (OffsetTy.getScalarType().isPointer())
1128  report("gep offset operand must not be a pointer", MI);
1129 
1130  // TODO: Is the offset allowed to be a scalar with a vector?
1131  break;
1132  }
1133  case TargetOpcode::G_PTRMASK: {
1134  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1135  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1136  LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1137  if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1138  break;
1139 
1140  if (!DstTy.getScalarType().isPointer())
1141  report("ptrmask result type must be a pointer", MI);
1142 
1143  if (!MaskTy.getScalarType().isScalar())
1144  report("ptrmask mask type must be an integer", MI);
1145 
1146  verifyVectorElementMatch(DstTy, MaskTy, MI);
1147  break;
1148  }
1149  case TargetOpcode::G_SEXT:
1150  case TargetOpcode::G_ZEXT:
1151  case TargetOpcode::G_ANYEXT:
1152  case TargetOpcode::G_TRUNC:
1153  case TargetOpcode::G_FPEXT:
1154  case TargetOpcode::G_FPTRUNC: {
1155  // Number of operands and presense of types is already checked (and
1156  // reported in case of any issues), so no need to report them again. As
1157  // we're trying to report as many issues as possible at once, however, the
1158  // instructions aren't guaranteed to have the right number of operands or
1159  // types attached to them at this point
1160  assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1161  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1162  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1163  if (!DstTy.isValid() || !SrcTy.isValid())
1164  break;
1165 
1166  LLT DstElTy = DstTy.getScalarType();
1167  LLT SrcElTy = SrcTy.getScalarType();
1168  if (DstElTy.isPointer() || SrcElTy.isPointer())
1169  report("Generic extend/truncate can not operate on pointers", MI);
1170 
1171  verifyVectorElementMatch(DstTy, SrcTy, MI);
1172 
1173  unsigned DstSize = DstElTy.getSizeInBits();
1174  unsigned SrcSize = SrcElTy.getSizeInBits();
1175  switch (MI->getOpcode()) {
1176  default:
1177  if (DstSize <= SrcSize)
1178  report("Generic extend has destination type no larger than source", MI);
1179  break;
1180  case TargetOpcode::G_TRUNC:
1181  case TargetOpcode::G_FPTRUNC:
1182  if (DstSize >= SrcSize)
1183  report("Generic truncate has destination type no smaller than source",
1184  MI);
1185  break;
1186  }
1187  break;
1188  }
1189  case TargetOpcode::G_SELECT: {
1190  LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1191  LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1192  if (!SelTy.isValid() || !CondTy.isValid())
1193  break;
1194 
1195  // Scalar condition select on a vector is valid.
1196  if (CondTy.isVector())
1197  verifyVectorElementMatch(SelTy, CondTy, MI);
1198  break;
1199  }
1200  case TargetOpcode::G_MERGE_VALUES: {
1201  // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1202  // e.g. s2N = MERGE sN, sN
1203  // Merging multiple scalars into a vector is not allowed, should use
1204  // G_BUILD_VECTOR for that.
1205  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1206  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1207  if (DstTy.isVector() || SrcTy.isVector())
1208  report("G_MERGE_VALUES cannot operate on vectors", MI);
1209 
1210  const unsigned NumOps = MI->getNumOperands();
1211  if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1212  report("G_MERGE_VALUES result size is inconsistent", MI);
1213 
1214  for (unsigned I = 2; I != NumOps; ++I) {
1215  if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1216  report("G_MERGE_VALUES source types do not match", MI);
1217  }
1218 
1219  break;
1220  }
1221  case TargetOpcode::G_UNMERGE_VALUES: {
1222  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1223  LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1224  // For now G_UNMERGE can split vectors.
1225  for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1226  if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1227  report("G_UNMERGE_VALUES destination types do not match", MI);
1228  }
1229  if (SrcTy.getSizeInBits() !=
1230  (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1231  report("G_UNMERGE_VALUES source operand does not cover dest operands",
1232  MI);
1233  }
1234  break;
1235  }
1236  case TargetOpcode::G_BUILD_VECTOR: {
1237  // Source types must be scalars, dest type a vector. Total size of scalars
1238  // must match the dest vector size.
1239  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1240  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1241  if (!DstTy.isVector() || SrcEltTy.isVector()) {
1242  report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1243  break;
1244  }
1245 
1246  if (DstTy.getElementType() != SrcEltTy)
1247  report("G_BUILD_VECTOR result element type must match source type", MI);
1248 
1249  if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1250  report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1251 
1252  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1253  if (MRI->getType(MI->getOperand(1).getReg()) !=
1254  MRI->getType(MI->getOperand(i).getReg()))
1255  report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1256  }
1257 
1258  break;
1259  }
1260  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1261  // Source types must be scalars, dest type a vector. Scalar types must be
1262  // larger than the dest vector elt type, as this is a truncating operation.
1263  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1264  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1265  if (!DstTy.isVector() || SrcEltTy.isVector())
1266  report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1267  MI);
1268  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1269  if (MRI->getType(MI->getOperand(1).getReg()) !=
1270  MRI->getType(MI->getOperand(i).getReg()))
1271  report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1272  MI);
1273  }
1274  if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1275  report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1276  "dest elt type",
1277  MI);
1278  break;
1279  }
1280  case TargetOpcode::G_CONCAT_VECTORS: {
1281  // Source types should be vectors, and total size should match the dest
1282  // vector size.
1283  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1284  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1285  if (!DstTy.isVector() || !SrcTy.isVector())
1286  report("G_CONCAT_VECTOR requires vector source and destination operands",
1287  MI);
1288 
1289  if (MI->getNumOperands() < 3)
1290  report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1291 
1292  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1293  if (MRI->getType(MI->getOperand(1).getReg()) !=
1294  MRI->getType(MI->getOperand(i).getReg()))
1295  report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1296  }
1297  if (DstTy.getNumElements() !=
1298  SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1299  report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1300  break;
1301  }
1302  case TargetOpcode::G_ICMP:
1303  case TargetOpcode::G_FCMP: {
1304  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1305  LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1306 
1307  if ((DstTy.isVector() != SrcTy.isVector()) ||
1308  (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1309  report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1310 
1311  break;
1312  }
1313  case TargetOpcode::G_EXTRACT: {
1314  const MachineOperand &SrcOp = MI->getOperand(1);
1315  if (!SrcOp.isReg()) {
1316  report("extract source must be a register", MI);
1317  break;
1318  }
1319 
1320  const MachineOperand &OffsetOp = MI->getOperand(2);
1321  if (!OffsetOp.isImm()) {
1322  report("extract offset must be a constant", MI);
1323  break;
1324  }
1325 
1326  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1327  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1328  if (SrcSize == DstSize)
1329  report("extract source must be larger than result", MI);
1330 
1331  if (DstSize + OffsetOp.getImm() > SrcSize)
1332  report("extract reads past end of register", MI);
1333  break;
1334  }
1335  case TargetOpcode::G_INSERT: {
1336  const MachineOperand &SrcOp = MI->getOperand(2);
1337  if (!SrcOp.isReg()) {
1338  report("insert source must be a register", MI);
1339  break;
1340  }
1341 
1342  const MachineOperand &OffsetOp = MI->getOperand(3);
1343  if (!OffsetOp.isImm()) {
1344  report("insert offset must be a constant", MI);
1345  break;
1346  }
1347 
1348  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1349  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1350 
1351  if (DstSize <= SrcSize)
1352  report("inserted size must be smaller than total register", MI);
1353 
1354  if (SrcSize + OffsetOp.getImm() > DstSize)
1355  report("insert writes past end of register", MI);
1356 
1357  break;
1358  }
1359  case TargetOpcode::G_JUMP_TABLE: {
1360  if (!MI->getOperand(1).isJTI())
1361  report("G_JUMP_TABLE source operand must be a jump table index", MI);
1362  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1363  if (!DstTy.isPointer())
1364  report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1365  break;
1366  }
1367  case TargetOpcode::G_BRJT: {
1368  if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1369  report("G_BRJT src operand 0 must be a pointer type", MI);
1370 
1371  if (!MI->getOperand(1).isJTI())
1372  report("G_BRJT src operand 1 must be a jump table index", MI);
1373 
1374  const auto &IdxOp = MI->getOperand(2);
1375  if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1376  report("G_BRJT src operand 2 must be a scalar reg type", MI);
1377  break;
1378  }
1379  case TargetOpcode::G_INTRINSIC:
1380  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1381  // TODO: Should verify number of def and use operands, but the current
1382  // interface requires passing in IR types for mangling.
1383  const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1384  if (!IntrIDOp.isIntrinsicID()) {
1385  report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1386  break;
1387  }
1388 
1389  bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1390  unsigned IntrID = IntrIDOp.getIntrinsicID();
1391  if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1393  = Intrinsic::getAttributes(MF->getFunction().getContext(),
1394  static_cast<Intrinsic::ID>(IntrID));
1395  bool DeclHasSideEffects = !Attrs.hasFnAttribute(Attribute::ReadNone);
1396  if (NoSideEffects && DeclHasSideEffects) {
1397  report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1398  break;
1399  }
1400  if (!NoSideEffects && !DeclHasSideEffects) {
1401  report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1402  break;
1403  }
1404  }
1405 
1406  break;
1407  }
1408  case TargetOpcode::G_SEXT_INREG: {
1409  if (!MI->getOperand(2).isImm()) {
1410  report("G_SEXT_INREG expects an immediate operand #2", MI);
1411  break;
1412  }
1413 
1414  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1415  int64_t Imm = MI->getOperand(2).getImm();
1416  if (Imm <= 0)
1417  report("G_SEXT_INREG size must be >= 1", MI);
1418  if (Imm >= SrcTy.getScalarSizeInBits())
1419  report("G_SEXT_INREG size must be less than source bit width", MI);
1420  break;
1421  }
1422  case TargetOpcode::G_SHUFFLE_VECTOR: {
1423  const MachineOperand &MaskOp = MI->getOperand(3);
1424  if (!MaskOp.isShuffleMask()) {
1425  report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1426  break;
1427  }
1428 
1429  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1430  LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1431  LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1432 
1433  if (Src0Ty != Src1Ty)
1434  report("Source operands must be the same type", MI);
1435 
1436  if (Src0Ty.getScalarType() != DstTy.getScalarType())
1437  report("G_SHUFFLE_VECTOR cannot change element type", MI);
1438 
1439  // Don't check that all operands are vector because scalars are used in
1440  // place of 1 element vectors.
1441  int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1442  int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1443 
1444  ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1445 
1446  if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1447  report("Wrong result type for shufflemask", MI);
1448 
1449  for (int Idx : MaskIdxes) {
1450  if (Idx < 0)
1451  continue;
1452 
1453  if (Idx >= 2 * SrcNumElts)
1454  report("Out of bounds shuffle index", MI);
1455  }
1456 
1457  break;
1458  }
1459  case TargetOpcode::G_DYN_STACKALLOC: {
1460  const MachineOperand &DstOp = MI->getOperand(0);
1461  const MachineOperand &AllocOp = MI->getOperand(1);
1462  const MachineOperand &AlignOp = MI->getOperand(2);
1463 
1464  if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1465  report("dst operand 0 must be a pointer type", MI);
1466  break;
1467  }
1468 
1469  if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1470  report("src operand 1 must be a scalar reg type", MI);
1471  break;
1472  }
1473 
1474  if (!AlignOp.isImm()) {
1475  report("src operand 2 must be an immediate type", MI);
1476  break;
1477  }
1478  break;
1479  }
1480  case TargetOpcode::G_MEMCPY_INLINE:
1481  case TargetOpcode::G_MEMCPY:
1482  case TargetOpcode::G_MEMMOVE: {
1483  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1484  if (MMOs.size() != 2) {
1485  report("memcpy/memmove must have 2 memory operands", MI);
1486  break;
1487  }
1488 
1489  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1490  (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1491  report("wrong memory operand types", MI);
1492  break;
1493  }
1494 
1495  if (MMOs[0]->getSize() != MMOs[1]->getSize())
1496  report("inconsistent memory operand sizes", MI);
1497 
1498  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1499  LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1500 
1501  if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1502  report("memory instruction operand must be a pointer", MI);
1503  break;
1504  }
1505 
1506  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1507  report("inconsistent store address space", MI);
1508  if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1509  report("inconsistent load address space", MI);
1510 
1511  if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1512  if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1513  report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1514 
1515  break;
1516  }
1517  case TargetOpcode::G_BZERO:
1518  case TargetOpcode::G_MEMSET: {
1519  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1520  std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1521  if (MMOs.size() != 1) {
1522  report(Twine(Name, " must have 1 memory operand"), MI);
1523  break;
1524  }
1525 
1526  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1527  report(Twine(Name, " memory operand must be a store"), MI);
1528  break;
1529  }
1530 
1531  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1532  if (!DstPtrTy.isPointer()) {
1533  report(Twine(Name, " operand must be a pointer"), MI);
1534  break;
1535  }
1536 
1537  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1538  report("inconsistent " + Twine(Name, " address space"), MI);
1539 
1540  if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1541  (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1542  report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1543 
1544  break;
1545  }
1546  case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1547  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1548  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1549  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1550  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1551  if (!DstTy.isScalar())
1552  report("Vector reduction requires a scalar destination type", MI);
1553  if (!Src1Ty.isScalar())
1554  report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1555  if (!Src2Ty.isVector())
1556  report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1557  break;
1558  }
1559  case TargetOpcode::G_VECREDUCE_FADD:
1560  case TargetOpcode::G_VECREDUCE_FMUL:
1561  case TargetOpcode::G_VECREDUCE_FMAX:
1562  case TargetOpcode::G_VECREDUCE_FMIN:
1563  case TargetOpcode::G_VECREDUCE_ADD:
1564  case TargetOpcode::G_VECREDUCE_MUL:
1565  case TargetOpcode::G_VECREDUCE_AND:
1566  case TargetOpcode::G_VECREDUCE_OR:
1567  case TargetOpcode::G_VECREDUCE_XOR:
1568  case TargetOpcode::G_VECREDUCE_SMAX:
1569  case TargetOpcode::G_VECREDUCE_SMIN:
1570  case TargetOpcode::G_VECREDUCE_UMAX:
1571  case TargetOpcode::G_VECREDUCE_UMIN: {
1572  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1573  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1574  if (!DstTy.isScalar())
1575  report("Vector reduction requires a scalar destination type", MI);
1576  if (!SrcTy.isVector())
1577  report("Vector reduction requires vector source=", MI);
1578  break;
1579  }
1580 
1581  case TargetOpcode::G_SBFX:
1582  case TargetOpcode::G_UBFX: {
1583  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1584  if (DstTy.isVector()) {
1585  report("Bitfield extraction is not supported on vectors", MI);
1586  break;
1587  }
1588  break;
1589  }
1590  case TargetOpcode::G_ROTR:
1591  case TargetOpcode::G_ROTL: {
1592  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1593  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1594  if (Src1Ty.isVector() != Src2Ty.isVector()) {
1595  report("Rotate requires operands to be either all scalars or all vectors",
1596  MI);
1597  break;
1598  }
1599  break;
1600  }
1601 
1602  default:
1603  break;
1604  }
1605 }
1606 
1607 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1608  const MCInstrDesc &MCID = MI->getDesc();
1609  if (MI->getNumOperands() < MCID.getNumOperands()) {
1610  report("Too few operands", MI);
1611  errs() << MCID.getNumOperands() << " operands expected, but "
1612  << MI->getNumOperands() << " given.\n";
1613  }
1614 
1615  if (MI->isPHI()) {
1616  if (MF->getProperties().hasProperty(
1618  report("Found PHI instruction with NoPHIs property set", MI);
1619 
1620  if (FirstNonPHI)
1621  report("Found PHI instruction after non-PHI", MI);
1622  } else if (FirstNonPHI == nullptr)
1623  FirstNonPHI = MI;
1624 
1625  // Check the tied operands.
1626  if (MI->isInlineAsm())
1627  verifyInlineAsm(MI);
1628 
1629  // Check that unspillable terminators define a reg and have at most one use.
1630  if (TII->isUnspillableTerminator(MI)) {
1631  if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
1632  report("Unspillable Terminator does not define a reg", MI);
1633  Register Def = MI->getOperand(0).getReg();
1634  if (Def.isVirtual() &&
1635  std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
1636  report("Unspillable Terminator expected to have at most one use!", MI);
1637  }
1638 
1639  // A fully-formed DBG_VALUE must have a location. Ignore partially formed
1640  // DBG_VALUEs: these are convenient to use in tests, but should never get
1641  // generated.
1642  if (MI->isDebugValue() && MI->getNumOperands() == 4)
1643  if (!MI->getDebugLoc())
1644  report("Missing DebugLoc for debug instruction", MI);
1645 
1646  // Meta instructions should never be the subject of debug value tracking,
1647  // they don't create a value in the output program at all.
1648  if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
1649  report("Metadata instruction should not have a value tracking number", MI);
1650 
1651  // Check the MachineMemOperands for basic consistency.
1652  for (MachineMemOperand *Op : MI->memoperands()) {
1653  if (Op->isLoad() && !MI->mayLoad())
1654  report("Missing mayLoad flag", MI);
1655  if (Op->isStore() && !MI->mayStore())
1656  report("Missing mayStore flag", MI);
1657  }
1658 
1659  // Debug values must not have a slot index.
1660  // Other instructions must have one, unless they are inside a bundle.
1661  if (LiveInts) {
1662  bool mapped = !LiveInts->isNotInMIMap(*MI);
1663  if (MI->isDebugOrPseudoInstr()) {
1664  if (mapped)
1665  report("Debug instruction has a slot index", MI);
1666  } else if (MI->isInsideBundle()) {
1667  if (mapped)
1668  report("Instruction inside bundle has a slot index", MI);
1669  } else {
1670  if (!mapped)
1671  report("Missing slot index", MI);
1672  }
1673  }
1674 
1675  unsigned Opc = MCID.getOpcode();
1677  verifyPreISelGenericInstruction(MI);
1678  return;
1679  }
1680 
1682  if (!TII->verifyInstruction(*MI, ErrorInfo))
1683  report(ErrorInfo.data(), MI);
1684 
1685  // Verify properties of various specific instruction types
1686  switch (MI->getOpcode()) {
1687  case TargetOpcode::COPY: {
1688  const MachineOperand &DstOp = MI->getOperand(0);
1689  const MachineOperand &SrcOp = MI->getOperand(1);
1690  const Register SrcReg = SrcOp.getReg();
1691  const Register DstReg = DstOp.getReg();
1692 
1693  LLT DstTy = MRI->getType(DstReg);
1694  LLT SrcTy = MRI->getType(SrcReg);
1695  if (SrcTy.isValid() && DstTy.isValid()) {
1696  // If both types are valid, check that the types are the same.
1697  if (SrcTy != DstTy) {
1698  report("Copy Instruction is illegal with mismatching types", MI);
1699  errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1700  }
1701 
1702  break;
1703  }
1704 
1705  if (!SrcTy.isValid() && !DstTy.isValid())
1706  break;
1707 
1708  // If we have only one valid type, this is likely a copy between a virtual
1709  // and physical register.
1710  unsigned SrcSize = 0;
1711  unsigned DstSize = 0;
1712  if (SrcReg.isPhysical() && DstTy.isValid()) {
1713  const TargetRegisterClass *SrcRC =
1714  TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1715  if (SrcRC)
1716  SrcSize = TRI->getRegSizeInBits(*SrcRC);
1717  }
1718 
1719  if (SrcSize == 0)
1720  SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
1721 
1722  if (DstReg.isPhysical() && SrcTy.isValid()) {
1723  const TargetRegisterClass *DstRC =
1724  TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1725  if (DstRC)
1726  DstSize = TRI->getRegSizeInBits(*DstRC);
1727  }
1728 
1729  if (DstSize == 0)
1730  DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
1731 
1732  if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1733  if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1734  report("Copy Instruction is illegal with mismatching sizes", MI);
1735  errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1736  << "\n";
1737  }
1738  }
1739  break;
1740  }
1741  case TargetOpcode::STATEPOINT: {
1742  StatepointOpers SO(MI);
1743  if (!MI->getOperand(SO.getIDPos()).isImm() ||
1744  !MI->getOperand(SO.getNBytesPos()).isImm() ||
1745  !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1746  report("meta operands to STATEPOINT not constant!", MI);
1747  break;
1748  }
1749 
1750  auto VerifyStackMapConstant = [&](unsigned Offset) {
1751  if (Offset >= MI->getNumOperands()) {
1752  report("stack map constant to STATEPOINT is out of range!", MI);
1753  return;
1754  }
1755  if (!MI->getOperand(Offset - 1).isImm() ||
1756  MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
1757  !MI->getOperand(Offset).isImm())
1758  report("stack map constant to STATEPOINT not well formed!", MI);
1759  };
1760  VerifyStackMapConstant(SO.getCCIdx());
1761  VerifyStackMapConstant(SO.getFlagsIdx());
1762  VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1763  VerifyStackMapConstant(SO.getNumGCPtrIdx());
1764  VerifyStackMapConstant(SO.getNumAllocaIdx());
1765  VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1766 
1767  // Verify that all explicit statepoint defs are tied to gc operands as
1768  // they are expected to be a relocation of gc operands.
1769  unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1770  unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1771  for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
1772  unsigned UseOpIdx;
1773  if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
1774  report("STATEPOINT defs expected to be tied", MI);
1775  break;
1776  }
1777  if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1778  report("STATEPOINT def tied to non-gc operand", MI);
1779  break;
1780  }
1781  }
1782 
1783  // TODO: verify we have properly encoded deopt arguments
1784  } break;
1785  case TargetOpcode::INSERT_SUBREG: {
1786  unsigned InsertedSize;
1787  if (unsigned SubIdx = MI->getOperand(2).getSubReg())
1788  InsertedSize = TRI->getSubRegIdxSize(SubIdx);
1789  else
1790  InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
1791  unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
1792  if (SubRegSize < InsertedSize) {
1793  report("INSERT_SUBREG expected inserted value to have equal or lesser "
1794  "size than the subreg it was inserted into", MI);
1795  break;
1796  }
1797  } break;
1798  }
1799 }
1800 
1801 void
1802 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1803  const MachineInstr *MI = MO->getParent();
1804  const MCInstrDesc &MCID = MI->getDesc();
1805  unsigned NumDefs = MCID.getNumDefs();
1806  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1807  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1808 
1809  // The first MCID.NumDefs operands must be explicit register defines
1810  if (MONum < NumDefs) {
1811  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1812  if (!MO->isReg())
1813  report("Explicit definition must be a register", MO, MONum);
1814  else if (!MO->isDef() && !MCOI.isOptionalDef())
1815  report("Explicit definition marked as use", MO, MONum);
1816  else if (MO->isImplicit())
1817  report("Explicit definition marked as implicit", MO, MONum);
1818  } else if (MONum < MCID.getNumOperands()) {
1819  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1820  // Don't check if it's the last operand in a variadic instruction. See,
1821  // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
1822  bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
1823  if (!IsOptional) {
1824  if (MO->isReg()) {
1825  if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
1826  report("Explicit operand marked as def", MO, MONum);
1827  if (MO->isImplicit())
1828  report("Explicit operand marked as implicit", MO, MONum);
1829  }
1830 
1831  // Check that an instruction has register operands only as expected.
1832  if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
1833  !MO->isReg() && !MO->isFI())
1834  report("Expected a register operand.", MO, MONum);
1835  if (MO->isReg()) {
1836  if (MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
1837  (MCOI.OperandType == MCOI::OPERAND_PCREL &&
1838  !TII->isPCRelRegisterOperandLegal(*MO)))
1839  report("Expected a non-register operand.", MO, MONum);
1840  }
1841  }
1842 
1843  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1844  if (TiedTo != -1) {
1845  if (!MO->isReg())
1846  report("Tied use must be a register", MO, MONum);
1847  else if (!MO->isTied())
1848  report("Operand should be tied", MO, MONum);
1849  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1850  report("Tied def doesn't match MCInstrDesc", MO, MONum);
1851  else if (Register::isPhysicalRegister(MO->getReg())) {
1852  const MachineOperand &MOTied = MI->getOperand(TiedTo);
1853  if (!MOTied.isReg())
1854  report("Tied counterpart must be a register", &MOTied, TiedTo);
1855  else if (Register::isPhysicalRegister(MOTied.getReg()) &&
1856  MO->getReg() != MOTied.getReg())
1857  report("Tied physical registers must match.", &MOTied, TiedTo);
1858  }
1859  } else if (MO->isReg() && MO->isTied())
1860  report("Explicit operand should not be tied", MO, MONum);
1861  } else {
1862  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1863  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1864  report("Extra explicit operand on non-variadic instruction", MO, MONum);
1865  }
1866 
1867  switch (MO->getType()) {
1869  const Register Reg = MO->getReg();
1870  if (!Reg)
1871  return;
1872  if (MRI->tracksLiveness() && !MI->isDebugValue())
1873  checkLiveness(MO, MONum);
1874 
1875  // Verify the consistency of tied operands.
1876  if (MO->isTied()) {
1877  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1878  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1879  if (!OtherMO.isReg())
1880  report("Must be tied to a register", MO, MONum);
1881  if (!OtherMO.isTied())
1882  report("Missing tie flags on tied operand", MO, MONum);
1883  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1884  report("Inconsistent tie links", MO, MONum);
1885  if (MONum < MCID.getNumDefs()) {
1886  if (OtherIdx < MCID.getNumOperands()) {
1887  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1888  report("Explicit def tied to explicit use without tie constraint",
1889  MO, MONum);
1890  } else {
1891  if (!OtherMO.isImplicit())
1892  report("Explicit def should be tied to implicit use", MO, MONum);
1893  }
1894  }
1895  }
1896 
1897  // Verify two-address constraints after the twoaddressinstruction pass.
1898  // Both twoaddressinstruction pass and phi-node-elimination pass call
1899  // MRI->leaveSSA() to set MF as NoSSA, we should do the verification after
1900  // twoaddressinstruction pass not after phi-node-elimination pass. So we
1901  // shouldn't use the NoSSA as the condition, we should based on
1902  // TiedOpsRewritten property to verify two-address constraints, this
1903  // property will be set in twoaddressinstruction pass.
1904  unsigned DefIdx;
1905  if (MF->getProperties().hasProperty(
1907  MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1908  Reg != MI->getOperand(DefIdx).getReg())
1909  report("Two-address instruction operands must be identical", MO, MONum);
1910 
1911  // Check register classes.
1912  unsigned SubIdx = MO->getSubReg();
1913 
1915  if (SubIdx) {
1916  report("Illegal subregister index for physical register", MO, MONum);
1917  return;
1918  }
1919  if (MONum < MCID.getNumOperands()) {
1920  if (const TargetRegisterClass *DRC =
1921  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1922  if (!DRC->contains(Reg)) {
1923  report("Illegal physical register for instruction", MO, MONum);
1924  errs() << printReg(Reg, TRI) << " is not a "
1925  << TRI->getRegClassName(DRC) << " register.\n";
1926  }
1927  }
1928  }
1929  if (MO->isRenamable()) {
1930  if (MRI->isReserved(Reg)) {
1931  report("isRenamable set on reserved register", MO, MONum);
1932  return;
1933  }
1934  }
1935  if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) {
1936  report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
1937  return;
1938  }
1939  } else {
1940  // Virtual register.
1942  if (!RC) {
1943  // This is a generic virtual register.
1944 
1945  // Do not allow undef uses for generic virtual registers. This ensures
1946  // getVRegDef can never fail and return null on a generic register.
1947  //
1948  // FIXME: This restriction should probably be broadened to all SSA
1949  // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
1950  // run on the SSA function just before phi elimination.
1951  if (MO->isUndef())
1952  report("Generic virtual register use cannot be undef", MO, MONum);
1953 
1954  // If we're post-Select, we can't have gvregs anymore.
1955  if (isFunctionSelected) {
1956  report("Generic virtual register invalid in a Selected function",
1957  MO, MONum);
1958  return;
1959  }
1960 
1961  // The gvreg must have a type and it must not have a SubIdx.
1962  LLT Ty = MRI->getType(Reg);
1963  if (!Ty.isValid()) {
1964  report("Generic virtual register must have a valid type", MO,
1965  MONum);
1966  return;
1967  }
1968 
1969  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1970 
1971  // If we're post-RegBankSelect, the gvreg must have a bank.
1972  if (!RegBank && isFunctionRegBankSelected) {
1973  report("Generic virtual register must have a bank in a "
1974  "RegBankSelected function",
1975  MO, MONum);
1976  return;
1977  }
1978 
1979  // Make sure the register fits into its register bank if any.
1980  if (RegBank && Ty.isValid() &&
1981  RegBank->getSize() < Ty.getSizeInBits()) {
1982  report("Register bank is too small for virtual register", MO,
1983  MONum);
1984  errs() << "Register bank " << RegBank->getName() << " too small("
1985  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
1986  << "-bits\n";
1987  return;
1988  }
1989  if (SubIdx) {
1990  report("Generic virtual register does not allow subregister index", MO,
1991  MONum);
1992  return;
1993  }
1994 
1995  // If this is a target specific instruction and this operand
1996  // has register class constraint, the virtual register must
1997  // comply to it.
1998  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
1999  MONum < MCID.getNumOperands() &&
2000  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2001  report("Virtual register does not match instruction constraint", MO,
2002  MONum);
2003  errs() << "Expect register class "
2004  << TRI->getRegClassName(
2005  TII->getRegClass(MCID, MONum, TRI, *MF))
2006  << " but got nothing\n";
2007  return;
2008  }
2009 
2010  break;
2011  }
2012  if (SubIdx) {
2013  const TargetRegisterClass *SRC =
2014  TRI->getSubClassWithSubReg(RC, SubIdx);
2015  if (!SRC) {
2016  report("Invalid subregister index for virtual register", MO, MONum);
2017  errs() << "Register class " << TRI->getRegClassName(RC)
2018  << " does not support subreg index " << SubIdx << "\n";
2019  return;
2020  }
2021  if (RC != SRC) {
2022  report("Invalid register class for subregister index", MO, MONum);
2023  errs() << "Register class " << TRI->getRegClassName(RC)
2024  << " does not fully support subreg index " << SubIdx << "\n";
2025  return;
2026  }
2027  }
2028  if (MONum < MCID.getNumOperands()) {
2029  if (const TargetRegisterClass *DRC =
2030  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2031  if (SubIdx) {
2032  const TargetRegisterClass *SuperRC =
2033  TRI->getLargestLegalSuperClass(RC, *MF);
2034  if (!SuperRC) {
2035  report("No largest legal super class exists.", MO, MONum);
2036  return;
2037  }
2038  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2039  if (!DRC) {
2040  report("No matching super-reg register class.", MO, MONum);
2041  return;
2042  }
2043  }
2044  if (!RC->hasSuperClassEq(DRC)) {
2045  report("Illegal virtual register for instruction", MO, MONum);
2046  errs() << "Expected a " << TRI->getRegClassName(DRC)
2047  << " register, but got a " << TRI->getRegClassName(RC)
2048  << " register\n";
2049  }
2050  }
2051  }
2052  }
2053  break;
2054  }
2055 
2057  regMasks.push_back(MO->getRegMask());
2058  break;
2059 
2061  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2062  report("PHI operand is not in the CFG", MO, MONum);
2063  break;
2064 
2066  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2067  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2068  int FI = MO->getIndex();
2069  LiveInterval &LI = LiveStks->getInterval(FI);
2070  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2071 
2072  bool stores = MI->mayStore();
2073  bool loads = MI->mayLoad();
2074  // For a memory-to-memory move, we need to check if the frame
2075  // index is used for storing or loading, by inspecting the
2076  // memory operands.
2077  if (stores && loads) {
2078  for (auto *MMO : MI->memoperands()) {
2079  const PseudoSourceValue *PSV = MMO->getPseudoValue();
2080  if (PSV == nullptr) continue;
2082  dyn_cast<FixedStackPseudoSourceValue>(PSV);
2083  if (Value == nullptr) continue;
2084  if (Value->getFrameIndex() != FI) continue;
2085 
2086  if (MMO->isStore())
2087  loads = false;
2088  else
2089  stores = false;
2090  break;
2091  }
2092  if (loads == stores)
2093  report("Missing fixed stack memoperand.", MI);
2094  }
2095  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2096  report("Instruction loads from dead spill slot", MO, MONum);
2097  errs() << "Live stack: " << LI << '\n';
2098  }
2099  if (stores && !LI.liveAt(Idx.getRegSlot())) {
2100  report("Instruction stores to dead spill slot", MO, MONum);
2101  errs() << "Live stack: " << LI << '\n';
2102  }
2103  }
2104  break;
2105 
2106  default:
2107  break;
2108  }
2109 }
2110 
2111 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2112  unsigned MONum, SlotIndex UseIdx,
2113  const LiveRange &LR,
2114  Register VRegOrUnit,
2115  LaneBitmask LaneMask) {
2116  LiveQueryResult LRQ = LR.Query(UseIdx);
2117  // Check if we have a segment at the use, note however that we only need one
2118  // live subregister range, the others may be dead.
2119  if (!LRQ.valueIn() && LaneMask.none()) {
2120  report("No live segment at use", MO, MONum);
2121  report_context_liverange(LR);
2122  report_context_vreg_regunit(VRegOrUnit);
2123  report_context(UseIdx);
2124  }
2125  if (MO->isKill() && !LRQ.isKill()) {
2126  report("Live range continues after kill flag", MO, MONum);
2127  report_context_liverange(LR);
2128  report_context_vreg_regunit(VRegOrUnit);
2129  if (LaneMask.any())
2130  report_context_lanemask(LaneMask);
2131  report_context(UseIdx);
2132  }
2133 }
2134 
2135 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2136  unsigned MONum, SlotIndex DefIdx,
2137  const LiveRange &LR,
2138  Register VRegOrUnit,
2139  bool SubRangeCheck,
2140  LaneBitmask LaneMask) {
2141  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2142  assert(VNI && "NULL valno is not allowed");
2143  if (VNI->def != DefIdx) {
2144  report("Inconsistent valno->def", MO, MONum);
2145  report_context_liverange(LR);
2146  report_context_vreg_regunit(VRegOrUnit);
2147  if (LaneMask.any())
2148  report_context_lanemask(LaneMask);
2149  report_context(*VNI);
2150  report_context(DefIdx);
2151  }
2152  } else {
2153  report("No live segment at def", MO, MONum);
2154  report_context_liverange(LR);
2155  report_context_vreg_regunit(VRegOrUnit);
2156  if (LaneMask.any())
2157  report_context_lanemask(LaneMask);
2158  report_context(DefIdx);
2159  }
2160  // Check that, if the dead def flag is present, LiveInts agree.
2161  if (MO->isDead()) {
2162  LiveQueryResult LRQ = LR.Query(DefIdx);
2163  if (!LRQ.isDeadDef()) {
2164  assert(Register::isVirtualRegister(VRegOrUnit) &&
2165  "Expecting a virtual register.");
2166  // A dead subreg def only tells us that the specific subreg is dead. There
2167  // could be other non-dead defs of other subregs, or we could have other
2168  // parts of the register being live through the instruction. So unless we
2169  // are checking liveness for a subrange it is ok for the live range to
2170  // continue, given that we have a dead def of a subregister.
2171  if (SubRangeCheck || MO->getSubReg() == 0) {
2172  report("Live range continues after dead def flag", MO, MONum);
2173  report_context_liverange(LR);
2174  report_context_vreg_regunit(VRegOrUnit);
2175  if (LaneMask.any())
2176  report_context_lanemask(LaneMask);
2177  }
2178  }
2179  }
2180 }
2181 
2182 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2183  const MachineInstr *MI = MO->getParent();
2184  const Register Reg = MO->getReg();
2185 
2186  // Both use and def operands can read a register.
2187  if (MO->readsReg()) {
2188  if (MO->isKill())
2189  addRegWithSubRegs(regsKilled, Reg);
2190 
2191  // Check that LiveVars knows this kill.
2192  if (LiveVars && Register::isVirtualRegister(Reg) && MO->isKill()) {
2193  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2194  if (!is_contained(VI.Kills, MI))
2195  report("Kill missing from LiveVariables", MO, MONum);
2196  }
2197 
2198  // Check LiveInts liveness and kill.
2199  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2200  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
2201  // Check the cached regunit intervals.
2202  if (Reg.isPhysical() && !isReserved(Reg)) {
2203  for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
2204  ++Units) {
2205  if (MRI->isReservedRegUnit(*Units))
2206  continue;
2207  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
2208  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2209  }
2210  }
2211 
2213  if (LiveInts->hasInterval(Reg)) {
2214  // This is a virtual register interval.
2215  const LiveInterval &LI = LiveInts->getInterval(Reg);
2216  checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
2217 
2218  if (LI.hasSubRanges() && !MO->isDef()) {
2219  unsigned SubRegIdx = MO->getSubReg();
2220  LaneBitmask MOMask = SubRegIdx != 0
2221  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2223  LaneBitmask LiveInMask;
2224  for (const LiveInterval::SubRange &SR : LI.subranges()) {
2225  if ((MOMask & SR.LaneMask).none())
2226  continue;
2227  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2228  LiveQueryResult LRQ = SR.Query(UseIdx);
2229  if (LRQ.valueIn())
2230  LiveInMask |= SR.LaneMask;
2231  }
2232  // At least parts of the register has to be live at the use.
2233  if ((LiveInMask & MOMask).none()) {
2234  report("No live subrange at use", MO, MONum);
2235  report_context(LI);
2236  report_context(UseIdx);
2237  }
2238  }
2239  } else {
2240  report("Virtual register has no live interval", MO, MONum);
2241  }
2242  }
2243  }
2244 
2245  // Use of a dead register.
2246  if (!regsLive.count(Reg)) {
2248  // Reserved registers may be used even when 'dead'.
2249  bool Bad = !isReserved(Reg);
2250  // We are fine if just any subregister has a defined value.
2251  if (Bad) {
2252 
2253  for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2254  if (regsLive.count(SubReg)) {
2255  Bad = false;
2256  break;
2257  }
2258  }
2259  }
2260  // If there is an additional implicit-use of a super register we stop
2261  // here. By definition we are fine if the super register is not
2262  // (completely) dead, if the complete super register is dead we will
2263  // get a report for its operand.
2264  if (Bad) {
2265  for (const MachineOperand &MOP : MI->uses()) {
2266  if (!MOP.isReg() || !MOP.isImplicit())
2267  continue;
2268 
2269  if (!Register::isPhysicalRegister(MOP.getReg()))
2270  continue;
2271 
2272  if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2273  Bad = false;
2274  }
2275  }
2276  if (Bad)
2277  report("Using an undefined physical register", MO, MONum);
2278  } else if (MRI->def_empty(Reg)) {
2279  report("Reading virtual register without a def", MO, MONum);
2280  } else {
2281  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2282  // We don't know which virtual registers are live in, so only complain
2283  // if vreg was killed in this MBB. Otherwise keep track of vregs that
2284  // must be live in. PHI instructions are handled separately.
2285  if (MInfo.regsKilled.count(Reg))
2286  report("Using a killed virtual register", MO, MONum);
2287  else if (!MI->isPHI())
2288  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2289  }
2290  }
2291  }
2292 
2293  if (MO->isDef()) {
2294  // Register defined.
2295  // TODO: verify that earlyclobber ops are not used.
2296  if (MO->isDead())
2297  addRegWithSubRegs(regsDead, Reg);
2298  else
2299  addRegWithSubRegs(regsDefined, Reg);
2300 
2301  // Verify SSA form.
2303  std::next(MRI->def_begin(Reg)) != MRI->def_end())
2304  report("Multiple virtual register defs in SSA form", MO, MONum);
2305 
2306  // Check LiveInts for a live segment, but only for virtual registers.
2307  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2308  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2309  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2310 
2312  if (LiveInts->hasInterval(Reg)) {
2313  const LiveInterval &LI = LiveInts->getInterval(Reg);
2314  checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
2315 
2316  if (LI.hasSubRanges()) {
2317  unsigned SubRegIdx = MO->getSubReg();
2318  LaneBitmask MOMask = SubRegIdx != 0
2319  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2321  for (const LiveInterval::SubRange &SR : LI.subranges()) {
2322  if ((SR.LaneMask & MOMask).none())
2323  continue;
2324  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2325  }
2326  }
2327  } else {
2328  report("Virtual register has no Live interval", MO, MONum);
2329  }
2330  }
2331  }
2332  }
2333 }
2334 
2335 // This function gets called after visiting all instructions in a bundle. The
2336 // argument points to the bundle header.
2337 // Normal stand-alone instructions are also considered 'bundles', and this
2338 // function is called for all of them.
2339 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2340  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2341  set_union(MInfo.regsKilled, regsKilled);
2342  set_subtract(regsLive, regsKilled); regsKilled.clear();
2343  // Kill any masked registers.
2344  while (!regMasks.empty()) {
2345  const uint32_t *Mask = regMasks.pop_back_val();
2346  for (Register Reg : regsLive)
2347  if (Reg.isPhysical() &&
2349  regsDead.push_back(Reg);
2350  }
2351  set_subtract(regsLive, regsDead); regsDead.clear();
2352  set_union(regsLive, regsDefined); regsDefined.clear();
2353 }
2354 
2355 void
2356 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2357  MBBInfoMap[MBB].regsLiveOut = regsLive;
2358  regsLive.clear();
2359 
2360  if (Indexes) {
2361  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2362  if (!(stop > lastIndex)) {
2363  report("Block ends before last instruction index", MBB);
2364  errs() << "Block ends at " << stop
2365  << " last instruction was at " << lastIndex << '\n';
2366  }
2367  lastIndex = stop;
2368  }
2369 }
2370 
2371 namespace {
2372 // This implements a set of registers that serves as a filter: can filter other
2373 // sets by passing through elements not in the filter and blocking those that
2374 // are. Any filter implicitly includes the full set of physical registers upon
2375 // creation, thus filtering them all out. The filter itself as a set only grows,
2376 // and needs to be as efficient as possible.
2377 struct VRegFilter {
2378  // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2379  // no duplicates. Both virtual and physical registers are fine.
2380  template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2381  SmallVector<Register, 0> VRegsBuffer;
2382  filterAndAdd(FromRegSet, VRegsBuffer);
2383  }
2384  // Filter \p FromRegSet through the filter and append passed elements into \p
2385  // ToVRegs. All elements appended are then added to the filter itself.
2386  // \returns true if anything changed.
2387  template <typename RegSetT>
2388  bool filterAndAdd(const RegSetT &FromRegSet,
2389  SmallVectorImpl<Register> &ToVRegs) {
2390  unsigned SparseUniverse = Sparse.size();
2391  unsigned NewSparseUniverse = SparseUniverse;
2392  unsigned NewDenseSize = Dense.size();
2393  size_t Begin = ToVRegs.size();
2394  for (Register Reg : FromRegSet) {
2395  if (!Reg.isVirtual())
2396  continue;
2397  unsigned Index = Register::virtReg2Index(Reg);
2398  if (Index < SparseUniverseMax) {
2399  if (Index < SparseUniverse && Sparse.test(Index))
2400  continue;
2401  NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2402  } else {
2403  if (Dense.count(Reg))
2404  continue;
2405  ++NewDenseSize;
2406  }
2407  ToVRegs.push_back(Reg);
2408  }
2409  size_t End = ToVRegs.size();
2410  if (Begin == End)
2411  return false;
2412  // Reserving space in sets once performs better than doing so continuously
2413  // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2414  // tuned all the way down) and double iteration (the second one is over a
2415  // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2416  Sparse.resize(NewSparseUniverse);
2417  Dense.reserve(NewDenseSize);
2418  for (unsigned I = Begin; I < End; ++I) {
2419  Register Reg = ToVRegs[I];
2420  unsigned Index = Register::virtReg2Index(Reg);
2421  if (Index < SparseUniverseMax)
2422  Sparse.set(Index);
2423  else
2424  Dense.insert(Reg);
2425  }
2426  return true;
2427  }
2428 
2429 private:
2430  static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2431  // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2432  // are tracked by Dense. The only purpose of the threashold and the Dense set
2433  // is to have a reasonably growing memory usage in pathological cases (large
2434  // number of very sparse VRegFilter instances live at the same time). In
2435  // practice even in the worst-by-execution time cases having all elements
2436  // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2437  // space efficient than if tracked by Dense. The threashold is set to keep the
2438  // worst-case memory usage within 2x of figures determined empirically for
2439  // "all Dense" scenario in such worst-by-execution-time cases.
2440  BitVector Sparse;
2441  DenseSet<unsigned> Dense;
2442 };
2443 
2444 // Implements both a transfer function and a (binary, in-place) join operator
2445 // for a dataflow over register sets with set union join and filtering transfer
2446 // (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2447 // Maintains out_b as its state, allowing for O(n) iteration over it at any
2448 // time, where n is the size of the set (as opposed to O(U) where U is the
2449 // universe). filter_b implicitly contains all physical registers at all times.
2450 class FilteringVRegSet {
2451  VRegFilter Filter;
2453 
2454 public:
2455  // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2456  // Both virtual and physical registers are fine.
2457  template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2458  Filter.add(RS);
2459  }
2460  // Passes \p RS through the filter_b (transfer function) and adds what's left
2461  // to itself (out_b).
2462  template <typename RegSetT> bool add(const RegSetT &RS) {
2463  // Double-duty the Filter: to maintain VRegs a set (and the join operation
2464  // a set union) just add everything being added here to the Filter as well.
2465  return Filter.filterAndAdd(RS, VRegs);
2466  }
2467  using const_iterator = decltype(VRegs)::const_iterator;
2468  const_iterator begin() const { return VRegs.begin(); }
2469  const_iterator end() const { return VRegs.end(); }
2470  size_t size() const { return VRegs.size(); }
2471 };
2472 } // namespace
2473 
2474 // Calculate the largest possible vregsPassed sets. These are the registers that
2475 // can pass through an MBB live, but may not be live every time. It is assumed
2476 // that all vregsPassed sets are empty before the call.
2477 void MachineVerifier::calcRegsPassed() {
2478  if (MF->empty())
2479  // ReversePostOrderTraversal doesn't handle empty functions.
2480  return;
2481 
2482  for (const MachineBasicBlock *MB :
2484  FilteringVRegSet VRegs;
2485  BBInfo &Info = MBBInfoMap[MB];
2486  assert(Info.reachable);
2487 
2488  VRegs.addToFilter(Info.regsKilled);
2489  VRegs.addToFilter(Info.regsLiveOut);
2490  for (const MachineBasicBlock *Pred : MB->predecessors()) {
2491  const BBInfo &PredInfo = MBBInfoMap[Pred];
2492  if (!PredInfo.reachable)
2493  continue;
2494 
2495  VRegs.add(PredInfo.regsLiveOut);
2496  VRegs.add(PredInfo.vregsPassed);
2497  }
2498  Info.vregsPassed.reserve(VRegs.size());
2499  Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2500  }
2501 }
2502 
2503 // Calculate the set of virtual registers that must be passed through each basic
2504 // block in order to satisfy the requirements of successor blocks. This is very
2505 // similar to calcRegsPassed, only backwards.
2506 void MachineVerifier::calcRegsRequired() {
2507  // First push live-in regs to predecessors' vregsRequired.
2509  for (const auto &MBB : *MF) {
2510  BBInfo &MInfo = MBBInfoMap[&MBB];
2511  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2512  BBInfo &PInfo = MBBInfoMap[Pred];
2513  if (PInfo.addRequired(MInfo.vregsLiveIn))
2514  todo.insert(Pred);
2515  }
2516 
2517  // Handle the PHI node.
2518  for (const MachineInstr &MI : MBB.phis()) {
2519  for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
2520  // Skip those Operands which are undef regs or not regs.
2521  if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
2522  continue;
2523 
2524  // Get register and predecessor for one PHI edge.
2525  Register Reg = MI.getOperand(i).getReg();
2526  const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
2527 
2528  BBInfo &PInfo = MBBInfoMap[Pred];
2529  if (PInfo.addRequired(Reg))
2530  todo.insert(Pred);
2531  }
2532  }
2533  }
2534 
2535  // Iteratively push vregsRequired to predecessors. This will converge to the
2536  // same final state regardless of DenseSet iteration order.
2537  while (!todo.empty()) {
2538  const MachineBasicBlock *MBB = *todo.begin();
2539  todo.erase(MBB);
2540  BBInfo &MInfo = MBBInfoMap[MBB];
2541  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2542  if (Pred == MBB)
2543  continue;
2544  BBInfo &SInfo = MBBInfoMap[Pred];
2545  if (SInfo.addRequired(MInfo.vregsRequired))
2546  todo.insert(Pred);
2547  }
2548  }
2549 }
2550 
2551 // Check PHI instructions at the beginning of MBB. It is assumed that
2552 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2553 void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2554  BBInfo &MInfo = MBBInfoMap[&MBB];
2555 
2557  for (const MachineInstr &Phi : MBB) {
2558  if (!Phi.isPHI())
2559  break;
2560  seen.clear();
2561 
2562  const MachineOperand &MODef = Phi.getOperand(0);
2563  if (!MODef.isReg() || !MODef.isDef()) {
2564  report("Expected first PHI operand to be a register def", &MODef, 0);
2565  continue;
2566  }
2567  if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2568  MODef.isEarlyClobber() || MODef.isDebug())
2569  report("Unexpected flag on PHI operand", &MODef, 0);
2570  Register DefReg = MODef.getReg();
2571  if (!Register::isVirtualRegister(DefReg))
2572  report("Expected first PHI operand to be a virtual register", &MODef, 0);
2573 
2574  for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2575  const MachineOperand &MO0 = Phi.getOperand(I);
2576  if (!MO0.isReg()) {
2577  report("Expected PHI operand to be a register", &MO0, I);
2578  continue;
2579  }
2580  if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2581  MO0.isDebug() || MO0.isTied())
2582  report("Unexpected flag on PHI operand", &MO0, I);
2583 
2584  const MachineOperand &MO1 = Phi.getOperand(I + 1);
2585  if (!MO1.isMBB()) {
2586  report("Expected PHI operand to be a basic block", &MO1, I + 1);
2587  continue;
2588  }
2589 
2590  const MachineBasicBlock &Pre = *MO1.getMBB();
2591  if (!Pre.isSuccessor(&MBB)) {
2592  report("PHI input is not a predecessor block", &MO1, I + 1);
2593  continue;
2594  }
2595 
2596  if (MInfo.reachable) {
2597  seen.insert(&Pre);
2598  BBInfo &PrInfo = MBBInfoMap[&Pre];
2599  if (!MO0.isUndef() && PrInfo.reachable &&
2600  !PrInfo.isLiveOut(MO0.getReg()))
2601  report("PHI operand is not live-out from predecessor", &MO0, I);
2602  }
2603  }
2604 
2605  // Did we see all predecessors?
2606  if (MInfo.reachable) {
2607  for (MachineBasicBlock *Pred : MBB.predecessors()) {
2608  if (!seen.count(Pred)) {
2609  report("Missing PHI operand", &Phi);
2610  errs() << printMBBReference(*Pred)
2611  << " is a predecessor according to the CFG.\n";
2612  }
2613  }
2614  }
2615  }
2616 }
2617 
2618 void MachineVerifier::visitMachineFunctionAfter() {
2619  calcRegsPassed();
2620 
2621  for (const MachineBasicBlock &MBB : *MF)
2622  checkPHIOps(MBB);
2623 
2624  // Now check liveness info if available
2625  calcRegsRequired();
2626 
2627  // Check for killed virtual registers that should be live out.
2628  for (const auto &MBB : *MF) {
2629  BBInfo &MInfo = MBBInfoMap[&MBB];
2630  for (Register VReg : MInfo.vregsRequired)
2631  if (MInfo.regsKilled.count(VReg)) {
2632  report("Virtual register killed in block, but needed live out.", &MBB);
2633  errs() << "Virtual register " << printReg(VReg)
2634  << " is used after the block.\n";
2635  }
2636  }
2637 
2638  if (!MF->empty()) {
2639  BBInfo &MInfo = MBBInfoMap[&MF->front()];
2640  for (Register VReg : MInfo.vregsRequired) {
2641  report("Virtual register defs don't dominate all uses.", MF);
2642  report_context_vreg(VReg);
2643  }
2644  }
2645 
2646  if (LiveVars)
2647  verifyLiveVariables();
2648  if (LiveInts)
2649  verifyLiveIntervals();
2650 
2651  // Check live-in list of each MBB. If a register is live into MBB, check
2652  // that the register is in regsLiveOut of each predecessor block. Since
2653  // this must come from a definition in the predecesssor or its live-in
2654  // list, this will catch a live-through case where the predecessor does not
2655  // have the register in its live-in list. This currently only checks
2656  // registers that have no aliases, are not allocatable and are not
2657  // reserved, which could mean a condition code register for instance.
2658  if (MRI->tracksLiveness())
2659  for (const auto &MBB : *MF)
2661  MCPhysReg LiveInReg = P.PhysReg;
2662  bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
2663  if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2664  continue;
2665  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2666  BBInfo &PInfo = MBBInfoMap[Pred];
2667  if (!PInfo.regsLiveOut.count(LiveInReg)) {
2668  report("Live in register not found to be live out from predecessor.",
2669  &MBB);
2670  errs() << TRI->getName(LiveInReg)
2671  << " not found to be live out from "
2672  << printMBBReference(*Pred) << "\n";
2673  }
2674  }
2675  }
2676 
2677  for (auto CSInfo : MF->getCallSitesInfo())
2678  if (!CSInfo.first->isCall())
2679  report("Call site info referencing instruction that is not call", MF);
2680 
2681  // If there's debug-info, check that we don't have any duplicate value
2682  // tracking numbers.
2683  if (MF->getFunction().getSubprogram()) {
2684  DenseSet<unsigned> SeenNumbers;
2685  for (auto &MBB : *MF) {
2686  for (auto &MI : MBB) {
2687  if (auto Num = MI.peekDebugInstrNum()) {
2688  auto Result = SeenNumbers.insert((unsigned)Num);
2689  if (!Result.second)
2690  report("Instruction has a duplicated value tracking number", &MI);
2691  }
2692  }
2693  }
2694  }
2695 }
2696 
2697 void MachineVerifier::verifyLiveVariables() {
2698  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2699  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2701  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2702  for (const auto &MBB : *MF) {
2703  BBInfo &MInfo = MBBInfoMap[&MBB];
2704 
2705  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2706  if (MInfo.vregsRequired.count(Reg)) {
2707  if (!VI.AliveBlocks.test(MBB.getNumber())) {
2708  report("LiveVariables: Block missing from AliveBlocks", &MBB);
2709  errs() << "Virtual register " << printReg(Reg)
2710  << " must be live through the block.\n";
2711  }
2712  } else {
2713  if (VI.AliveBlocks.test(MBB.getNumber())) {
2714  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2715  errs() << "Virtual register " << printReg(Reg)
2716  << " is not needed live through the block.\n";
2717  }
2718  }
2719  }
2720  }
2721 }
2722 
2723 void MachineVerifier::verifyLiveIntervals() {
2724  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2725  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2727 
2728  // Spilling and splitting may leave unused registers around. Skip them.
2729  if (MRI->reg_nodbg_empty(Reg))
2730  continue;
2731 
2732  if (!LiveInts->hasInterval(Reg)) {
2733  report("Missing live interval for virtual register", MF);
2734  errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2735  continue;
2736  }
2737 
2738  const LiveInterval &LI = LiveInts->getInterval(Reg);
2739  assert(Reg == LI.reg() && "Invalid reg to interval mapping");
2740  verifyLiveInterval(LI);
2741  }
2742 
2743  // Verify all the cached regunit intervals.
2744  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2745  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2746  verifyLiveRange(*LR, i);
2747 }
2748 
2749 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2750  const VNInfo *VNI, Register Reg,
2751  LaneBitmask LaneMask) {
2752  if (VNI->isUnused())
2753  return;
2754 
2755  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2756 
2757  if (!DefVNI) {
2758  report("Value not live at VNInfo def and not marked unused", MF);
2759  report_context(LR, Reg, LaneMask);
2760  report_context(*VNI);
2761  return;
2762  }
2763 
2764  if (DefVNI != VNI) {
2765  report("Live segment at def has different VNInfo", MF);
2766  report_context(LR, Reg, LaneMask);
2767  report_context(*VNI);
2768  return;
2769  }
2770 
2771  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2772  if (!MBB) {
2773  report("Invalid VNInfo definition index", MF);
2774  report_context(LR, Reg, LaneMask);
2775  report_context(*VNI);
2776  return;
2777  }
2778 
2779  if (VNI->isPHIDef()) {
2780  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2781  report("PHIDef VNInfo is not defined at MBB start", MBB);
2782  report_context(LR, Reg, LaneMask);
2783  report_context(*VNI);
2784  }
2785  return;
2786  }
2787 
2788  // Non-PHI def.
2789  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2790  if (!MI) {
2791  report("No instruction at VNInfo def index", MBB);
2792  report_context(LR, Reg, LaneMask);
2793  report_context(*VNI);
2794  return;
2795  }
2796 
2797  if (Reg != 0) {
2798  bool hasDef = false;
2799  bool isEarlyClobber = false;
2800  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2801  if (!MOI->isReg() || !MOI->isDef())
2802  continue;
2804  if (MOI->getReg() != Reg)
2805  continue;
2806  } else {
2807  if (!Register::isPhysicalRegister(MOI->getReg()) ||
2808  !TRI->hasRegUnit(MOI->getReg(), Reg))
2809  continue;
2810  }
2811  if (LaneMask.any() &&
2812  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2813  continue;
2814  hasDef = true;
2815  if (MOI->isEarlyClobber())
2816  isEarlyClobber = true;
2817  }
2818 
2819  if (!hasDef) {
2820  report("Defining instruction does not modify register", MI);
2821  report_context(LR, Reg, LaneMask);
2822  report_context(*VNI);
2823  }
2824 
2825  // Early clobber defs begin at USE slots, but other defs must begin at
2826  // DEF slots.
2827  if (isEarlyClobber) {
2828  if (!VNI->def.isEarlyClobber()) {
2829  report("Early clobber def must be at an early-clobber slot", MBB);
2830  report_context(LR, Reg, LaneMask);
2831  report_context(*VNI);
2832  }
2833  } else if (!VNI->def.isRegister()) {
2834  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2835  report_context(LR, Reg, LaneMask);
2836  report_context(*VNI);
2837  }
2838  }
2839 }
2840 
2841 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2843  Register Reg,
2844  LaneBitmask LaneMask) {
2845  const LiveRange::Segment &S = *I;
2846  const VNInfo *VNI = S.valno;
2847  assert(VNI && "Live segment has no valno");
2848 
2849  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2850  report("Foreign valno in live segment", MF);
2851  report_context(LR, Reg, LaneMask);
2852  report_context(S);
2853  report_context(*VNI);
2854  }
2855 
2856  if (VNI->isUnused()) {
2857  report("Live segment valno is marked unused", MF);
2858  report_context(LR, Reg, LaneMask);
2859  report_context(S);
2860  }
2861 
2862  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2863  if (!MBB) {
2864  report("Bad start of live segment, no basic block", MF);
2865  report_context(LR, Reg, LaneMask);
2866  report_context(S);
2867  return;
2868  }
2869  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2870  if (S.start != MBBStartIdx && S.start != VNI->def) {
2871  report("Live segment must begin at MBB entry or valno def", MBB);
2872  report_context(LR, Reg, LaneMask);
2873  report_context(S);
2874  }
2875 
2876  const MachineBasicBlock *EndMBB =
2877  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2878  if (!EndMBB) {
2879  report("Bad end of live segment, no basic block", MF);
2880  report_context(LR, Reg, LaneMask);
2881  report_context(S);
2882  return;
2883  }
2884 
2885  // No more checks for live-out segments.
2886  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2887  return;
2888 
2889  // RegUnit intervals are allowed dead phis.
2890  if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2891  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2892  return;
2893 
2894  // The live segment is ending inside EndMBB
2895  const MachineInstr *MI =
2896  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2897  if (!MI) {
2898  report("Live segment doesn't end at a valid instruction", EndMBB);
2899  report_context(LR, Reg, LaneMask);
2900  report_context(S);
2901  return;
2902  }
2903 
2904  // The block slot must refer to a basic block boundary.
2905  if (S.end.isBlock()) {
2906  report("Live segment ends at B slot of an instruction", EndMBB);
2907  report_context(LR, Reg, LaneMask);
2908  report_context(S);
2909  }
2910 
2911  if (S.end.isDead()) {
2912  // Segment ends on the dead slot.
2913  // That means there must be a dead def.
2914  if (!SlotIndex::isSameInstr(S.start, S.end)) {
2915  report("Live segment ending at dead slot spans instructions", EndMBB);
2916  report_context(LR, Reg, LaneMask);
2917  report_context(S);
2918  }
2919  }
2920 
2921  // A live segment can only end at an early-clobber slot if it is being
2922  // redefined by an early-clobber def.
2923  if (S.end.isEarlyClobber()) {
2924  if (I+1 == LR.end() || (I+1)->start != S.end) {
2925  report("Live segment ending at early clobber slot must be "
2926  "redefined by an EC def in the same instruction", EndMBB);
2927  report_context(LR, Reg, LaneMask);
2928  report_context(S);
2929  }
2930  }
2931 
2932  // The following checks only apply to virtual registers. Physreg liveness
2933  // is too weird to check.
2935  // A live segment can end with either a redefinition, a kill flag on a
2936  // use, or a dead flag on a def.
2937  bool hasRead = false;
2938  bool hasSubRegDef = false;
2939  bool hasDeadDef = false;
2940  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2941  if (!MOI->isReg() || MOI->getReg() != Reg)
2942  continue;
2943  unsigned Sub = MOI->getSubReg();
2944  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
2945  : LaneBitmask::getAll();
2946  if (MOI->isDef()) {
2947  if (Sub != 0) {
2948  hasSubRegDef = true;
2949  // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2950  // mask for subregister defs. Read-undef defs will be handled by
2951  // readsReg below.
2952  SLM = ~SLM;
2953  }
2954  if (MOI->isDead())
2955  hasDeadDef = true;
2956  }
2957  if (LaneMask.any() && (LaneMask & SLM).none())
2958  continue;
2959  if (MOI->readsReg())
2960  hasRead = true;
2961  }
2962  if (S.end.isDead()) {
2963  // Make sure that the corresponding machine operand for a "dead" live
2964  // range has the dead flag. We cannot perform this check for subregister
2965  // liveranges as partially dead values are allowed.
2966  if (LaneMask.none() && !hasDeadDef) {
2967  report("Instruction ending live segment on dead slot has no dead flag",
2968  MI);
2969  report_context(LR, Reg, LaneMask);
2970  report_context(S);
2971  }
2972  } else {
2973  if (!hasRead) {
2974  // When tracking subregister liveness, the main range must start new
2975  // values on partial register writes, even if there is no read.
2976  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
2977  !hasSubRegDef) {
2978  report("Instruction ending live segment doesn't read the register",
2979  MI);
2980  report_context(LR, Reg, LaneMask);
2981  report_context(S);
2982  }
2983  }
2984  }
2985  }
2986 
2987  // Now check all the basic blocks in this live segment.
2989  // Is this live segment the beginning of a non-PHIDef VN?
2990  if (S.start == VNI->def && !VNI->isPHIDef()) {
2991  // Not live-in to any blocks.
2992  if (MBB == EndMBB)
2993  return;
2994  // Skip this block.
2995  ++MFI;
2996  }
2997 
2999  if (LaneMask.any()) {
3000  LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3001  OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3002  }
3003 
3004  while (true) {
3005  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3006  // We don't know how to track physregs into a landing pad.
3007  if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
3008  if (&*MFI == EndMBB)
3009  break;
3010  ++MFI;
3011  continue;
3012  }
3013 
3014  // Is VNI a PHI-def in the current block?
3015  bool IsPHI = VNI->isPHIDef() &&
3016  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3017 
3018  // Check that VNI is live-out of all predecessors.
3019  for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3020  SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3021  // Predecessor of landing pad live-out on last call.
3022  if (MFI->isEHPad()) {
3023  for (auto I = Pred->rbegin(), E = Pred->rend(); I != E; ++I) {
3024  if (I->isCall()) {
3025  PEnd = Indexes->getInstructionIndex(*I).getBoundaryIndex();
3026  break;
3027  }
3028  }
3029  }
3030  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3031 
3032  // All predecessors must have a live-out value. However for a phi
3033  // instruction with subregister intervals
3034  // only one of the subregisters (not necessarily the current one) needs to
3035  // be defined.
3036  if (!PVNI && (LaneMask.none() || !IsPHI)) {
3037  if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3038  continue;
3039  report("Register not marked live out of predecessor", Pred);
3040  report_context(LR, Reg, LaneMask);
3041  report_context(*VNI);
3042  errs() << " live into " << printMBBReference(*MFI) << '@'
3043  << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3044  << PEnd << '\n';
3045  continue;
3046  }
3047 
3048  // Only PHI-defs can take different predecessor values.
3049  if (!IsPHI && PVNI != VNI) {
3050  report("Different value live out of predecessor", Pred);
3051  report_context(LR, Reg, LaneMask);
3052  errs() << "Valno #" << PVNI->id << " live out of "
3053  << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3054  << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3055  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3056  }
3057  }
3058  if (&*MFI == EndMBB)
3059  break;
3060  ++MFI;
3061  }
3062 }
3063 
3064 void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3065  LaneBitmask LaneMask) {
3066  for (const VNInfo *VNI : LR.valnos)
3067  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3068 
3069  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3070  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3071 }
3072 
3073 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3074  Register Reg = LI.reg();
3076  verifyLiveRange(LI, Reg);
3077 
3078  LaneBitmask Mask;
3080  for (const LiveInterval::SubRange &SR : LI.subranges()) {
3081  if ((Mask & SR.LaneMask).any()) {
3082  report("Lane masks of sub ranges overlap in live interval", MF);
3083  report_context(LI);
3084  }
3085  if ((SR.LaneMask & ~MaxMask).any()) {
3086  report("Subrange lanemask is invalid", MF);
3087  report_context(LI);
3088  }
3089  if (SR.empty()) {
3090  report("Subrange must not be empty", MF);
3091  report_context(SR, LI.reg(), SR.LaneMask);
3092  }
3093  Mask |= SR.LaneMask;
3094  verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3095  if (!LI.covers(SR)) {
3096  report("A Subrange is not covered by the main range", MF);
3097  report_context(LI);
3098  }
3099  }
3100 
3101  // Check the LI only has one connected component.
3102  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3103  unsigned NumComp = ConEQ.Classify(LI);
3104  if (NumComp > 1) {
3105  report("Multiple connected components in live interval", MF);
3106  report_context(LI);
3107  for (unsigned comp = 0; comp != NumComp; ++comp) {
3108  errs() << comp << ": valnos";
3109  for (const VNInfo *I : LI.valnos)
3110  if (comp == ConEQ.getEqClass(I))
3111  errs() << ' ' << I->id;
3112  errs() << '\n';
3113  }
3114  }
3115 }
3116 
3117 namespace {
3118 
3119  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3120  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3121  // value is zero.
3122  // We use a bool plus an integer to capture the stack state.
3123  struct StackStateOfBB {
3124  StackStateOfBB() = default;
3125  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3126  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3127  ExitIsSetup(ExitSetup) {}
3128 
3129  // Can be negative, which means we are setting up a frame.
3130  int EntryValue = 0;
3131  int ExitValue = 0;
3132  bool EntryIsSetup = false;
3133  bool ExitIsSetup = false;
3134  };
3135 
3136 } // end anonymous namespace
3137 
3138 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3139 /// by a FrameDestroy <n>, stack adjustments are identical on all
3140 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
3141 void MachineVerifier::verifyStackFrame() {
3142  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3143  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3144  if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3145  return;
3146 
3148  SPState.resize(MF->getNumBlockIDs());
3150 
3151  // Visit the MBBs in DFS order.
3152  for (df_ext_iterator<const MachineFunction *,
3154  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3155  DFI != DFE; ++DFI) {
3156  const MachineBasicBlock *MBB = *DFI;
3157 
3158  StackStateOfBB BBState;
3159  // Check the exit state of the DFS stack predecessor.
3160  if (DFI.getPathLength() >= 2) {
3161  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3162  assert(Reachable.count(StackPred) &&
3163  "DFS stack predecessor is already visited.\n");
3164  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3165  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3166  BBState.ExitValue = BBState.EntryValue;
3167  BBState.ExitIsSetup = BBState.EntryIsSetup;
3168  }
3169 
3170  // Update stack state by checking contents of MBB.
3171  for (const auto &I : *MBB) {
3172  if (I.getOpcode() == FrameSetupOpcode) {
3173  if (BBState.ExitIsSetup)
3174  report("FrameSetup is after another FrameSetup", &I);
3175  BBState.ExitValue -= TII->getFrameTotalSize(I);
3176  BBState.ExitIsSetup = true;
3177  }
3178 
3179  if (I.getOpcode() == FrameDestroyOpcode) {
3180  int Size = TII->getFrameTotalSize(I);
3181  if (!BBState.ExitIsSetup)
3182  report("FrameDestroy is not after a FrameSetup", &I);
3183  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3184  BBState.ExitValue;
3185  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3186  report("FrameDestroy <n> is after FrameSetup <m>", &I);
3187  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3188  << AbsSPAdj << ">.\n";
3189  }
3190  BBState.ExitValue += Size;
3191  BBState.ExitIsSetup = false;
3192  }
3193  }
3194  SPState[MBB->getNumber()] = BBState;
3195 
3196  // Make sure the exit state of any predecessor is consistent with the entry
3197  // state.
3198  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3199  if (Reachable.count(Pred) &&
3200  (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3201  SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3202  report("The exit stack state of a predecessor is inconsistent.", MBB);
3203  errs() << "Predecessor " << printMBBReference(*Pred)
3204  << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3205  << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3206  << printMBBReference(*MBB) << " has entry state ("
3207  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3208  }
3209  }
3210 
3211  // Make sure the entry state of any successor is consistent with the exit
3212  // state.
3213  for (const MachineBasicBlock *Succ : MBB->successors()) {
3214  if (Reachable.count(Succ) &&
3215  (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3216  SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3217  report("The entry stack state of a successor is inconsistent.", MBB);
3218  errs() << "Successor " << printMBBReference(*Succ)
3219  << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3220  << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3221  << printMBBReference(*MBB) << " has exit state ("
3222  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3223  }
3224  }
3225 
3226  // Make sure a basic block with return ends with zero stack adjustment.
3227  if (!MBB->empty() && MBB->back().isReturn()) {
3228  if (BBState.ExitIsSetup)
3229  report("A return block ends with a FrameSetup.", MBB);
3230  if (BBState.ExitValue)
3231  report("A return block ends with a nonzero stack adjustment.", MBB);
3232  }
3233  }
3234 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:611
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:775
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:344
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:299
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::LiveInterval::computeSubRangeUndefs
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
Definition: LiveInterval.cpp:976
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:221
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:165
llvm::MachineBasicBlock::pred_begin
pred_iterator pred_begin()
Definition: MachineBasicBlock.h:316
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
MachineInstr.h
MathExtras.h
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:384
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::LiveStacks::getInterval
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:64
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:266
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:214
llvm::SmallPtrSetImpl::erase
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:378
MCTargetOptions.h
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:213
llvm::LiveIntervals::isLiveInToMBB
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
Definition: LiveIntervals.h:245
llvm::ConstantInt::getBitWidth
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:136
MCInstrDesc.h
SetOperations.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:58
llvm::Function
Definition: Function.h:61
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:391
llvm::BitVector::clear
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:327
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:263
llvm::SlotIndex::getBoundaryIndex
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
Definition: SlotIndexes.h:248
llvm::set_union
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:22
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::LiveIntervals::isNotInMIMap
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
Definition: LiveIntervals.h:221
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:583
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:726
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:229
InlineAsm.h
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:359
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::LiveQueryResult::isDeadDef
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
llvm::LiveRange::Segment
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:132
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
INITIALIZE_PASS
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
Definition: MachineVerifier.cpp:301
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:241
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:168
DenseMap.h
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:412
llvm::AttributeList
Definition: Attributes.h:398
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1580
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
EHPersonalities.h
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:297
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:355
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::SmallPtrSet< const MachineBasicBlock *, 8 >
llvm::SlotIndex::isEarlyClobber
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:229
llvm::Intrinsic::getAttributes
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
llvm::SlotIndexes::getMBBEndIdx
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:476
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
STLExtras.h
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:248
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:331
llvm::LiveQueryResult
Result of a LiveRange query.
Definition: LiveInterval.h:90
llvm::detail::DenseSetImpl::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1225
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
p
the resulting code requires compare and branches when and if * p
Definition: README.txt:396
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:255
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
DepthFirstIterator.h
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:518
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MCRegisterInfo::subregs
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
Definition: MCRegisterInfo.h:309
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:197
llvm::LiveIntervals::print
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Definition: LiveIntervals.cpp:155
isLiveOut
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
Definition: SIOptimizeExecMasking.cpp:286
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:21
llvm::verifyMachineFunction
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
Definition: MachineVerifier.cpp:308
llvm::df_ext_begin
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:241
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:328
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::APFloatBase::getSizeInBits
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:226
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1547
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:816
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:632
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::LiveStacks::hasInterval
bool hasInterval(int Slot) const
Definition: LiveStacks.h:78
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:393
llvm::MachineFunctionProperties::Property::Selected
@ Selected
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::LiveVariables::VarInfo
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
llvm::LiveRange::begin
iterator begin()
Definition: LiveInterval.h:215
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:375
llvm::MCRegisterInfo::subregs_inclusive
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
Definition: MCRegisterInfo.h:316
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:236
llvm::LiveIntervals::getCachedRegUnit
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
Definition: LiveIntervals.h:406
llvm::LiveRange::covers
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
Definition: LiveInterval.cpp:494
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::set_subtract
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:62
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:334
llvm::Pass::getAnalysisIfAvailable
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Definition: PassAnalysisSupport.h:211
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:99
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:915
Twine.h
llvm::BitVector::size
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:151
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:630
llvm::MachineBasicBlock::isSuccessor
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Definition: MachineBasicBlock.cpp:908
llvm::LiveRange::const_iterator
Segments::const_iterator const_iterator
Definition: LiveInterval.h:213
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:57
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LaneBitmask::getNone
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:433
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:713
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:329
LiveVariables.h
DenseSet.h
TargetOpcodes.h
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
pass
modulo schedule Modulo Schedule test pass
Definition: ModuloSchedule.cpp:2126
llvm::LiveRange::valnos
VNInfoList valnos
Definition: LiveInterval.h:204
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:101
MachineInstrBundle.h
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:278
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:136
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:385
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::PrintLaneMask
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:606
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
BitVector.h
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:804
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:521
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
llvm::SlotIndex::isRegister
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:233
SmallPtrSet.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::BitVector
Definition: BitVector.h:74
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:61
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:321
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::MachineRegisterInfo::reservedRegsFrozen
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
Definition: MachineRegisterInfo.h:890
llvm::LiveQueryResult::valueIn
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
llvm::MachineFunctionAnalysisManager
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
Definition: MachinePassManager.h:39
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::initializeMachineVerifierPassPass
void initializeMachineVerifierPassPass(PassRegistry &)
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:426
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::Twine::str
std::string str() const
Return the twine contents as a std::string.
Definition: Twine.cpp:17
llvm::SlotIndexes::MBBIndexEnd
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:509
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:185
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:111
LiveIntervalCalc.h
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:227
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:622
BasicBlock.h
llvm::ClrHandlerType::Filter
@ Filter
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
VI
@ VI
Definition: SIInstrInfo.cpp:7542
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::LiveRange::getVNInfoBefore
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:421
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:466
llvm::MachineBasicBlock::pred_end
pred_iterator pred_end()
Definition: MachineBasicBlock.h:318
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:111
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
LiveIntervals.h
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::LiveIntervals::getMBBEndIdx
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Definition: LiveIntervals.h:241
llvm::VNInfo::id
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:743
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::MCOperandInfo::isGenericType
bool isGenericType() const
Definition: MCInstrDesc.h:116
llvm::SlotIndexes::MBBIndexBegin
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:504
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
llvm::LiveRange::getNumValNums
unsigned getNumValNums() const
Definition: LiveInterval.h:305
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:53
llvm::isScopedEHPersonality
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
Definition: EHPersonalities.h:80
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:59
MCRegisterInfo.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:123
llvm::SmallPtrSetImpl::begin
iterator begin() const
Definition: SmallPtrSet.h:402
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:127
llvm::createMachineVerifierPass
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1612
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:533
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:220
MachineFunctionPass.h
llvm::MachineFunctionProperties::Property::RegBankSelected
@ RegBankSelected
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:541
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:121
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1605
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:436
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:593
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:349
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:349
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:387
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:813
isStore
static bool isStore(int Opcode)
Definition: ARCInstrInfo.cpp:58
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:119
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:254
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::SmallPtrSetImpl::count
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:382
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::df_iterator_default_set
Definition: DepthFirstIterator.h:69
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1528
llvm::MachineOperand::isShuffleMask
bool isShuffleMask() const
Definition: MachineOperand.h:354
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
llvm::SmallPtrSetImplBase::clear
void clear()
Definition: SmallPtrSet.h:94
llvm::MachineBasicBlock::phis
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
Definition: MachineBasicBlock.h:296
llvm::ArrayRef< int >
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1056
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:526
isLoad
static bool isLoad(int Opcode)
Definition: ARCInstrInfo.cpp:53
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:272
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:352
uint32_t
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:1744
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
verify
ppc ctr loops verify
Definition: PPCCTRLoops.cpp:76
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:847
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineFunctionProperties::Property::TiedOpsRewritten
@ TiedOpsRewritten
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:409
llvm::df_ext_end
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:246
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:687
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:904
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallPtrSetImplBase::size
size_type size() const
Definition: SmallPtrSet.h:92
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::VNInfo::isPHIDef
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeCalc::isJointlyDominated
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
Definition: LiveRangeCalc.cpp:434
llvm::MCOperandInfo::getGenericTypeIndex
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:121
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:493
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
std
Definition: BitVector.h:838
llvm::MachineFunctionProperties::Property::NoPHIs
@ NoPHIs
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:458
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:274
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:618
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::RegisterBank::getName
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
llvm::LLT::getSizeInBytes
TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:163
llvm::RegisterBank::getSize
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
Casting.h
llvm::FixedStackPseudoSourceValue
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
Definition: PseudoSourceValue.h:94
Function.h
llvm::MachineFunction::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Definition: MachineFunction.cpp:545
llvm::SlotIndexes::MBBIndexIterator
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
Definition: SlotIndexes.h:487
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:660
StackMaps.h
llvm::LiveRange::getValNumInfo
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:309
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:290
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:446
LiveInterval.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:762
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:216
Instructions.h
PostOrderIterator.h
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:339
LiveStacks.h
RegisterBank.h
llvm::SmallPtrSetImplBase::empty
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:91
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:797
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::df_ext_iterator
Definition: DepthFirstIterator.h:235
llvm::LiveVariables::getVarInfo
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Definition: LiveVariables.cpp:84
LaneBitmask.h
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:431
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::VNInfo::isUnused
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:640
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
SlotIndexes.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:237
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
raw_ostream.h
llvm::MachineFunction::empty
bool empty() const
Definition: MachineFunction.h:815
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:210
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:838
llvm::ConnectedVNInfoEqClasses
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:992
InitializePasses.h
llvm::LiveStacks
Definition: LiveStacks.h:31
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:314
llvm::LiveQueryResult::isKill
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::LaneBitmask::getAll
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SrcOp
Definition: MachineIRBuilder.h:119
llvm::LiveRange::end
iterator end()
Definition: LiveInterval.h:216
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:255
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:213
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769