LLVM  16.0.0git
MachineVerifier.cpp
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1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled with the command-line option
20 // -verify-machineinstrs.
21 //===----------------------------------------------------------------------===//
22 
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/StringRef.h"
33 #include "llvm/ADT/Twine.h"
54 #include "llvm/CodeGen/StackMaps.h"
59 #include "llvm/IR/BasicBlock.h"
60 #include "llvm/IR/Constants.h"
61 #include "llvm/IR/Function.h"
62 #include "llvm/IR/InlineAsm.h"
63 #include "llvm/IR/Instructions.h"
64 #include "llvm/InitializePasses.h"
65 #include "llvm/MC/LaneBitmask.h"
66 #include "llvm/MC/MCAsmInfo.h"
67 #include "llvm/MC/MCDwarf.h"
68 #include "llvm/MC/MCInstrDesc.h"
69 #include "llvm/MC/MCRegisterInfo.h"
71 #include "llvm/Pass.h"
72 #include "llvm/Support/Casting.h"
76 #include "llvm/Support/ModRef.h"
79 #include <algorithm>
80 #include <cassert>
81 #include <cstddef>
82 #include <cstdint>
83 #include <iterator>
84 #include <string>
85 #include <utility>
86 
87 using namespace llvm;
88 
89 namespace {
90 
91  struct MachineVerifier {
92  MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
93 
94  unsigned verify(const MachineFunction &MF);
95 
96  Pass *const PASS;
97  const char *Banner;
98  const MachineFunction *MF;
99  const TargetMachine *TM;
100  const TargetInstrInfo *TII;
101  const TargetRegisterInfo *TRI;
102  const MachineRegisterInfo *MRI;
103  const RegisterBankInfo *RBI;
104 
105  unsigned foundErrors;
106 
107  // Avoid querying the MachineFunctionProperties for each operand.
108  bool isFunctionRegBankSelected;
109  bool isFunctionSelected;
110  bool isFunctionTracksDebugUserValues;
111 
112  using RegVector = SmallVector<Register, 16>;
113  using RegMaskVector = SmallVector<const uint32_t *, 4>;
114  using RegSet = DenseSet<Register>;
117 
118  const MachineInstr *FirstNonPHI;
119  const MachineInstr *FirstTerminator;
120  BlockSet FunctionBlocks;
121 
122  BitVector regsReserved;
123  RegSet regsLive;
124  RegVector regsDefined, regsDead, regsKilled;
125  RegMaskVector regMasks;
126 
127  SlotIndex lastIndex;
128 
129  // Add Reg and any sub-registers to RV
130  void addRegWithSubRegs(RegVector &RV, Register Reg) {
131  RV.push_back(Reg);
132  if (Reg.isPhysical())
133  append_range(RV, TRI->subregs(Reg.asMCReg()));
134  }
135 
136  struct BBInfo {
137  // Is this MBB reachable from the MF entry point?
138  bool reachable = false;
139 
140  // Vregs that must be live in because they are used without being
141  // defined. Map value is the user. vregsLiveIn doesn't include regs
142  // that only are used by PHI nodes.
143  RegMap vregsLiveIn;
144 
145  // Regs killed in MBB. They may be defined again, and will then be in both
146  // regsKilled and regsLiveOut.
147  RegSet regsKilled;
148 
149  // Regs defined in MBB and live out. Note that vregs passing through may
150  // be live out without being mentioned here.
151  RegSet regsLiveOut;
152 
153  // Vregs that pass through MBB untouched. This set is disjoint from
154  // regsKilled and regsLiveOut.
155  RegSet vregsPassed;
156 
157  // Vregs that must pass through MBB because they are needed by a successor
158  // block. This set is disjoint from regsLiveOut.
159  RegSet vregsRequired;
160 
161  // Set versions of block's predecessor and successor lists.
162  BlockSet Preds, Succs;
163 
164  BBInfo() = default;
165 
166  // Add register to vregsRequired if it belongs there. Return true if
167  // anything changed.
168  bool addRequired(Register Reg) {
169  if (!Reg.isVirtual())
170  return false;
171  if (regsLiveOut.count(Reg))
172  return false;
173  return vregsRequired.insert(Reg).second;
174  }
175 
176  // Same for a full set.
177  bool addRequired(const RegSet &RS) {
178  bool Changed = false;
179  for (Register Reg : RS)
180  Changed |= addRequired(Reg);
181  return Changed;
182  }
183 
184  // Same for a full map.
185  bool addRequired(const RegMap &RM) {
186  bool Changed = false;
187  for (const auto &I : RM)
188  Changed |= addRequired(I.first);
189  return Changed;
190  }
191 
192  // Live-out registers are either in regsLiveOut or vregsPassed.
193  bool isLiveOut(Register Reg) const {
194  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
195  }
196  };
197 
198  // Extra register info per MBB.
200 
201  bool isReserved(Register Reg) {
202  return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
203  }
204 
205  bool isAllocatable(Register Reg) const {
206  return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
207  !regsReserved.test(Reg.id());
208  }
209 
210  // Analysis information if available
211  LiveVariables *LiveVars;
212  LiveIntervals *LiveInts;
213  LiveStacks *LiveStks;
214  SlotIndexes *Indexes;
215 
216  void visitMachineFunctionBefore();
217  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
218  void visitMachineBundleBefore(const MachineInstr *MI);
219 
220  /// Verify that all of \p MI's virtual register operands are scalars.
221  /// \returns True if all virtual register operands are scalar. False
222  /// otherwise.
223  bool verifyAllRegOpsScalar(const MachineInstr &MI,
224  const MachineRegisterInfo &MRI);
225  bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
226  void verifyPreISelGenericInstruction(const MachineInstr *MI);
227  void visitMachineInstrBefore(const MachineInstr *MI);
228  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
229  void visitMachineBundleAfter(const MachineInstr *MI);
230  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
231  void visitMachineFunctionAfter();
232 
233  void report(const char *msg, const MachineFunction *MF);
234  void report(const char *msg, const MachineBasicBlock *MBB);
235  void report(const char *msg, const MachineInstr *MI);
236  void report(const char *msg, const MachineOperand *MO, unsigned MONum,
237  LLT MOVRegType = LLT{});
238  void report(const Twine &Msg, const MachineInstr *MI);
239 
240  void report_context(const LiveInterval &LI) const;
241  void report_context(const LiveRange &LR, Register VRegUnit,
242  LaneBitmask LaneMask) const;
243  void report_context(const LiveRange::Segment &S) const;
244  void report_context(const VNInfo &VNI) const;
245  void report_context(SlotIndex Pos) const;
246  void report_context(MCPhysReg PhysReg) const;
247  void report_context_liverange(const LiveRange &LR) const;
248  void report_context_lanemask(LaneBitmask LaneMask) const;
249  void report_context_vreg(Register VReg) const;
250  void report_context_vreg_regunit(Register VRegOrUnit) const;
251 
252  void verifyInlineAsm(const MachineInstr *MI);
253 
254  void checkLiveness(const MachineOperand *MO, unsigned MONum);
255  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
256  SlotIndex UseIdx, const LiveRange &LR,
257  Register VRegOrUnit,
258  LaneBitmask LaneMask = LaneBitmask::getNone());
259  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
260  SlotIndex DefIdx, const LiveRange &LR,
261  Register VRegOrUnit, bool SubRangeCheck = false,
262  LaneBitmask LaneMask = LaneBitmask::getNone());
263 
264  void markReachable(const MachineBasicBlock *MBB);
265  void calcRegsPassed();
266  void checkPHIOps(const MachineBasicBlock &MBB);
267 
268  void calcRegsRequired();
269  void verifyLiveVariables();
270  void verifyLiveIntervals();
271  void verifyLiveInterval(const LiveInterval&);
272  void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
273  LaneBitmask);
274  void verifyLiveRangeSegment(const LiveRange &,
276  LaneBitmask);
277  void verifyLiveRange(const LiveRange &, Register,
278  LaneBitmask LaneMask = LaneBitmask::getNone());
279 
280  void verifyStackFrame();
281 
282  void verifySlotIndexes() const;
283  void verifyProperties(const MachineFunction &MF);
284  };
285 
286  struct MachineVerifierPass : public MachineFunctionPass {
287  static char ID; // Pass ID, replacement for typeid
288 
289  const std::string Banner;
290 
291  MachineVerifierPass(std::string banner = std::string())
292  : MachineFunctionPass(ID), Banner(std::move(banner)) {
294  }
295 
296  void getAnalysisUsage(AnalysisUsage &AU) const override {
299  AU.setPreservesAll();
301  }
302 
303  bool runOnMachineFunction(MachineFunction &MF) override {
304  // Skip functions that have known verification problems.
305  // FIXME: Remove this mechanism when all problematic passes have been
306  // fixed.
307  if (MF.getProperties().hasProperty(
309  return false;
310 
311  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
312  if (FoundErrors)
313  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
314  return false;
315  }
316  };
317 
318 } // end anonymous namespace
319 
320 char MachineVerifierPass::ID = 0;
321 
322 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
323  "Verify generated machine code", false, false)
324 
326  return new MachineVerifierPass(Banner);
327 }
328 
330  const std::string &Banner,
331  const MachineFunction &MF) {
332  // TODO: Use MFAM after porting below analyses.
333  // LiveVariables *LiveVars;
334  // LiveIntervals *LiveInts;
335  // LiveStacks *LiveStks;
336  // SlotIndexes *Indexes;
337  unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
338  if (FoundErrors)
339  report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
340 }
341 
342 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
343  const {
344  MachineFunction &MF = const_cast<MachineFunction&>(*this);
345  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
346  if (AbortOnErrors && FoundErrors)
347  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
348  return FoundErrors == 0;
349 }
350 
351 void MachineVerifier::verifySlotIndexes() const {
352  if (Indexes == nullptr)
353  return;
354 
355  // Ensure the IdxMBB list is sorted by slot indexes.
356  SlotIndex Last;
358  E = Indexes->MBBIndexEnd(); I != E; ++I) {
359  assert(!Last.isValid() || I->first > Last);
360  Last = I->first;
361  }
362 }
363 
364 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
365  // If a pass has introduced virtual registers without clearing the
366  // NoVRegs property (or set it without allocating the vregs)
367  // then report an error.
368  if (MF.getProperties().hasProperty(
370  MRI->getNumVirtRegs())
371  report("Function has NoVRegs property but there are VReg operands", &MF);
372 }
373 
374 unsigned MachineVerifier::verify(const MachineFunction &MF) {
375  foundErrors = 0;
376 
377  this->MF = &MF;
378  TM = &MF.getTarget();
379  TII = MF.getSubtarget().getInstrInfo();
381  RBI = MF.getSubtarget().getRegBankInfo();
382  MRI = &MF.getRegInfo();
383 
384  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
386 
387  // If we're mid-GlobalISel and we already triggered the fallback path then
388  // it's expected that the MIR is somewhat broken but that's ok since we'll
389  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
390  if (isFunctionFailedISel)
391  return foundErrors;
392 
393  isFunctionRegBankSelected = MF.getProperties().hasProperty(
395  isFunctionSelected = MF.getProperties().hasProperty(
397  isFunctionTracksDebugUserValues = MF.getProperties().hasProperty(
399 
400  LiveVars = nullptr;
401  LiveInts = nullptr;
402  LiveStks = nullptr;
403  Indexes = nullptr;
404  if (PASS) {
405  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
406  // We don't want to verify LiveVariables if LiveIntervals is available.
407  if (!LiveInts)
408  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
409  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
410  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
411  }
412 
413  verifySlotIndexes();
414 
415  verifyProperties(MF);
416 
417  visitMachineFunctionBefore();
418  for (const MachineBasicBlock &MBB : MF) {
419  visitMachineBasicBlockBefore(&MBB);
420  // Keep track of the current bundle header.
421  const MachineInstr *CurBundle = nullptr;
422  // Do we expect the next instruction to be part of the same bundle?
423  bool InBundle = false;
424 
425  for (const MachineInstr &MI : MBB.instrs()) {
426  if (MI.getParent() != &MBB) {
427  report("Bad instruction parent pointer", &MBB);
428  errs() << "Instruction: " << MI;
429  continue;
430  }
431 
432  // Check for consistent bundle flags.
433  if (InBundle && !MI.isBundledWithPred())
434  report("Missing BundledPred flag, "
435  "BundledSucc was set on predecessor",
436  &MI);
437  if (!InBundle && MI.isBundledWithPred())
438  report("BundledPred flag is set, "
439  "but BundledSucc not set on predecessor",
440  &MI);
441 
442  // Is this a bundle header?
443  if (!MI.isInsideBundle()) {
444  if (CurBundle)
445  visitMachineBundleAfter(CurBundle);
446  CurBundle = &MI;
447  visitMachineBundleBefore(CurBundle);
448  } else if (!CurBundle)
449  report("No bundle header", &MI);
450  visitMachineInstrBefore(&MI);
451  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
452  const MachineOperand &Op = MI.getOperand(I);
453  if (Op.getParent() != &MI) {
454  // Make sure to use correct addOperand / removeOperand / ChangeTo
455  // functions when replacing operands of a MachineInstr.
456  report("Instruction has operand with wrong parent set", &MI);
457  }
458 
459  visitMachineOperand(&Op, I);
460  }
461 
462  // Was this the last bundled instruction?
463  InBundle = MI.isBundledWithSucc();
464  }
465  if (CurBundle)
466  visitMachineBundleAfter(CurBundle);
467  if (InBundle)
468  report("BundledSucc flag set on last instruction in block", &MBB.back());
469  visitMachineBasicBlockAfter(&MBB);
470  }
471  visitMachineFunctionAfter();
472 
473  // Clean up.
474  regsLive.clear();
475  regsDefined.clear();
476  regsDead.clear();
477  regsKilled.clear();
478  regMasks.clear();
479  MBBInfoMap.clear();
480 
481  return foundErrors;
482 }
483 
484 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
485  assert(MF);
486  errs() << '\n';
487  if (!foundErrors++) {
488  if (Banner)
489  errs() << "# " << Banner << '\n';
490  if (LiveInts != nullptr)
491  LiveInts->print(errs());
492  else
493  MF->print(errs(), Indexes);
494  }
495  errs() << "*** Bad machine code: " << msg << " ***\n"
496  << "- function: " << MF->getName() << "\n";
497 }
498 
499 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
500  assert(MBB);
501  report(msg, MBB->getParent());
502  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
503  << MBB->getName() << " (" << (const void *)MBB << ')';
504  if (Indexes)
505  errs() << " [" << Indexes->getMBBStartIdx(MBB)
506  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
507  errs() << '\n';
508 }
509 
510 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
511  assert(MI);
512  report(msg, MI->getParent());
513  errs() << "- instruction: ";
514  if (Indexes && Indexes->hasIndex(*MI))
515  errs() << Indexes->getInstructionIndex(*MI) << '\t';
516  MI->print(errs(), /*IsStandalone=*/true);
517 }
518 
519 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
520  unsigned MONum, LLT MOVRegType) {
521  assert(MO);
522  report(msg, MO->getParent());
523  errs() << "- operand " << MONum << ": ";
524  MO->print(errs(), MOVRegType, TRI);
525  errs() << "\n";
526 }
527 
528 void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
529  report(Msg.str().c_str(), MI);
530 }
531 
532 void MachineVerifier::report_context(SlotIndex Pos) const {
533  errs() << "- at: " << Pos << '\n';
534 }
535 
536 void MachineVerifier::report_context(const LiveInterval &LI) const {
537  errs() << "- interval: " << LI << '\n';
538 }
539 
540 void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
541  LaneBitmask LaneMask) const {
542  report_context_liverange(LR);
543  report_context_vreg_regunit(VRegUnit);
544  if (LaneMask.any())
545  report_context_lanemask(LaneMask);
546 }
547 
548 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
549  errs() << "- segment: " << S << '\n';
550 }
551 
552 void MachineVerifier::report_context(const VNInfo &VNI) const {
553  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
554 }
555 
556 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
557  errs() << "- liverange: " << LR << '\n';
558 }
559 
560 void MachineVerifier::report_context(MCPhysReg PReg) const {
561  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
562 }
563 
564 void MachineVerifier::report_context_vreg(Register VReg) const {
565  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
566 }
567 
568 void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
569  if (Register::isVirtualRegister(VRegOrUnit)) {
570  report_context_vreg(VRegOrUnit);
571  } else {
572  errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
573  }
574 }
575 
576 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
577  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
578 }
579 
580 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
581  BBInfo &MInfo = MBBInfoMap[MBB];
582  if (!MInfo.reachable) {
583  MInfo.reachable = true;
584  for (const MachineBasicBlock *Succ : MBB->successors())
585  markReachable(Succ);
586  }
587 }
588 
589 void MachineVerifier::visitMachineFunctionBefore() {
590  lastIndex = SlotIndex();
591  regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
592  : TRI->getReservedRegs(*MF);
593 
594  if (!MF->empty())
595  markReachable(&MF->front());
596 
597  // Build a set of the basic blocks in the function.
598  FunctionBlocks.clear();
599  for (const auto &MBB : *MF) {
600  FunctionBlocks.insert(&MBB);
601  BBInfo &MInfo = MBBInfoMap[&MBB];
602 
603  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
604  if (MInfo.Preds.size() != MBB.pred_size())
605  report("MBB has duplicate entries in its predecessor list.", &MBB);
606 
607  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
608  if (MInfo.Succs.size() != MBB.succ_size())
609  report("MBB has duplicate entries in its successor list.", &MBB);
610  }
611 
612  // Check that the register use lists are sane.
613  MRI->verifyUseLists();
614 
615  if (!MF->empty())
616  verifyStackFrame();
617 }
618 
619 void
620 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
621  FirstTerminator = nullptr;
622  FirstNonPHI = nullptr;
623 
624  if (!MF->getProperties().hasProperty(
626  // If this block has allocatable physical registers live-in, check that
627  // it is an entry block or landing pad.
628  for (const auto &LI : MBB->liveins()) {
629  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
630  MBB->getIterator() != MBB->getParent()->begin()) {
631  report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
632  report_context(LI.PhysReg);
633  }
634  }
635  }
636 
637  if (MBB->isIRBlockAddressTaken()) {
639  report("ir-block-address-taken is associated with basic block not used by "
640  "a blockaddress.",
641  MBB);
642  }
643 
644  // Count the number of landing pad successors.
646  for (const auto *succ : MBB->successors()) {
647  if (succ->isEHPad())
648  LandingPadSuccs.insert(succ);
649  if (!FunctionBlocks.count(succ))
650  report("MBB has successor that isn't part of the function.", MBB);
651  if (!MBBInfoMap[succ].Preds.count(MBB)) {
652  report("Inconsistent CFG", MBB);
653  errs() << "MBB is not in the predecessor list of the successor "
654  << printMBBReference(*succ) << ".\n";
655  }
656  }
657 
658  // Check the predecessor list.
659  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
660  if (!FunctionBlocks.count(Pred))
661  report("MBB has predecessor that isn't part of the function.", MBB);
662  if (!MBBInfoMap[Pred].Succs.count(MBB)) {
663  report("Inconsistent CFG", MBB);
664  errs() << "MBB is not in the successor list of the predecessor "
665  << printMBBReference(*Pred) << ".\n";
666  }
667  }
668 
669  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
670  const BasicBlock *BB = MBB->getBasicBlock();
671  const Function &F = MF->getFunction();
672  if (LandingPadSuccs.size() > 1 &&
673  !(AsmInfo &&
675  BB && isa<SwitchInst>(BB->getTerminator())) &&
676  !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
677  report("MBB has more than one landing pad successor", MBB);
678 
679  // Call analyzeBranch. If it succeeds, there several more conditions to check.
680  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
682  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
683  Cond)) {
684  // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
685  // check whether its answers match up with reality.
686  if (!TBB && !FBB) {
687  // Block falls through to its successor.
688  if (!MBB->empty() && MBB->back().isBarrier() &&
689  !TII->isPredicated(MBB->back())) {
690  report("MBB exits via unconditional fall-through but ends with a "
691  "barrier instruction!", MBB);
692  }
693  if (!Cond.empty()) {
694  report("MBB exits via unconditional fall-through but has a condition!",
695  MBB);
696  }
697  } else if (TBB && !FBB && Cond.empty()) {
698  // Block unconditionally branches somewhere.
699  if (MBB->empty()) {
700  report("MBB exits via unconditional branch but doesn't contain "
701  "any instructions!", MBB);
702  } else if (!MBB->back().isBarrier()) {
703  report("MBB exits via unconditional branch but doesn't end with a "
704  "barrier instruction!", MBB);
705  } else if (!MBB->back().isTerminator()) {
706  report("MBB exits via unconditional branch but the branch isn't a "
707  "terminator instruction!", MBB);
708  }
709  } else if (TBB && !FBB && !Cond.empty()) {
710  // Block conditionally branches somewhere, otherwise falls through.
711  if (MBB->empty()) {
712  report("MBB exits via conditional branch/fall-through but doesn't "
713  "contain any instructions!", MBB);
714  } else if (MBB->back().isBarrier()) {
715  report("MBB exits via conditional branch/fall-through but ends with a "
716  "barrier instruction!", MBB);
717  } else if (!MBB->back().isTerminator()) {
718  report("MBB exits via conditional branch/fall-through but the branch "
719  "isn't a terminator instruction!", MBB);
720  }
721  } else if (TBB && FBB) {
722  // Block conditionally branches somewhere, otherwise branches
723  // somewhere else.
724  if (MBB->empty()) {
725  report("MBB exits via conditional branch/branch but doesn't "
726  "contain any instructions!", MBB);
727  } else if (!MBB->back().isBarrier()) {
728  report("MBB exits via conditional branch/branch but doesn't end with a "
729  "barrier instruction!", MBB);
730  } else if (!MBB->back().isTerminator()) {
731  report("MBB exits via conditional branch/branch but the branch "
732  "isn't a terminator instruction!", MBB);
733  }
734  if (Cond.empty()) {
735  report("MBB exits via conditional branch/branch but there's no "
736  "condition!", MBB);
737  }
738  } else {
739  report("analyzeBranch returned invalid data!", MBB);
740  }
741 
742  // Now check that the successors match up with the answers reported by
743  // analyzeBranch.
744  if (TBB && !MBB->isSuccessor(TBB))
745  report("MBB exits via jump or conditional branch, but its target isn't a "
746  "CFG successor!",
747  MBB);
748  if (FBB && !MBB->isSuccessor(FBB))
749  report("MBB exits via conditional branch, but its target isn't a CFG "
750  "successor!",
751  MBB);
752 
753  // There might be a fallthrough to the next block if there's either no
754  // unconditional true branch, or if there's a condition, and one of the
755  // branches is missing.
756  bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
757 
758  // A conditional fallthrough must be an actual CFG successor, not
759  // unreachable. (Conversely, an unconditional fallthrough might not really
760  // be a successor, because the block might end in unreachable.)
761  if (!Cond.empty() && !FBB) {
763  if (MBBI == MF->end()) {
764  report("MBB conditionally falls through out of function!", MBB);
765  } else if (!MBB->isSuccessor(&*MBBI))
766  report("MBB exits via conditional branch/fall-through but the CFG "
767  "successors don't match the actual successors!",
768  MBB);
769  }
770 
771  // Verify that there aren't any extra un-accounted-for successors.
772  for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
773  // If this successor is one of the branch targets, it's okay.
774  if (SuccMBB == TBB || SuccMBB == FBB)
775  continue;
776  // If we might have a fallthrough, and the successor is the fallthrough
777  // block, that's also ok.
778  if (Fallthrough && SuccMBB == MBB->getNextNode())
779  continue;
780  // Also accept successors which are for exception-handling or might be
781  // inlineasm_br targets.
782  if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
783  continue;
784  report("MBB has unexpected successors which are not branch targets, "
785  "fallthrough, EHPads, or inlineasm_br targets.",
786  MBB);
787  }
788  }
789 
790  regsLive.clear();
791  if (MRI->tracksLiveness()) {
792  for (const auto &LI : MBB->liveins()) {
793  if (!Register::isPhysicalRegister(LI.PhysReg)) {
794  report("MBB live-in list contains non-physical register", MBB);
795  continue;
796  }
797  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
798  regsLive.insert(SubReg);
799  }
800  }
801 
802  const MachineFrameInfo &MFI = MF->getFrameInfo();
803  BitVector PR = MFI.getPristineRegs(*MF);
804  for (unsigned I : PR.set_bits()) {
805  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
806  regsLive.insert(SubReg);
807  }
808 
809  regsKilled.clear();
810  regsDefined.clear();
811 
812  if (Indexes)
813  lastIndex = Indexes->getMBBStartIdx(MBB);
814 }
815 
816 // This function gets called for all bundle headers, including normal
817 // stand-alone unbundled instructions.
818 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
819  if (Indexes && Indexes->hasIndex(*MI)) {
820  SlotIndex idx = Indexes->getInstructionIndex(*MI);
821  if (!(idx > lastIndex)) {
822  report("Instruction index out of order", MI);
823  errs() << "Last instruction was at " << lastIndex << '\n';
824  }
825  lastIndex = idx;
826  }
827 
828  // Ensure non-terminators don't follow terminators.
829  if (MI->isTerminator()) {
830  if (!FirstTerminator)
831  FirstTerminator = MI;
832  } else if (FirstTerminator) {
833  report("Non-terminator instruction after the first terminator", MI);
834  errs() << "First terminator was:\t" << *FirstTerminator;
835  }
836 }
837 
838 // The operands on an INLINEASM instruction must follow a template.
839 // Verify that the flag operands make sense.
840 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
841  // The first two operands on INLINEASM are the asm string and global flags.
842  if (MI->getNumOperands() < 2) {
843  report("Too few operands on inline asm", MI);
844  return;
845  }
846  if (!MI->getOperand(0).isSymbol())
847  report("Asm string must be an external symbol", MI);
848  if (!MI->getOperand(1).isImm())
849  report("Asm flags must be an immediate", MI);
850  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
851  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
852  // and Extra_IsConvergent = 32.
853  if (!isUInt<6>(MI->getOperand(1).getImm()))
854  report("Unknown asm flags", &MI->getOperand(1), 1);
855 
856  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
857 
858  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
859  unsigned NumOps;
860  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
861  const MachineOperand &MO = MI->getOperand(OpNo);
862  // There may be implicit ops after the fixed operands.
863  if (!MO.isImm())
864  break;
865  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
866  }
867 
868  if (OpNo > MI->getNumOperands())
869  report("Missing operands in last group", MI);
870 
871  // An optional MDNode follows the groups.
872  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
873  ++OpNo;
874 
875  // All trailing operands must be implicit registers.
876  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
877  const MachineOperand &MO = MI->getOperand(OpNo);
878  if (!MO.isReg() || !MO.isImplicit())
879  report("Expected implicit register after groups", &MO, OpNo);
880  }
881 
882  if (MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
883  const MachineBasicBlock *MBB = MI->getParent();
884 
885  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
886  i != e; ++i) {
887  const MachineOperand &MO = MI->getOperand(i);
888 
889  if (!MO.isMBB())
890  continue;
891 
892  // Check the successor & predecessor lists look ok, assume they are
893  // not. Find the indirect target without going through the successors.
894  const MachineBasicBlock *IndirectTargetMBB = MO.getMBB();
895  if (!IndirectTargetMBB) {
896  report("INLINEASM_BR indirect target does not exist", &MO, i);
897  break;
898  }
899 
900  if (!MBB->isSuccessor(IndirectTargetMBB))
901  report("INLINEASM_BR indirect target missing from successor list", &MO,
902  i);
903 
904  if (!IndirectTargetMBB->isPredecessor(MBB))
905  report("INLINEASM_BR indirect target predecessor list missing parent",
906  &MO, i);
907  }
908  }
909 }
910 
911 bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
912  const MachineRegisterInfo &MRI) {
913  if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
914  if (!Op.isReg())
915  return false;
916  const auto Reg = Op.getReg();
917  if (Reg.isPhysical())
918  return false;
919  return !MRI.getType(Reg).isScalar();
920  }))
921  return true;
922  report("All register operands must have scalar types", &MI);
923  return false;
924 }
925 
926 /// Check that types are consistent when two operands need to have the same
927 /// number of vector elements.
928 /// \return true if the types are valid.
929 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
930  const MachineInstr *MI) {
931  if (Ty0.isVector() != Ty1.isVector()) {
932  report("operand types must be all-vector or all-scalar", MI);
933  // Generally we try to report as many issues as possible at once, but in
934  // this case it's not clear what should we be comparing the size of the
935  // scalar with: the size of the whole vector or its lane. Instead of
936  // making an arbitrary choice and emitting not so helpful message, let's
937  // avoid the extra noise and stop here.
938  return false;
939  }
940 
941  if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
942  report("operand types must preserve number of vector elements", MI);
943  return false;
944  }
945 
946  return true;
947 }
948 
949 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
950  if (isFunctionSelected)
951  report("Unexpected generic instruction in a Selected function", MI);
952 
953  const MCInstrDesc &MCID = MI->getDesc();
954  unsigned NumOps = MI->getNumOperands();
955 
956  // Branches must reference a basic block if they are not indirect
957  if (MI->isBranch() && !MI->isIndirectBranch()) {
958  bool HasMBB = false;
959  for (const MachineOperand &Op : MI->operands()) {
960  if (Op.isMBB()) {
961  HasMBB = true;
962  break;
963  }
964  }
965 
966  if (!HasMBB) {
967  report("Branch instruction is missing a basic block operand or "
968  "isIndirectBranch property",
969  MI);
970  }
971  }
972 
973  // Check types.
975  for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
976  I != E; ++I) {
977  if (!MCID.OpInfo[I].isGenericType())
978  continue;
979  // Generic instructions specify type equality constraints between some of
980  // their operands. Make sure these are consistent.
981  size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
982  Types.resize(std::max(TypeIdx + 1, Types.size()));
983 
984  const MachineOperand *MO = &MI->getOperand(I);
985  if (!MO->isReg()) {
986  report("generic instruction must use register operands", MI);
987  continue;
988  }
989 
990  LLT OpTy = MRI->getType(MO->getReg());
991  // Don't report a type mismatch if there is no actual mismatch, only a
992  // type missing, to reduce noise:
993  if (OpTy.isValid()) {
994  // Only the first valid type for a type index will be printed: don't
995  // overwrite it later so it's always clear which type was expected:
996  if (!Types[TypeIdx].isValid())
997  Types[TypeIdx] = OpTy;
998  else if (Types[TypeIdx] != OpTy)
999  report("Type mismatch in generic instruction", MO, I, OpTy);
1000  } else {
1001  // Generic instructions must have types attached to their operands.
1002  report("Generic instruction is missing a virtual register type", MO, I);
1003  }
1004  }
1005 
1006  // Generic opcodes must not have physical register operands.
1007  for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
1008  const MachineOperand *MO = &MI->getOperand(I);
1009  if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
1010  report("Generic instruction cannot have physical register", MO, I);
1011  }
1012 
1013  // Avoid out of bounds in checks below. This was already reported earlier.
1014  if (MI->getNumOperands() < MCID.getNumOperands())
1015  return;
1016 
1018  if (!TII->verifyInstruction(*MI, ErrorInfo))
1019  report(ErrorInfo.data(), MI);
1020 
1021  // Verify properties of various specific instruction types
1022  unsigned Opc = MI->getOpcode();
1023  switch (Opc) {
1024  case TargetOpcode::G_ASSERT_SEXT:
1025  case TargetOpcode::G_ASSERT_ZEXT: {
1026  std::string OpcName =
1027  Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
1028  if (!MI->getOperand(2).isImm()) {
1029  report(Twine(OpcName, " expects an immediate operand #2"), MI);
1030  break;
1031  }
1032 
1033  Register Dst = MI->getOperand(0).getReg();
1034  Register Src = MI->getOperand(1).getReg();
1035  LLT SrcTy = MRI->getType(Src);
1036  int64_t Imm = MI->getOperand(2).getImm();
1037  if (Imm <= 0) {
1038  report(Twine(OpcName, " size must be >= 1"), MI);
1039  break;
1040  }
1041 
1042  if (Imm >= SrcTy.getScalarSizeInBits()) {
1043  report(Twine(OpcName, " size must be less than source bit width"), MI);
1044  break;
1045  }
1046 
1047  const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI);
1048  const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI);
1049 
1050  // Allow only the source bank to be set.
1051  if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1052  report(Twine(OpcName, " cannot change register bank"), MI);
1053  break;
1054  }
1055 
1056  // Don't allow a class change. Do allow member class->regbank.
1057  const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst);
1058  if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) {
1059  report(
1060  Twine(OpcName, " source and destination register classes must match"),
1061  MI);
1062  break;
1063  }
1064 
1065  break;
1066  }
1067 
1068  case TargetOpcode::G_CONSTANT:
1069  case TargetOpcode::G_FCONSTANT: {
1070  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1071  if (DstTy.isVector())
1072  report("Instruction cannot use a vector result type", MI);
1073 
1074  if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1075  if (!MI->getOperand(1).isCImm()) {
1076  report("G_CONSTANT operand must be cimm", MI);
1077  break;
1078  }
1079 
1080  const ConstantInt *CI = MI->getOperand(1).getCImm();
1081  if (CI->getBitWidth() != DstTy.getSizeInBits())
1082  report("inconsistent constant size", MI);
1083  } else {
1084  if (!MI->getOperand(1).isFPImm()) {
1085  report("G_FCONSTANT operand must be fpimm", MI);
1086  break;
1087  }
1088  const ConstantFP *CF = MI->getOperand(1).getFPImm();
1089 
1091  DstTy.getSizeInBits()) {
1092  report("inconsistent constant size", MI);
1093  }
1094  }
1095 
1096  break;
1097  }
1098  case TargetOpcode::G_LOAD:
1099  case TargetOpcode::G_STORE:
1100  case TargetOpcode::G_ZEXTLOAD:
1101  case TargetOpcode::G_SEXTLOAD: {
1102  LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1103  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1104  if (!PtrTy.isPointer())
1105  report("Generic memory instruction must access a pointer", MI);
1106 
1107  // Generic loads and stores must have a single MachineMemOperand
1108  // describing that access.
1109  if (!MI->hasOneMemOperand()) {
1110  report("Generic instruction accessing memory must have one mem operand",
1111  MI);
1112  } else {
1113  const MachineMemOperand &MMO = **MI->memoperands_begin();
1114  if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1115  MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1116  if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1117  report("Generic extload must have a narrower memory type", MI);
1118  } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1119  if (MMO.getSize() > ValTy.getSizeInBytes())
1120  report("load memory size cannot exceed result size", MI);
1121  } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1122  if (ValTy.getSizeInBytes() < MMO.getSize())
1123  report("store memory size cannot exceed value size", MI);
1124  }
1125 
1126  const AtomicOrdering Order = MMO.getSuccessOrdering();
1127  if (Opc == TargetOpcode::G_STORE) {
1128  if (Order == AtomicOrdering::Acquire ||
1130  report("atomic store cannot use acquire ordering", MI);
1131 
1132  } else {
1133  if (Order == AtomicOrdering::Release ||
1135  report("atomic load cannot use release ordering", MI);
1136  }
1137  }
1138 
1139  break;
1140  }
1141  case TargetOpcode::G_PHI: {
1142  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1143  if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1144  [this, &DstTy](const MachineOperand &MO) {
1145  if (!MO.isReg())
1146  return true;
1147  LLT Ty = MRI->getType(MO.getReg());
1148  if (!Ty.isValid() || (Ty != DstTy))
1149  return false;
1150  return true;
1151  }))
1152  report("Generic Instruction G_PHI has operands with incompatible/missing "
1153  "types",
1154  MI);
1155  break;
1156  }
1157  case TargetOpcode::G_BITCAST: {
1158  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1159  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1160  if (!DstTy.isValid() || !SrcTy.isValid())
1161  break;
1162 
1163  if (SrcTy.isPointer() != DstTy.isPointer())
1164  report("bitcast cannot convert between pointers and other types", MI);
1165 
1166  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1167  report("bitcast sizes must match", MI);
1168 
1169  if (SrcTy == DstTy)
1170  report("bitcast must change the type", MI);
1171 
1172  break;
1173  }
1174  case TargetOpcode::G_INTTOPTR:
1175  case TargetOpcode::G_PTRTOINT:
1176  case TargetOpcode::G_ADDRSPACE_CAST: {
1177  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1178  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1179  if (!DstTy.isValid() || !SrcTy.isValid())
1180  break;
1181 
1182  verifyVectorElementMatch(DstTy, SrcTy, MI);
1183 
1184  DstTy = DstTy.getScalarType();
1185  SrcTy = SrcTy.getScalarType();
1186 
1187  if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1188  if (!DstTy.isPointer())
1189  report("inttoptr result type must be a pointer", MI);
1190  if (SrcTy.isPointer())
1191  report("inttoptr source type must not be a pointer", MI);
1192  } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1193  if (!SrcTy.isPointer())
1194  report("ptrtoint source type must be a pointer", MI);
1195  if (DstTy.isPointer())
1196  report("ptrtoint result type must not be a pointer", MI);
1197  } else {
1198  assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1199  if (!SrcTy.isPointer() || !DstTy.isPointer())
1200  report("addrspacecast types must be pointers", MI);
1201  else {
1202  if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1203  report("addrspacecast must convert different address spaces", MI);
1204  }
1205  }
1206 
1207  break;
1208  }
1209  case TargetOpcode::G_PTR_ADD: {
1210  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1211  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1212  LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1213  if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1214  break;
1215 
1216  if (!PtrTy.getScalarType().isPointer())
1217  report("gep first operand must be a pointer", MI);
1218 
1219  if (OffsetTy.getScalarType().isPointer())
1220  report("gep offset operand must not be a pointer", MI);
1221 
1222  // TODO: Is the offset allowed to be a scalar with a vector?
1223  break;
1224  }
1225  case TargetOpcode::G_PTRMASK: {
1226  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1227  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1228  LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1229  if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1230  break;
1231 
1232  if (!DstTy.getScalarType().isPointer())
1233  report("ptrmask result type must be a pointer", MI);
1234 
1235  if (!MaskTy.getScalarType().isScalar())
1236  report("ptrmask mask type must be an integer", MI);
1237 
1238  verifyVectorElementMatch(DstTy, MaskTy, MI);
1239  break;
1240  }
1241  case TargetOpcode::G_SEXT:
1242  case TargetOpcode::G_ZEXT:
1243  case TargetOpcode::G_ANYEXT:
1244  case TargetOpcode::G_TRUNC:
1245  case TargetOpcode::G_FPEXT:
1246  case TargetOpcode::G_FPTRUNC: {
1247  // Number of operands and presense of types is already checked (and
1248  // reported in case of any issues), so no need to report them again. As
1249  // we're trying to report as many issues as possible at once, however, the
1250  // instructions aren't guaranteed to have the right number of operands or
1251  // types attached to them at this point
1252  assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1253  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1254  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1255  if (!DstTy.isValid() || !SrcTy.isValid())
1256  break;
1257 
1258  LLT DstElTy = DstTy.getScalarType();
1259  LLT SrcElTy = SrcTy.getScalarType();
1260  if (DstElTy.isPointer() || SrcElTy.isPointer())
1261  report("Generic extend/truncate can not operate on pointers", MI);
1262 
1263  verifyVectorElementMatch(DstTy, SrcTy, MI);
1264 
1265  unsigned DstSize = DstElTy.getSizeInBits();
1266  unsigned SrcSize = SrcElTy.getSizeInBits();
1267  switch (MI->getOpcode()) {
1268  default:
1269  if (DstSize <= SrcSize)
1270  report("Generic extend has destination type no larger than source", MI);
1271  break;
1272  case TargetOpcode::G_TRUNC:
1273  case TargetOpcode::G_FPTRUNC:
1274  if (DstSize >= SrcSize)
1275  report("Generic truncate has destination type no smaller than source",
1276  MI);
1277  break;
1278  }
1279  break;
1280  }
1281  case TargetOpcode::G_SELECT: {
1282  LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1283  LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1284  if (!SelTy.isValid() || !CondTy.isValid())
1285  break;
1286 
1287  // Scalar condition select on a vector is valid.
1288  if (CondTy.isVector())
1289  verifyVectorElementMatch(SelTy, CondTy, MI);
1290  break;
1291  }
1292  case TargetOpcode::G_MERGE_VALUES: {
1293  // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1294  // e.g. s2N = MERGE sN, sN
1295  // Merging multiple scalars into a vector is not allowed, should use
1296  // G_BUILD_VECTOR for that.
1297  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1298  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1299  if (DstTy.isVector() || SrcTy.isVector())
1300  report("G_MERGE_VALUES cannot operate on vectors", MI);
1301 
1302  const unsigned NumOps = MI->getNumOperands();
1303  if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1304  report("G_MERGE_VALUES result size is inconsistent", MI);
1305 
1306  for (unsigned I = 2; I != NumOps; ++I) {
1307  if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1308  report("G_MERGE_VALUES source types do not match", MI);
1309  }
1310 
1311  break;
1312  }
1313  case TargetOpcode::G_UNMERGE_VALUES: {
1314  unsigned NumDsts = MI->getNumOperands() - 1;
1315  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1316  for (unsigned i = 1; i < NumDsts; ++i) {
1317  if (MRI->getType(MI->getOperand(i).getReg()) != DstTy) {
1318  report("G_UNMERGE_VALUES destination types do not match", MI);
1319  break;
1320  }
1321  }
1322 
1323  LLT SrcTy = MRI->getType(MI->getOperand(NumDsts).getReg());
1324  if (DstTy.isVector()) {
1325  // This case is the converse of G_CONCAT_VECTORS.
1326  if (!SrcTy.isVector() || SrcTy.getScalarType() != DstTy.getScalarType() ||
1327  SrcTy.getNumElements() != NumDsts * DstTy.getNumElements())
1328  report("G_UNMERGE_VALUES source operand does not match vector "
1329  "destination operands",
1330  MI);
1331  } else if (SrcTy.isVector()) {
1332  // This case is the converse of G_BUILD_VECTOR, but relaxed to allow
1333  // mismatched types as long as the total size matches:
1334  // %0:_(s64), %1:_(s64) = G_UNMERGE_VALUES %2:_(<4 x s32>)
1335  if (SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
1336  report("G_UNMERGE_VALUES vector source operand does not match scalar "
1337  "destination operands",
1338  MI);
1339  } else {
1340  // This case is the converse of G_MERGE_VALUES.
1341  if (SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits()) {
1342  report("G_UNMERGE_VALUES scalar source operand does not match scalar "
1343  "destination operands",
1344  MI);
1345  }
1346  }
1347  break;
1348  }
1349  case TargetOpcode::G_BUILD_VECTOR: {
1350  // Source types must be scalars, dest type a vector. Total size of scalars
1351  // must match the dest vector size.
1352  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1353  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1354  if (!DstTy.isVector() || SrcEltTy.isVector()) {
1355  report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1356  break;
1357  }
1358 
1359  if (DstTy.getElementType() != SrcEltTy)
1360  report("G_BUILD_VECTOR result element type must match source type", MI);
1361 
1362  if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1363  report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1364 
1365  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1366  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1367  report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1368 
1369  break;
1370  }
1371  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1372  // Source types must be scalars, dest type a vector. Scalar types must be
1373  // larger than the dest vector elt type, as this is a truncating operation.
1374  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1375  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1376  if (!DstTy.isVector() || SrcEltTy.isVector())
1377  report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1378  MI);
1379  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1380  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1381  report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1382  MI);
1383  if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1384  report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1385  "dest elt type",
1386  MI);
1387  break;
1388  }
1389  case TargetOpcode::G_CONCAT_VECTORS: {
1390  // Source types should be vectors, and total size should match the dest
1391  // vector size.
1392  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1393  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1394  if (!DstTy.isVector() || !SrcTy.isVector())
1395  report("G_CONCAT_VECTOR requires vector source and destination operands",
1396  MI);
1397 
1398  if (MI->getNumOperands() < 3)
1399  report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1400 
1401  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1402  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1403  report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1404  if (DstTy.getNumElements() !=
1405  SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1406  report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1407  break;
1408  }
1409  case TargetOpcode::G_ICMP:
1410  case TargetOpcode::G_FCMP: {
1411  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1412  LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1413 
1414  if ((DstTy.isVector() != SrcTy.isVector()) ||
1415  (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1416  report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1417 
1418  break;
1419  }
1420  case TargetOpcode::G_EXTRACT: {
1421  const MachineOperand &SrcOp = MI->getOperand(1);
1422  if (!SrcOp.isReg()) {
1423  report("extract source must be a register", MI);
1424  break;
1425  }
1426 
1427  const MachineOperand &OffsetOp = MI->getOperand(2);
1428  if (!OffsetOp.isImm()) {
1429  report("extract offset must be a constant", MI);
1430  break;
1431  }
1432 
1433  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1434  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1435  if (SrcSize == DstSize)
1436  report("extract source must be larger than result", MI);
1437 
1438  if (DstSize + OffsetOp.getImm() > SrcSize)
1439  report("extract reads past end of register", MI);
1440  break;
1441  }
1442  case TargetOpcode::G_INSERT: {
1443  const MachineOperand &SrcOp = MI->getOperand(2);
1444  if (!SrcOp.isReg()) {
1445  report("insert source must be a register", MI);
1446  break;
1447  }
1448 
1449  const MachineOperand &OffsetOp = MI->getOperand(3);
1450  if (!OffsetOp.isImm()) {
1451  report("insert offset must be a constant", MI);
1452  break;
1453  }
1454 
1455  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1456  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1457 
1458  if (DstSize <= SrcSize)
1459  report("inserted size must be smaller than total register", MI);
1460 
1461  if (SrcSize + OffsetOp.getImm() > DstSize)
1462  report("insert writes past end of register", MI);
1463 
1464  break;
1465  }
1466  case TargetOpcode::G_JUMP_TABLE: {
1467  if (!MI->getOperand(1).isJTI())
1468  report("G_JUMP_TABLE source operand must be a jump table index", MI);
1469  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1470  if (!DstTy.isPointer())
1471  report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1472  break;
1473  }
1474  case TargetOpcode::G_BRJT: {
1475  if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1476  report("G_BRJT src operand 0 must be a pointer type", MI);
1477 
1478  if (!MI->getOperand(1).isJTI())
1479  report("G_BRJT src operand 1 must be a jump table index", MI);
1480 
1481  const auto &IdxOp = MI->getOperand(2);
1482  if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1483  report("G_BRJT src operand 2 must be a scalar reg type", MI);
1484  break;
1485  }
1486  case TargetOpcode::G_INTRINSIC:
1487  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1488  // TODO: Should verify number of def and use operands, but the current
1489  // interface requires passing in IR types for mangling.
1490  const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1491  if (!IntrIDOp.isIntrinsicID()) {
1492  report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1493  break;
1494  }
1495 
1496  bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1497  unsigned IntrID = IntrIDOp.getIntrinsicID();
1498  if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1500  MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
1501  bool DeclHasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
1502  if (NoSideEffects && DeclHasSideEffects) {
1503  report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1504  break;
1505  }
1506  if (!NoSideEffects && !DeclHasSideEffects) {
1507  report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1508  break;
1509  }
1510  }
1511 
1512  break;
1513  }
1514  case TargetOpcode::G_SEXT_INREG: {
1515  if (!MI->getOperand(2).isImm()) {
1516  report("G_SEXT_INREG expects an immediate operand #2", MI);
1517  break;
1518  }
1519 
1520  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1521  int64_t Imm = MI->getOperand(2).getImm();
1522  if (Imm <= 0)
1523  report("G_SEXT_INREG size must be >= 1", MI);
1524  if (Imm >= SrcTy.getScalarSizeInBits())
1525  report("G_SEXT_INREG size must be less than source bit width", MI);
1526  break;
1527  }
1528  case TargetOpcode::G_SHUFFLE_VECTOR: {
1529  const MachineOperand &MaskOp = MI->getOperand(3);
1530  if (!MaskOp.isShuffleMask()) {
1531  report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1532  break;
1533  }
1534 
1535  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1536  LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1537  LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1538 
1539  if (Src0Ty != Src1Ty)
1540  report("Source operands must be the same type", MI);
1541 
1542  if (Src0Ty.getScalarType() != DstTy.getScalarType())
1543  report("G_SHUFFLE_VECTOR cannot change element type", MI);
1544 
1545  // Don't check that all operands are vector because scalars are used in
1546  // place of 1 element vectors.
1547  int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1548  int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1549 
1550  ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1551 
1552  if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1553  report("Wrong result type for shufflemask", MI);
1554 
1555  for (int Idx : MaskIdxes) {
1556  if (Idx < 0)
1557  continue;
1558 
1559  if (Idx >= 2 * SrcNumElts)
1560  report("Out of bounds shuffle index", MI);
1561  }
1562 
1563  break;
1564  }
1565  case TargetOpcode::G_DYN_STACKALLOC: {
1566  const MachineOperand &DstOp = MI->getOperand(0);
1567  const MachineOperand &AllocOp = MI->getOperand(1);
1568  const MachineOperand &AlignOp = MI->getOperand(2);
1569 
1570  if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1571  report("dst operand 0 must be a pointer type", MI);
1572  break;
1573  }
1574 
1575  if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1576  report("src operand 1 must be a scalar reg type", MI);
1577  break;
1578  }
1579 
1580  if (!AlignOp.isImm()) {
1581  report("src operand 2 must be an immediate type", MI);
1582  break;
1583  }
1584  break;
1585  }
1586  case TargetOpcode::G_MEMCPY_INLINE:
1587  case TargetOpcode::G_MEMCPY:
1588  case TargetOpcode::G_MEMMOVE: {
1589  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1590  if (MMOs.size() != 2) {
1591  report("memcpy/memmove must have 2 memory operands", MI);
1592  break;
1593  }
1594 
1595  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1596  (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1597  report("wrong memory operand types", MI);
1598  break;
1599  }
1600 
1601  if (MMOs[0]->getSize() != MMOs[1]->getSize())
1602  report("inconsistent memory operand sizes", MI);
1603 
1604  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1605  LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1606 
1607  if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1608  report("memory instruction operand must be a pointer", MI);
1609  break;
1610  }
1611 
1612  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1613  report("inconsistent store address space", MI);
1614  if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1615  report("inconsistent load address space", MI);
1616 
1617  if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1618  if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1619  report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1620 
1621  break;
1622  }
1623  case TargetOpcode::G_BZERO:
1624  case TargetOpcode::G_MEMSET: {
1625  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1626  std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1627  if (MMOs.size() != 1) {
1628  report(Twine(Name, " must have 1 memory operand"), MI);
1629  break;
1630  }
1631 
1632  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1633  report(Twine(Name, " memory operand must be a store"), MI);
1634  break;
1635  }
1636 
1637  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1638  if (!DstPtrTy.isPointer()) {
1639  report(Twine(Name, " operand must be a pointer"), MI);
1640  break;
1641  }
1642 
1643  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1644  report("inconsistent " + Twine(Name, " address space"), MI);
1645 
1646  if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1647  (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1648  report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1649 
1650  break;
1651  }
1652  case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1653  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1654  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1655  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1656  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1657  if (!DstTy.isScalar())
1658  report("Vector reduction requires a scalar destination type", MI);
1659  if (!Src1Ty.isScalar())
1660  report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1661  if (!Src2Ty.isVector())
1662  report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1663  break;
1664  }
1665  case TargetOpcode::G_VECREDUCE_FADD:
1666  case TargetOpcode::G_VECREDUCE_FMUL:
1667  case TargetOpcode::G_VECREDUCE_FMAX:
1668  case TargetOpcode::G_VECREDUCE_FMIN:
1669  case TargetOpcode::G_VECREDUCE_ADD:
1670  case TargetOpcode::G_VECREDUCE_MUL:
1671  case TargetOpcode::G_VECREDUCE_AND:
1672  case TargetOpcode::G_VECREDUCE_OR:
1673  case TargetOpcode::G_VECREDUCE_XOR:
1674  case TargetOpcode::G_VECREDUCE_SMAX:
1675  case TargetOpcode::G_VECREDUCE_SMIN:
1676  case TargetOpcode::G_VECREDUCE_UMAX:
1677  case TargetOpcode::G_VECREDUCE_UMIN: {
1678  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1679  if (!DstTy.isScalar())
1680  report("Vector reduction requires a scalar destination type", MI);
1681  break;
1682  }
1683 
1684  case TargetOpcode::G_SBFX:
1685  case TargetOpcode::G_UBFX: {
1686  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1687  if (DstTy.isVector()) {
1688  report("Bitfield extraction is not supported on vectors", MI);
1689  break;
1690  }
1691  break;
1692  }
1693  case TargetOpcode::G_SHL:
1694  case TargetOpcode::G_LSHR:
1695  case TargetOpcode::G_ASHR:
1696  case TargetOpcode::G_ROTR:
1697  case TargetOpcode::G_ROTL: {
1698  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1699  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1700  if (Src1Ty.isVector() != Src2Ty.isVector()) {
1701  report("Shifts and rotates require operands to be either all scalars or "
1702  "all vectors",
1703  MI);
1704  break;
1705  }
1706  break;
1707  }
1708  case TargetOpcode::G_LLROUND:
1709  case TargetOpcode::G_LROUND: {
1710  verifyAllRegOpsScalar(*MI, *MRI);
1711  break;
1712  }
1713  case TargetOpcode::G_IS_FPCLASS: {
1714  LLT DestTy = MRI->getType(MI->getOperand(0).getReg());
1715  LLT DestEltTy = DestTy.getScalarType();
1716  if (!DestEltTy.isScalar()) {
1717  report("Destination must be a scalar or vector of scalars", MI);
1718  break;
1719  }
1720  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1721  LLT SrcEltTy = SrcTy.getScalarType();
1722  if (!SrcEltTy.isScalar()) {
1723  report("Source must be a scalar or vector of scalars", MI);
1724  break;
1725  }
1726  if (!verifyVectorElementMatch(DestTy, SrcTy, MI))
1727  break;
1728  const MachineOperand &TestMO = MI->getOperand(2);
1729  if (!TestMO.isImm()) {
1730  report("floating-point class set (operand 2) must be an immediate", MI);
1731  break;
1732  }
1733  int64_t Test = TestMO.getImm();
1734  if (Test < 0 || Test > fcAllFlags) {
1735  report("Incorrect floating-point class set (operand 2)", MI);
1736  break;
1737  }
1738  break;
1739  }
1740  case TargetOpcode::G_ASSERT_ALIGN: {
1741  if (MI->getOperand(2).getImm() < 1)
1742  report("alignment immediate must be >= 1", MI);
1743  break;
1744  }
1745  default:
1746  break;
1747  }
1748 }
1749 
1750 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1751  const MCInstrDesc &MCID = MI->getDesc();
1752  if (MI->getNumOperands() < MCID.getNumOperands()) {
1753  report("Too few operands", MI);
1754  errs() << MCID.getNumOperands() << " operands expected, but "
1755  << MI->getNumOperands() << " given.\n";
1756  }
1757 
1758  if (MI->isPHI()) {
1759  if (MF->getProperties().hasProperty(
1761  report("Found PHI instruction with NoPHIs property set", MI);
1762 
1763  if (FirstNonPHI)
1764  report("Found PHI instruction after non-PHI", MI);
1765  } else if (FirstNonPHI == nullptr)
1766  FirstNonPHI = MI;
1767 
1768  // Check the tied operands.
1769  if (MI->isInlineAsm())
1770  verifyInlineAsm(MI);
1771 
1772  // Check that unspillable terminators define a reg and have at most one use.
1773  if (TII->isUnspillableTerminator(MI)) {
1774  if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
1775  report("Unspillable Terminator does not define a reg", MI);
1776  Register Def = MI->getOperand(0).getReg();
1777  if (Def.isVirtual() &&
1778  !MF->getProperties().hasProperty(
1780  std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
1781  report("Unspillable Terminator expected to have at most one use!", MI);
1782  }
1783 
1784  // A fully-formed DBG_VALUE must have a location. Ignore partially formed
1785  // DBG_VALUEs: these are convenient to use in tests, but should never get
1786  // generated.
1787  if (MI->isDebugValue() && MI->getNumOperands() == 4)
1788  if (!MI->getDebugLoc())
1789  report("Missing DebugLoc for debug instruction", MI);
1790 
1791  // Meta instructions should never be the subject of debug value tracking,
1792  // they don't create a value in the output program at all.
1793  if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
1794  report("Metadata instruction should not have a value tracking number", MI);
1795 
1796  // Check the MachineMemOperands for basic consistency.
1797  for (MachineMemOperand *Op : MI->memoperands()) {
1798  if (Op->isLoad() && !MI->mayLoad())
1799  report("Missing mayLoad flag", MI);
1800  if (Op->isStore() && !MI->mayStore())
1801  report("Missing mayStore flag", MI);
1802  }
1803 
1804  // Debug values must not have a slot index.
1805  // Other instructions must have one, unless they are inside a bundle.
1806  if (LiveInts) {
1807  bool mapped = !LiveInts->isNotInMIMap(*MI);
1808  if (MI->isDebugOrPseudoInstr()) {
1809  if (mapped)
1810  report("Debug instruction has a slot index", MI);
1811  } else if (MI->isInsideBundle()) {
1812  if (mapped)
1813  report("Instruction inside bundle has a slot index", MI);
1814  } else {
1815  if (!mapped)
1816  report("Missing slot index", MI);
1817  }
1818  }
1819 
1820  unsigned Opc = MCID.getOpcode();
1822  verifyPreISelGenericInstruction(MI);
1823  return;
1824  }
1825 
1827  if (!TII->verifyInstruction(*MI, ErrorInfo))
1828  report(ErrorInfo.data(), MI);
1829 
1830  // Verify properties of various specific instruction types
1831  switch (MI->getOpcode()) {
1832  case TargetOpcode::COPY: {
1833  const MachineOperand &DstOp = MI->getOperand(0);
1834  const MachineOperand &SrcOp = MI->getOperand(1);
1835  const Register SrcReg = SrcOp.getReg();
1836  const Register DstReg = DstOp.getReg();
1837 
1838  LLT DstTy = MRI->getType(DstReg);
1839  LLT SrcTy = MRI->getType(SrcReg);
1840  if (SrcTy.isValid() && DstTy.isValid()) {
1841  // If both types are valid, check that the types are the same.
1842  if (SrcTy != DstTy) {
1843  report("Copy Instruction is illegal with mismatching types", MI);
1844  errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1845  }
1846 
1847  break;
1848  }
1849 
1850  if (!SrcTy.isValid() && !DstTy.isValid())
1851  break;
1852 
1853  // If we have only one valid type, this is likely a copy between a virtual
1854  // and physical register.
1855  unsigned SrcSize = 0;
1856  unsigned DstSize = 0;
1857  if (SrcReg.isPhysical() && DstTy.isValid()) {
1858  const TargetRegisterClass *SrcRC =
1859  TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1860  if (SrcRC)
1861  SrcSize = TRI->getRegSizeInBits(*SrcRC);
1862  }
1863 
1864  if (SrcSize == 0)
1865  SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
1866 
1867  if (DstReg.isPhysical() && SrcTy.isValid()) {
1868  const TargetRegisterClass *DstRC =
1869  TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1870  if (DstRC)
1871  DstSize = TRI->getRegSizeInBits(*DstRC);
1872  }
1873 
1874  if (DstSize == 0)
1875  DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
1876 
1877  if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1878  if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1879  report("Copy Instruction is illegal with mismatching sizes", MI);
1880  errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1881  << "\n";
1882  }
1883  }
1884  break;
1885  }
1886  case TargetOpcode::STATEPOINT: {
1887  StatepointOpers SO(MI);
1888  if (!MI->getOperand(SO.getIDPos()).isImm() ||
1889  !MI->getOperand(SO.getNBytesPos()).isImm() ||
1890  !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1891  report("meta operands to STATEPOINT not constant!", MI);
1892  break;
1893  }
1894 
1895  auto VerifyStackMapConstant = [&](unsigned Offset) {
1896  if (Offset >= MI->getNumOperands()) {
1897  report("stack map constant to STATEPOINT is out of range!", MI);
1898  return;
1899  }
1900  if (!MI->getOperand(Offset - 1).isImm() ||
1901  MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
1902  !MI->getOperand(Offset).isImm())
1903  report("stack map constant to STATEPOINT not well formed!", MI);
1904  };
1905  VerifyStackMapConstant(SO.getCCIdx());
1906  VerifyStackMapConstant(SO.getFlagsIdx());
1907  VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1908  VerifyStackMapConstant(SO.getNumGCPtrIdx());
1909  VerifyStackMapConstant(SO.getNumAllocaIdx());
1910  VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1911 
1912  // Verify that all explicit statepoint defs are tied to gc operands as
1913  // they are expected to be a relocation of gc operands.
1914  unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1915  unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1916  for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
1917  unsigned UseOpIdx;
1918  if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
1919  report("STATEPOINT defs expected to be tied", MI);
1920  break;
1921  }
1922  if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1923  report("STATEPOINT def tied to non-gc operand", MI);
1924  break;
1925  }
1926  }
1927 
1928  // TODO: verify we have properly encoded deopt arguments
1929  } break;
1930  case TargetOpcode::INSERT_SUBREG: {
1931  unsigned InsertedSize;
1932  if (unsigned SubIdx = MI->getOperand(2).getSubReg())
1933  InsertedSize = TRI->getSubRegIdxSize(SubIdx);
1934  else
1935  InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
1936  unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
1937  if (SubRegSize < InsertedSize) {
1938  report("INSERT_SUBREG expected inserted value to have equal or lesser "
1939  "size than the subreg it was inserted into", MI);
1940  break;
1941  }
1942  } break;
1943  case TargetOpcode::REG_SEQUENCE: {
1944  unsigned NumOps = MI->getNumOperands();
1945  if (!(NumOps & 1)) {
1946  report("Invalid number of operands for REG_SEQUENCE", MI);
1947  break;
1948  }
1949 
1950  for (unsigned I = 1; I != NumOps; I += 2) {
1951  const MachineOperand &RegOp = MI->getOperand(I);
1952  const MachineOperand &SubRegOp = MI->getOperand(I + 1);
1953 
1954  if (!RegOp.isReg())
1955  report("Invalid register operand for REG_SEQUENCE", &RegOp, I);
1956 
1957  if (!SubRegOp.isImm() || SubRegOp.getImm() == 0 ||
1958  SubRegOp.getImm() >= TRI->getNumSubRegIndices()) {
1959  report("Invalid subregister index operand for REG_SEQUENCE",
1960  &SubRegOp, I + 1);
1961  }
1962  }
1963 
1964  Register DstReg = MI->getOperand(0).getReg();
1965  if (DstReg.isPhysical())
1966  report("REG_SEQUENCE does not support physical register results", MI);
1967 
1968  if (MI->getOperand(0).getSubReg())
1969  report("Invalid subreg result for REG_SEQUENCE", MI);
1970 
1971  break;
1972  }
1973  }
1974 }
1975 
1976 void
1977 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1978  const MachineInstr *MI = MO->getParent();
1979  const MCInstrDesc &MCID = MI->getDesc();
1980  unsigned NumDefs = MCID.getNumDefs();
1981  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1982  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1983 
1984  // The first MCID.NumDefs operands must be explicit register defines
1985  if (MONum < NumDefs) {
1986  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1987  if (!MO->isReg())
1988  report("Explicit definition must be a register", MO, MONum);
1989  else if (!MO->isDef() && !MCOI.isOptionalDef())
1990  report("Explicit definition marked as use", MO, MONum);
1991  else if (MO->isImplicit())
1992  report("Explicit definition marked as implicit", MO, MONum);
1993  } else if (MONum < MCID.getNumOperands()) {
1994  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1995  // Don't check if it's the last operand in a variadic instruction. See,
1996  // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
1997  bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
1998  if (!IsOptional) {
1999  if (MO->isReg()) {
2000  if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
2001  report("Explicit operand marked as def", MO, MONum);
2002  if (MO->isImplicit())
2003  report("Explicit operand marked as implicit", MO, MONum);
2004  }
2005 
2006  // Check that an instruction has register operands only as expected.
2007  if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
2008  !MO->isReg() && !MO->isFI())
2009  report("Expected a register operand.", MO, MONum);
2010  if (MO->isReg()) {
2011  if (MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
2012  (MCOI.OperandType == MCOI::OPERAND_PCREL &&
2013  !TII->isPCRelRegisterOperandLegal(*MO)))
2014  report("Expected a non-register operand.", MO, MONum);
2015  }
2016  }
2017 
2018  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
2019  if (TiedTo != -1) {
2020  if (!MO->isReg())
2021  report("Tied use must be a register", MO, MONum);
2022  else if (!MO->isTied())
2023  report("Operand should be tied", MO, MONum);
2024  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
2025  report("Tied def doesn't match MCInstrDesc", MO, MONum);
2026  else if (Register::isPhysicalRegister(MO->getReg())) {
2027  const MachineOperand &MOTied = MI->getOperand(TiedTo);
2028  if (!MOTied.isReg())
2029  report("Tied counterpart must be a register", &MOTied, TiedTo);
2030  else if (Register::isPhysicalRegister(MOTied.getReg()) &&
2031  MO->getReg() != MOTied.getReg())
2032  report("Tied physical registers must match.", &MOTied, TiedTo);
2033  }
2034  } else if (MO->isReg() && MO->isTied())
2035  report("Explicit operand should not be tied", MO, MONum);
2036  } else {
2037  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
2038  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
2039  report("Extra explicit operand on non-variadic instruction", MO, MONum);
2040  }
2041 
2042  switch (MO->getType()) {
2044  // Verify debug flag on debug instructions. Check this first because reg0
2045  // indicates an undefined debug value.
2046  if (MI->isDebugInstr() && MO->isUse()) {
2047  if (!MO->isDebug())
2048  report("Register operand must be marked debug", MO, MONum);
2049  } else if (MO->isDebug()) {
2050  report("Register operand must not be marked debug", MO, MONum);
2051  }
2052 
2053  const Register Reg = MO->getReg();
2054  if (!Reg)
2055  return;
2056  if (MRI->tracksLiveness() && !MI->isDebugInstr())
2057  checkLiveness(MO, MONum);
2058 
2059  if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
2060  MO->getReg().isVirtual()) // TODO: Apply to physregs too
2061  report("Undef virtual register def operands require a subregister", MO, MONum);
2062 
2063  // Verify the consistency of tied operands.
2064  if (MO->isTied()) {
2065  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
2066  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
2067  if (!OtherMO.isReg())
2068  report("Must be tied to a register", MO, MONum);
2069  if (!OtherMO.isTied())
2070  report("Missing tie flags on tied operand", MO, MONum);
2071  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
2072  report("Inconsistent tie links", MO, MONum);
2073  if (MONum < MCID.getNumDefs()) {
2074  if (OtherIdx < MCID.getNumOperands()) {
2075  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
2076  report("Explicit def tied to explicit use without tie constraint",
2077  MO, MONum);
2078  } else {
2079  if (!OtherMO.isImplicit())
2080  report("Explicit def should be tied to implicit use", MO, MONum);
2081  }
2082  }
2083  }
2084 
2085  // Verify two-address constraints after the twoaddressinstruction pass.
2086  // Both twoaddressinstruction pass and phi-node-elimination pass call
2087  // MRI->leaveSSA() to set MF as NoSSA, we should do the verification after
2088  // twoaddressinstruction pass not after phi-node-elimination pass. So we
2089  // shouldn't use the NoSSA as the condition, we should based on
2090  // TiedOpsRewritten property to verify two-address constraints, this
2091  // property will be set in twoaddressinstruction pass.
2092  unsigned DefIdx;
2093  if (MF->getProperties().hasProperty(
2095  MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2096  Reg != MI->getOperand(DefIdx).getReg())
2097  report("Two-address instruction operands must be identical", MO, MONum);
2098 
2099  // Check register classes.
2100  unsigned SubIdx = MO->getSubReg();
2101 
2103  if (SubIdx) {
2104  report("Illegal subregister index for physical register", MO, MONum);
2105  return;
2106  }
2107  if (MONum < MCID.getNumOperands()) {
2108  if (const TargetRegisterClass *DRC =
2109  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2110  if (!DRC->contains(Reg)) {
2111  report("Illegal physical register for instruction", MO, MONum);
2112  errs() << printReg(Reg, TRI) << " is not a "
2113  << TRI->getRegClassName(DRC) << " register.\n";
2114  }
2115  }
2116  }
2117  if (MO->isRenamable()) {
2118  if (MRI->isReserved(Reg)) {
2119  report("isRenamable set on reserved register", MO, MONum);
2120  return;
2121  }
2122  }
2123  } else {
2124  // Virtual register.
2126  if (!RC) {
2127  // This is a generic virtual register.
2128 
2129  // Do not allow undef uses for generic virtual registers. This ensures
2130  // getVRegDef can never fail and return null on a generic register.
2131  //
2132  // FIXME: This restriction should probably be broadened to all SSA
2133  // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
2134  // run on the SSA function just before phi elimination.
2135  if (MO->isUndef())
2136  report("Generic virtual register use cannot be undef", MO, MONum);
2137 
2138  // Debug value instruction is permitted to use undefined vregs.
2139  // This is a performance measure to skip the overhead of immediately
2140  // pruning unused debug operands. The final undef substitution occurs
2141  // when debug values are allocated in LDVImpl::handleDebugValue, so
2142  // these verifications always apply after this pass.
2143  if (isFunctionTracksDebugUserValues || !MO->isUse() ||
2144  !MI->isDebugValue() || !MRI->def_empty(Reg)) {
2145  // If we're post-Select, we can't have gvregs anymore.
2146  if (isFunctionSelected) {
2147  report("Generic virtual register invalid in a Selected function",
2148  MO, MONum);
2149  return;
2150  }
2151 
2152  // The gvreg must have a type and it must not have a SubIdx.
2153  LLT Ty = MRI->getType(Reg);
2154  if (!Ty.isValid()) {
2155  report("Generic virtual register must have a valid type", MO,
2156  MONum);
2157  return;
2158  }
2159 
2160  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
2161 
2162  // If we're post-RegBankSelect, the gvreg must have a bank.
2163  if (!RegBank && isFunctionRegBankSelected) {
2164  report("Generic virtual register must have a bank in a "
2165  "RegBankSelected function",
2166  MO, MONum);
2167  return;
2168  }
2169 
2170  // Make sure the register fits into its register bank if any.
2171  if (RegBank && Ty.isValid() &&
2172  RegBank->getSize() < Ty.getSizeInBits()) {
2173  report("Register bank is too small for virtual register", MO,
2174  MONum);
2175  errs() << "Register bank " << RegBank->getName() << " too small("
2176  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
2177  << "-bits\n";
2178  return;
2179  }
2180  }
2181 
2182  if (SubIdx) {
2183  report("Generic virtual register does not allow subregister index", MO,
2184  MONum);
2185  return;
2186  }
2187 
2188  // If this is a target specific instruction and this operand
2189  // has register class constraint, the virtual register must
2190  // comply to it.
2191  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
2192  MONum < MCID.getNumOperands() &&
2193  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2194  report("Virtual register does not match instruction constraint", MO,
2195  MONum);
2196  errs() << "Expect register class "
2197  << TRI->getRegClassName(
2198  TII->getRegClass(MCID, MONum, TRI, *MF))
2199  << " but got nothing\n";
2200  return;
2201  }
2202 
2203  break;
2204  }
2205  if (SubIdx) {
2206  const TargetRegisterClass *SRC =
2207  TRI->getSubClassWithSubReg(RC, SubIdx);
2208  if (!SRC) {
2209  report("Invalid subregister index for virtual register", MO, MONum);
2210  errs() << "Register class " << TRI->getRegClassName(RC)
2211  << " does not support subreg index " << SubIdx << "\n";
2212  return;
2213  }
2214  if (RC != SRC) {
2215  report("Invalid register class for subregister index", MO, MONum);
2216  errs() << "Register class " << TRI->getRegClassName(RC)
2217  << " does not fully support subreg index " << SubIdx << "\n";
2218  return;
2219  }
2220  }
2221  if (MONum < MCID.getNumOperands()) {
2222  if (const TargetRegisterClass *DRC =
2223  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2224  if (SubIdx) {
2225  const TargetRegisterClass *SuperRC =
2226  TRI->getLargestLegalSuperClass(RC, *MF);
2227  if (!SuperRC) {
2228  report("No largest legal super class exists.", MO, MONum);
2229  return;
2230  }
2231  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2232  if (!DRC) {
2233  report("No matching super-reg register class.", MO, MONum);
2234  return;
2235  }
2236  }
2237  if (!RC->hasSuperClassEq(DRC)) {
2238  report("Illegal virtual register for instruction", MO, MONum);
2239  errs() << "Expected a " << TRI->getRegClassName(DRC)
2240  << " register, but got a " << TRI->getRegClassName(RC)
2241  << " register\n";
2242  }
2243  }
2244  }
2245  }
2246  break;
2247  }
2248 
2250  regMasks.push_back(MO->getRegMask());
2251  break;
2252 
2254  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2255  report("PHI operand is not in the CFG", MO, MONum);
2256  break;
2257 
2259  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2260  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2261  int FI = MO->getIndex();
2262  LiveInterval &LI = LiveStks->getInterval(FI);
2263  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2264 
2265  bool stores = MI->mayStore();
2266  bool loads = MI->mayLoad();
2267  // For a memory-to-memory move, we need to check if the frame
2268  // index is used for storing or loading, by inspecting the
2269  // memory operands.
2270  if (stores && loads) {
2271  for (auto *MMO : MI->memoperands()) {
2272  const PseudoSourceValue *PSV = MMO->getPseudoValue();
2273  if (PSV == nullptr) continue;
2275  dyn_cast<FixedStackPseudoSourceValue>(PSV);
2276  if (Value == nullptr) continue;
2277  if (Value->getFrameIndex() != FI) continue;
2278 
2279  if (MMO->isStore())
2280  loads = false;
2281  else
2282  stores = false;
2283  break;
2284  }
2285  if (loads == stores)
2286  report("Missing fixed stack memoperand.", MI);
2287  }
2288  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2289  report("Instruction loads from dead spill slot", MO, MONum);
2290  errs() << "Live stack: " << LI << '\n';
2291  }
2292  if (stores && !LI.liveAt(Idx.getRegSlot())) {
2293  report("Instruction stores to dead spill slot", MO, MONum);
2294  errs() << "Live stack: " << LI << '\n';
2295  }
2296  }
2297  break;
2298 
2300  if (MO->getCFIIndex() >= MF->getFrameInstructions().size())
2301  report("CFI instruction has invalid index", MO, MONum);
2302  break;
2303 
2304  default:
2305  break;
2306  }
2307 }
2308 
2309 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2310  unsigned MONum, SlotIndex UseIdx,
2311  const LiveRange &LR,
2312  Register VRegOrUnit,
2313  LaneBitmask LaneMask) {
2314  LiveQueryResult LRQ = LR.Query(UseIdx);
2315  // Check if we have a segment at the use, note however that we only need one
2316  // live subregister range, the others may be dead.
2317  if (!LRQ.valueIn() && LaneMask.none()) {
2318  report("No live segment at use", MO, MONum);
2319  report_context_liverange(LR);
2320  report_context_vreg_regunit(VRegOrUnit);
2321  report_context(UseIdx);
2322  }
2323  if (MO->isKill() && !LRQ.isKill()) {
2324  report("Live range continues after kill flag", MO, MONum);
2325  report_context_liverange(LR);
2326  report_context_vreg_regunit(VRegOrUnit);
2327  if (LaneMask.any())
2328  report_context_lanemask(LaneMask);
2329  report_context(UseIdx);
2330  }
2331 }
2332 
2333 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2334  unsigned MONum, SlotIndex DefIdx,
2335  const LiveRange &LR,
2336  Register VRegOrUnit,
2337  bool SubRangeCheck,
2338  LaneBitmask LaneMask) {
2339  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2340  // The LR can correspond to the whole reg and its def slot is not obliged
2341  // to be the same as the MO' def slot. E.g. when we check here "normal"
2342  // subreg MO but there is other EC subreg MO in the same instruction so the
2343  // whole reg has EC def slot and differs from the currently checked MO' def
2344  // slot. For example:
2345  // %0 [16e,32r:0) 0@16e L..3 [16e,32r:0) 0@16e L..C [16r,32r:0) 0@16r
2346  // Check that there is an early-clobber def of the same superregister
2347  // somewhere is performed in visitMachineFunctionAfter()
2348  if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) ||
2349  !SlotIndex::isSameInstr(VNI->def, DefIdx) ||
2350  (VNI->def != DefIdx &&
2351  (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) {
2352  report("Inconsistent valno->def", MO, MONum);
2353  report_context_liverange(LR);
2354  report_context_vreg_regunit(VRegOrUnit);
2355  if (LaneMask.any())
2356  report_context_lanemask(LaneMask);
2357  report_context(*VNI);
2358  report_context(DefIdx);
2359  }
2360  } else {
2361  report("No live segment at def", MO, MONum);
2362  report_context_liverange(LR);
2363  report_context_vreg_regunit(VRegOrUnit);
2364  if (LaneMask.any())
2365  report_context_lanemask(LaneMask);
2366  report_context(DefIdx);
2367  }
2368  // Check that, if the dead def flag is present, LiveInts agree.
2369  if (MO->isDead()) {
2370  LiveQueryResult LRQ = LR.Query(DefIdx);
2371  if (!LRQ.isDeadDef()) {
2372  assert(Register::isVirtualRegister(VRegOrUnit) &&
2373  "Expecting a virtual register.");
2374  // A dead subreg def only tells us that the specific subreg is dead. There
2375  // could be other non-dead defs of other subregs, or we could have other
2376  // parts of the register being live through the instruction. So unless we
2377  // are checking liveness for a subrange it is ok for the live range to
2378  // continue, given that we have a dead def of a subregister.
2379  if (SubRangeCheck || MO->getSubReg() == 0) {
2380  report("Live range continues after dead def flag", MO, MONum);
2381  report_context_liverange(LR);
2382  report_context_vreg_regunit(VRegOrUnit);
2383  if (LaneMask.any())
2384  report_context_lanemask(LaneMask);
2385  }
2386  }
2387  }
2388 }
2389 
2390 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2391  const MachineInstr *MI = MO->getParent();
2392  const Register Reg = MO->getReg();
2393  const unsigned SubRegIdx = MO->getSubReg();
2394 
2395  const LiveInterval *LI = nullptr;
2396  if (LiveInts && Reg.isVirtual()) {
2397  if (LiveInts->hasInterval(Reg)) {
2398  LI = &LiveInts->getInterval(Reg);
2399  if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
2401  report("Live interval for subreg operand has no subranges", MO, MONum);
2402  } else {
2403  report("Virtual register has no live interval", MO, MONum);
2404  }
2405  }
2406 
2407  // Both use and def operands can read a register.
2408  if (MO->readsReg()) {
2409  if (MO->isKill())
2410  addRegWithSubRegs(regsKilled, Reg);
2411 
2412  // Check that LiveVars knows this kill (unless we are inside a bundle, in
2413  // which case we have already checked that LiveVars knows any kills on the
2414  // bundle header instead).
2415  if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2416  !MI->isBundledWithPred()) {
2417  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2418  if (!is_contained(VI.Kills, MI))
2419  report("Kill missing from LiveVariables", MO, MONum);
2420  }
2421 
2422  // Check LiveInts liveness and kill.
2423  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2424  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
2425  // Check the cached regunit intervals.
2426  if (Reg.isPhysical() && !isReserved(Reg)) {
2427  for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
2428  ++Units) {
2429  if (MRI->isReservedRegUnit(*Units))
2430  continue;
2431  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
2432  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2433  }
2434  }
2435 
2436  if (Reg.isVirtual()) {
2437  // This is a virtual register interval.
2438  checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2439 
2440  if (LI->hasSubRanges() && !MO->isDef()) {
2441  LaneBitmask MOMask = SubRegIdx != 0
2442  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2444  LaneBitmask LiveInMask;
2445  for (const LiveInterval::SubRange &SR : LI->subranges()) {
2446  if ((MOMask & SR.LaneMask).none())
2447  continue;
2448  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2449  LiveQueryResult LRQ = SR.Query(UseIdx);
2450  if (LRQ.valueIn())
2451  LiveInMask |= SR.LaneMask;
2452  }
2453  // At least parts of the register has to be live at the use.
2454  if ((LiveInMask & MOMask).none()) {
2455  report("No live subrange at use", MO, MONum);
2456  report_context(*LI);
2457  report_context(UseIdx);
2458  }
2459  }
2460  }
2461  }
2462 
2463  // Use of a dead register.
2464  if (!regsLive.count(Reg)) {
2465  if (Reg.isPhysical()) {
2466  // Reserved registers may be used even when 'dead'.
2467  bool Bad = !isReserved(Reg);
2468  // We are fine if just any subregister has a defined value.
2469  if (Bad) {
2470 
2471  for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2472  if (regsLive.count(SubReg)) {
2473  Bad = false;
2474  break;
2475  }
2476  }
2477  }
2478  // If there is an additional implicit-use of a super register we stop
2479  // here. By definition we are fine if the super register is not
2480  // (completely) dead, if the complete super register is dead we will
2481  // get a report for its operand.
2482  if (Bad) {
2483  for (const MachineOperand &MOP : MI->uses()) {
2484  if (!MOP.isReg() || !MOP.isImplicit())
2485  continue;
2486 
2487  if (!MOP.getReg().isPhysical())
2488  continue;
2489 
2490  if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2491  Bad = false;
2492  }
2493  }
2494  if (Bad)
2495  report("Using an undefined physical register", MO, MONum);
2496  } else if (MRI->def_empty(Reg)) {
2497  report("Reading virtual register without a def", MO, MONum);
2498  } else {
2499  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2500  // We don't know which virtual registers are live in, so only complain
2501  // if vreg was killed in this MBB. Otherwise keep track of vregs that
2502  // must be live in. PHI instructions are handled separately.
2503  if (MInfo.regsKilled.count(Reg))
2504  report("Using a killed virtual register", MO, MONum);
2505  else if (!MI->isPHI())
2506  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2507  }
2508  }
2509  }
2510 
2511  if (MO->isDef()) {
2512  // Register defined.
2513  // TODO: verify that earlyclobber ops are not used.
2514  if (MO->isDead())
2515  addRegWithSubRegs(regsDead, Reg);
2516  else
2517  addRegWithSubRegs(regsDefined, Reg);
2518 
2519  // Verify SSA form.
2520  if (MRI->isSSA() && Reg.isVirtual() &&
2521  std::next(MRI->def_begin(Reg)) != MRI->def_end())
2522  report("Multiple virtual register defs in SSA form", MO, MONum);
2523 
2524  // Check LiveInts for a live segment, but only for virtual registers.
2525  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2526  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2527  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2528 
2529  if (Reg.isVirtual()) {
2530  checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2531 
2532  if (LI->hasSubRanges()) {
2533  LaneBitmask MOMask = SubRegIdx != 0
2534  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2536  for (const LiveInterval::SubRange &SR : LI->subranges()) {
2537  if ((SR.LaneMask & MOMask).none())
2538  continue;
2539  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2540  }
2541  }
2542  }
2543  }
2544  }
2545 }
2546 
2547 // This function gets called after visiting all instructions in a bundle. The
2548 // argument points to the bundle header.
2549 // Normal stand-alone instructions are also considered 'bundles', and this
2550 // function is called for all of them.
2551 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2552  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2553  set_union(MInfo.regsKilled, regsKilled);
2554  set_subtract(regsLive, regsKilled); regsKilled.clear();
2555  // Kill any masked registers.
2556  while (!regMasks.empty()) {
2557  const uint32_t *Mask = regMasks.pop_back_val();
2558  for (Register Reg : regsLive)
2559  if (Reg.isPhysical() &&
2561  regsDead.push_back(Reg);
2562  }
2563  set_subtract(regsLive, regsDead); regsDead.clear();
2564  set_union(regsLive, regsDefined); regsDefined.clear();
2565 }
2566 
2567 void
2568 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2569  MBBInfoMap[MBB].regsLiveOut = regsLive;
2570  regsLive.clear();
2571 
2572  if (Indexes) {
2573  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2574  if (!(stop > lastIndex)) {
2575  report("Block ends before last instruction index", MBB);
2576  errs() << "Block ends at " << stop
2577  << " last instruction was at " << lastIndex << '\n';
2578  }
2579  lastIndex = stop;
2580  }
2581 }
2582 
2583 namespace {
2584 // This implements a set of registers that serves as a filter: can filter other
2585 // sets by passing through elements not in the filter and blocking those that
2586 // are. Any filter implicitly includes the full set of physical registers upon
2587 // creation, thus filtering them all out. The filter itself as a set only grows,
2588 // and needs to be as efficient as possible.
2589 struct VRegFilter {
2590  // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2591  // no duplicates. Both virtual and physical registers are fine.
2592  template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2593  SmallVector<Register, 0> VRegsBuffer;
2594  filterAndAdd(FromRegSet, VRegsBuffer);
2595  }
2596  // Filter \p FromRegSet through the filter and append passed elements into \p
2597  // ToVRegs. All elements appended are then added to the filter itself.
2598  // \returns true if anything changed.
2599  template <typename RegSetT>
2600  bool filterAndAdd(const RegSetT &FromRegSet,
2601  SmallVectorImpl<Register> &ToVRegs) {
2602  unsigned SparseUniverse = Sparse.size();
2603  unsigned NewSparseUniverse = SparseUniverse;
2604  unsigned NewDenseSize = Dense.size();
2605  size_t Begin = ToVRegs.size();
2606  for (Register Reg : FromRegSet) {
2607  if (!Reg.isVirtual())
2608  continue;
2609  unsigned Index = Register::virtReg2Index(Reg);
2610  if (Index < SparseUniverseMax) {
2611  if (Index < SparseUniverse && Sparse.test(Index))
2612  continue;
2613  NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2614  } else {
2615  if (Dense.count(Reg))
2616  continue;
2617  ++NewDenseSize;
2618  }
2619  ToVRegs.push_back(Reg);
2620  }
2621  size_t End = ToVRegs.size();
2622  if (Begin == End)
2623  return false;
2624  // Reserving space in sets once performs better than doing so continuously
2625  // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2626  // tuned all the way down) and double iteration (the second one is over a
2627  // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2628  Sparse.resize(NewSparseUniverse);
2629  Dense.reserve(NewDenseSize);
2630  for (unsigned I = Begin; I < End; ++I) {
2631  Register Reg = ToVRegs[I];
2632  unsigned Index = Register::virtReg2Index(Reg);
2633  if (Index < SparseUniverseMax)
2634  Sparse.set(Index);
2635  else
2636  Dense.insert(Reg);
2637  }
2638  return true;
2639  }
2640 
2641 private:
2642  static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2643  // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2644  // are tracked by Dense. The only purpose of the threashold and the Dense set
2645  // is to have a reasonably growing memory usage in pathological cases (large
2646  // number of very sparse VRegFilter instances live at the same time). In
2647  // practice even in the worst-by-execution time cases having all elements
2648  // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2649  // space efficient than if tracked by Dense. The threashold is set to keep the
2650  // worst-case memory usage within 2x of figures determined empirically for
2651  // "all Dense" scenario in such worst-by-execution-time cases.
2652  BitVector Sparse;
2654 };
2655 
2656 // Implements both a transfer function and a (binary, in-place) join operator
2657 // for a dataflow over register sets with set union join and filtering transfer
2658 // (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2659 // Maintains out_b as its state, allowing for O(n) iteration over it at any
2660 // time, where n is the size of the set (as opposed to O(U) where U is the
2661 // universe). filter_b implicitly contains all physical registers at all times.
2662 class FilteringVRegSet {
2663  VRegFilter Filter;
2665 
2666 public:
2667  // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2668  // Both virtual and physical registers are fine.
2669  template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2670  Filter.add(RS);
2671  }
2672  // Passes \p RS through the filter_b (transfer function) and adds what's left
2673  // to itself (out_b).
2674  template <typename RegSetT> bool add(const RegSetT &RS) {
2675  // Double-duty the Filter: to maintain VRegs a set (and the join operation
2676  // a set union) just add everything being added here to the Filter as well.
2677  return Filter.filterAndAdd(RS, VRegs);
2678  }
2679  using const_iterator = decltype(VRegs)::const_iterator;
2680  const_iterator begin() const { return VRegs.begin(); }
2681  const_iterator end() const { return VRegs.end(); }
2682  size_t size() const { return VRegs.size(); }
2683 };
2684 } // namespace
2685 
2686 // Calculate the largest possible vregsPassed sets. These are the registers that
2687 // can pass through an MBB live, but may not be live every time. It is assumed
2688 // that all vregsPassed sets are empty before the call.
2689 void MachineVerifier::calcRegsPassed() {
2690  if (MF->empty())
2691  // ReversePostOrderTraversal doesn't handle empty functions.
2692  return;
2693 
2694  for (const MachineBasicBlock *MB :
2696  FilteringVRegSet VRegs;
2697  BBInfo &Info = MBBInfoMap[MB];
2698  assert(Info.reachable);
2699 
2700  VRegs.addToFilter(Info.regsKilled);
2701  VRegs.addToFilter(Info.regsLiveOut);
2702  for (const MachineBasicBlock *Pred : MB->predecessors()) {
2703  const BBInfo &PredInfo = MBBInfoMap[Pred];
2704  if (!PredInfo.reachable)
2705  continue;
2706 
2707  VRegs.add(PredInfo.regsLiveOut);
2708  VRegs.add(PredInfo.vregsPassed);
2709  }
2710  Info.vregsPassed.reserve(VRegs.size());
2711  Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2712  }
2713 }
2714 
2715 // Calculate the set of virtual registers that must be passed through each basic
2716 // block in order to satisfy the requirements of successor blocks. This is very
2717 // similar to calcRegsPassed, only backwards.
2718 void MachineVerifier::calcRegsRequired() {
2719  // First push live-in regs to predecessors' vregsRequired.
2721  for (const auto &MBB : *MF) {
2722  BBInfo &MInfo = MBBInfoMap[&MBB];
2723  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2724  BBInfo &PInfo = MBBInfoMap[Pred];
2725  if (PInfo.addRequired(MInfo.vregsLiveIn))
2726  todo.insert(Pred);
2727  }
2728 
2729  // Handle the PHI node.
2730  for (const MachineInstr &MI : MBB.phis()) {
2731  for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
2732  // Skip those Operands which are undef regs or not regs.
2733  if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
2734  continue;
2735 
2736  // Get register and predecessor for one PHI edge.
2737  Register Reg = MI.getOperand(i).getReg();
2738  const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
2739 
2740  BBInfo &PInfo = MBBInfoMap[Pred];
2741  if (PInfo.addRequired(Reg))
2742  todo.insert(Pred);
2743  }
2744  }
2745  }
2746 
2747  // Iteratively push vregsRequired to predecessors. This will converge to the
2748  // same final state regardless of DenseSet iteration order.
2749  while (!todo.empty()) {
2750  const MachineBasicBlock *MBB = *todo.begin();
2751  todo.erase(MBB);
2752  BBInfo &MInfo = MBBInfoMap[MBB];
2753  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2754  if (Pred == MBB)
2755  continue;
2756  BBInfo &SInfo = MBBInfoMap[Pred];
2757  if (SInfo.addRequired(MInfo.vregsRequired))
2758  todo.insert(Pred);
2759  }
2760  }
2761 }
2762 
2763 // Check PHI instructions at the beginning of MBB. It is assumed that
2764 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2765 void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2766  BBInfo &MInfo = MBBInfoMap[&MBB];
2767 
2769  for (const MachineInstr &Phi : MBB) {
2770  if (!Phi.isPHI())
2771  break;
2772  seen.clear();
2773 
2774  const MachineOperand &MODef = Phi.getOperand(0);
2775  if (!MODef.isReg() || !MODef.isDef()) {
2776  report("Expected first PHI operand to be a register def", &MODef, 0);
2777  continue;
2778  }
2779  if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2780  MODef.isEarlyClobber() || MODef.isDebug())
2781  report("Unexpected flag on PHI operand", &MODef, 0);
2782  Register DefReg = MODef.getReg();
2783  if (!Register::isVirtualRegister(DefReg))
2784  report("Expected first PHI operand to be a virtual register", &MODef, 0);
2785 
2786  for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2787  const MachineOperand &MO0 = Phi.getOperand(I);
2788  if (!MO0.isReg()) {
2789  report("Expected PHI operand to be a register", &MO0, I);
2790  continue;
2791  }
2792  if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2793  MO0.isDebug() || MO0.isTied())
2794  report("Unexpected flag on PHI operand", &MO0, I);
2795 
2796  const MachineOperand &MO1 = Phi.getOperand(I + 1);
2797  if (!MO1.isMBB()) {
2798  report("Expected PHI operand to be a basic block", &MO1, I + 1);
2799  continue;
2800  }
2801 
2802  const MachineBasicBlock &Pre = *MO1.getMBB();
2803  if (!Pre.isSuccessor(&MBB)) {
2804  report("PHI input is not a predecessor block", &MO1, I + 1);
2805  continue;
2806  }
2807 
2808  if (MInfo.reachable) {
2809  seen.insert(&Pre);
2810  BBInfo &PrInfo = MBBInfoMap[&Pre];
2811  if (!MO0.isUndef() && PrInfo.reachable &&
2812  !PrInfo.isLiveOut(MO0.getReg()))
2813  report("PHI operand is not live-out from predecessor", &MO0, I);
2814  }
2815  }
2816 
2817  // Did we see all predecessors?
2818  if (MInfo.reachable) {
2819  for (MachineBasicBlock *Pred : MBB.predecessors()) {
2820  if (!seen.count(Pred)) {
2821  report("Missing PHI operand", &Phi);
2822  errs() << printMBBReference(*Pred)
2823  << " is a predecessor according to the CFG.\n";
2824  }
2825  }
2826  }
2827  }
2828 }
2829 
2830 void MachineVerifier::visitMachineFunctionAfter() {
2831  calcRegsPassed();
2832 
2833  for (const MachineBasicBlock &MBB : *MF)
2834  checkPHIOps(MBB);
2835 
2836  // Now check liveness info if available
2837  calcRegsRequired();
2838 
2839  // Check for killed virtual registers that should be live out.
2840  for (const auto &MBB : *MF) {
2841  BBInfo &MInfo = MBBInfoMap[&MBB];
2842  for (Register VReg : MInfo.vregsRequired)
2843  if (MInfo.regsKilled.count(VReg)) {
2844  report("Virtual register killed in block, but needed live out.", &MBB);
2845  errs() << "Virtual register " << printReg(VReg)
2846  << " is used after the block.\n";
2847  }
2848  }
2849 
2850  if (!MF->empty()) {
2851  BBInfo &MInfo = MBBInfoMap[&MF->front()];
2852  for (Register VReg : MInfo.vregsRequired) {
2853  report("Virtual register defs don't dominate all uses.", MF);
2854  report_context_vreg(VReg);
2855  }
2856  }
2857 
2858  if (LiveVars)
2859  verifyLiveVariables();
2860  if (LiveInts)
2861  verifyLiveIntervals();
2862 
2863  // Check live-in list of each MBB. If a register is live into MBB, check
2864  // that the register is in regsLiveOut of each predecessor block. Since
2865  // this must come from a definition in the predecesssor or its live-in
2866  // list, this will catch a live-through case where the predecessor does not
2867  // have the register in its live-in list. This currently only checks
2868  // registers that have no aliases, are not allocatable and are not
2869  // reserved, which could mean a condition code register for instance.
2870  if (MRI->tracksLiveness())
2871  for (const auto &MBB : *MF)
2873  MCPhysReg LiveInReg = P.PhysReg;
2874  bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
2875  if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2876  continue;
2877  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2878  BBInfo &PInfo = MBBInfoMap[Pred];
2879  if (!PInfo.regsLiveOut.count(LiveInReg)) {
2880  report("Live in register not found to be live out from predecessor.",
2881  &MBB);
2882  errs() << TRI->getName(LiveInReg)
2883  << " not found to be live out from "
2884  << printMBBReference(*Pred) << "\n";
2885  }
2886  }
2887  }
2888 
2889  for (auto CSInfo : MF->getCallSitesInfo())
2890  if (!CSInfo.first->isCall())
2891  report("Call site info referencing instruction that is not call", MF);
2892 
2893  // If there's debug-info, check that we don't have any duplicate value
2894  // tracking numbers.
2895  if (MF->getFunction().getSubprogram()) {
2896  DenseSet<unsigned> SeenNumbers;
2897  for (const auto &MBB : *MF) {
2898  for (const auto &MI : MBB) {
2899  if (auto Num = MI.peekDebugInstrNum()) {
2900  auto Result = SeenNumbers.insert((unsigned)Num);
2901  if (!Result.second)
2902  report("Instruction has a duplicated value tracking number", &MI);
2903  }
2904  }
2905  }
2906  }
2907 }
2908 
2909 void MachineVerifier::verifyLiveVariables() {
2910  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2911  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2913  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2914  for (const auto &MBB : *MF) {
2915  BBInfo &MInfo = MBBInfoMap[&MBB];
2916 
2917  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2918  if (MInfo.vregsRequired.count(Reg)) {
2919  if (!VI.AliveBlocks.test(MBB.getNumber())) {
2920  report("LiveVariables: Block missing from AliveBlocks", &MBB);
2921  errs() << "Virtual register " << printReg(Reg)
2922  << " must be live through the block.\n";
2923  }
2924  } else {
2925  if (VI.AliveBlocks.test(MBB.getNumber())) {
2926  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2927  errs() << "Virtual register " << printReg(Reg)
2928  << " is not needed live through the block.\n";
2929  }
2930  }
2931  }
2932  }
2933 }
2934 
2935 void MachineVerifier::verifyLiveIntervals() {
2936  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2937  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2939 
2940  // Spilling and splitting may leave unused registers around. Skip them.
2941  if (MRI->reg_nodbg_empty(Reg))
2942  continue;
2943 
2944  if (!LiveInts->hasInterval(Reg)) {
2945  report("Missing live interval for virtual register", MF);
2946  errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2947  continue;
2948  }
2949 
2950  const LiveInterval &LI = LiveInts->getInterval(Reg);
2951  assert(Reg == LI.reg() && "Invalid reg to interval mapping");
2952  verifyLiveInterval(LI);
2953  }
2954 
2955  // Verify all the cached regunit intervals.
2956  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2957  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2958  verifyLiveRange(*LR, i);
2959 }
2960 
2961 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2962  const VNInfo *VNI, Register Reg,
2963  LaneBitmask LaneMask) {
2964  if (VNI->isUnused())
2965  return;
2966 
2967  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2968 
2969  if (!DefVNI) {
2970  report("Value not live at VNInfo def and not marked unused", MF);
2971  report_context(LR, Reg, LaneMask);
2972  report_context(*VNI);
2973  return;
2974  }
2975 
2976  if (DefVNI != VNI) {
2977  report("Live segment at def has different VNInfo", MF);
2978  report_context(LR, Reg, LaneMask);
2979  report_context(*VNI);
2980  return;
2981  }
2982 
2983  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2984  if (!MBB) {
2985  report("Invalid VNInfo definition index", MF);
2986  report_context(LR, Reg, LaneMask);
2987  report_context(*VNI);
2988  return;
2989  }
2990 
2991  if (VNI->isPHIDef()) {
2992  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2993  report("PHIDef VNInfo is not defined at MBB start", MBB);
2994  report_context(LR, Reg, LaneMask);
2995  report_context(*VNI);
2996  }
2997  return;
2998  }
2999 
3000  // Non-PHI def.
3001  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
3002  if (!MI) {
3003  report("No instruction at VNInfo def index", MBB);
3004  report_context(LR, Reg, LaneMask);
3005  report_context(*VNI);
3006  return;
3007  }
3008 
3009  if (Reg != 0) {
3010  bool hasDef = false;
3011  bool isEarlyClobber = false;
3012  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3013  if (!MOI->isReg() || !MOI->isDef())
3014  continue;
3016  if (MOI->getReg() != Reg)
3017  continue;
3018  } else {
3019  if (!Register::isPhysicalRegister(MOI->getReg()) ||
3020  !TRI->hasRegUnit(MOI->getReg(), Reg))
3021  continue;
3022  }
3023  if (LaneMask.any() &&
3024  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3025  continue;
3026  hasDef = true;
3027  if (MOI->isEarlyClobber())
3028  isEarlyClobber = true;
3029  }
3030 
3031  if (!hasDef) {
3032  report("Defining instruction does not modify register", MI);
3033  report_context(LR, Reg, LaneMask);
3034  report_context(*VNI);
3035  }
3036 
3037  // Early clobber defs begin at USE slots, but other defs must begin at
3038  // DEF slots.
3039  if (isEarlyClobber) {
3040  if (!VNI->def.isEarlyClobber()) {
3041  report("Early clobber def must be at an early-clobber slot", MBB);
3042  report_context(LR, Reg, LaneMask);
3043  report_context(*VNI);
3044  }
3045  } else if (!VNI->def.isRegister()) {
3046  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
3047  report_context(LR, Reg, LaneMask);
3048  report_context(*VNI);
3049  }
3050  }
3051 }
3052 
3053 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
3055  Register Reg,
3056  LaneBitmask LaneMask) {
3057  const LiveRange::Segment &S = *I;
3058  const VNInfo *VNI = S.valno;
3059  assert(VNI && "Live segment has no valno");
3060 
3061  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
3062  report("Foreign valno in live segment", MF);
3063  report_context(LR, Reg, LaneMask);
3064  report_context(S);
3065  report_context(*VNI);
3066  }
3067 
3068  if (VNI->isUnused()) {
3069  report("Live segment valno is marked unused", MF);
3070  report_context(LR, Reg, LaneMask);
3071  report_context(S);
3072  }
3073 
3074  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
3075  if (!MBB) {
3076  report("Bad start of live segment, no basic block", MF);
3077  report_context(LR, Reg, LaneMask);
3078  report_context(S);
3079  return;
3080  }
3081  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
3082  if (S.start != MBBStartIdx && S.start != VNI->def) {
3083  report("Live segment must begin at MBB entry or valno def", MBB);
3084  report_context(LR, Reg, LaneMask);
3085  report_context(S);
3086  }
3087 
3088  const MachineBasicBlock *EndMBB =
3089  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
3090  if (!EndMBB) {
3091  report("Bad end of live segment, no basic block", MF);
3092  report_context(LR, Reg, LaneMask);
3093  report_context(S);
3094  return;
3095  }
3096 
3097  // No more checks for live-out segments.
3098  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
3099  return;
3100 
3101  // RegUnit intervals are allowed dead phis.
3102  if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
3103  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
3104  return;
3105 
3106  // The live segment is ending inside EndMBB
3107  const MachineInstr *MI =
3108  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
3109  if (!MI) {
3110  report("Live segment doesn't end at a valid instruction", EndMBB);
3111  report_context(LR, Reg, LaneMask);
3112  report_context(S);
3113  return;
3114  }
3115 
3116  // The block slot must refer to a basic block boundary.
3117  if (S.end.isBlock()) {
3118  report("Live segment ends at B slot of an instruction", EndMBB);
3119  report_context(LR, Reg, LaneMask);
3120  report_context(S);
3121  }
3122 
3123  if (S.end.isDead()) {
3124  // Segment ends on the dead slot.
3125  // That means there must be a dead def.
3126  if (!SlotIndex::isSameInstr(S.start, S.end)) {
3127  report("Live segment ending at dead slot spans instructions", EndMBB);
3128  report_context(LR, Reg, LaneMask);
3129  report_context(S);
3130  }
3131  }
3132 
3133  // After tied operands are rewritten, a live segment can only end at an
3134  // early-clobber slot if it is being redefined by an early-clobber def.
3135  // TODO: Before tied operands are rewritten, a live segment can only end at an
3136  // early-clobber slot if the last use is tied to an early-clobber def.
3137  if (MF->getProperties().hasProperty(
3139  S.end.isEarlyClobber()) {
3140  if (I+1 == LR.end() || (I+1)->start != S.end) {
3141  report("Live segment ending at early clobber slot must be "
3142  "redefined by an EC def in the same instruction", EndMBB);
3143  report_context(LR, Reg, LaneMask);
3144  report_context(S);
3145  }
3146  }
3147 
3148  // The following checks only apply to virtual registers. Physreg liveness
3149  // is too weird to check.
3151  // A live segment can end with either a redefinition, a kill flag on a
3152  // use, or a dead flag on a def.
3153  bool hasRead = false;
3154  bool hasSubRegDef = false;
3155  bool hasDeadDef = false;
3156  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3157  if (!MOI->isReg() || MOI->getReg() != Reg)
3158  continue;
3159  unsigned Sub = MOI->getSubReg();
3160  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
3161  : LaneBitmask::getAll();
3162  if (MOI->isDef()) {
3163  if (Sub != 0) {
3164  hasSubRegDef = true;
3165  // An operand %0:sub0 reads %0:sub1..n. Invert the lane
3166  // mask for subregister defs. Read-undef defs will be handled by
3167  // readsReg below.
3168  SLM = ~SLM;
3169  }
3170  if (MOI->isDead())
3171  hasDeadDef = true;
3172  }
3173  if (LaneMask.any() && (LaneMask & SLM).none())
3174  continue;
3175  if (MOI->readsReg())
3176  hasRead = true;
3177  }
3178  if (S.end.isDead()) {
3179  // Make sure that the corresponding machine operand for a "dead" live
3180  // range has the dead flag. We cannot perform this check for subregister
3181  // liveranges as partially dead values are allowed.
3182  if (LaneMask.none() && !hasDeadDef) {
3183  report("Instruction ending live segment on dead slot has no dead flag",
3184  MI);
3185  report_context(LR, Reg, LaneMask);
3186  report_context(S);
3187  }
3188  } else {
3189  if (!hasRead) {
3190  // When tracking subregister liveness, the main range must start new
3191  // values on partial register writes, even if there is no read.
3192  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3193  !hasSubRegDef) {
3194  report("Instruction ending live segment doesn't read the register",
3195  MI);
3196  report_context(LR, Reg, LaneMask);
3197  report_context(S);
3198  }
3199  }
3200  }
3201  }
3202 
3203  // Now check all the basic blocks in this live segment.
3205  // Is this live segment the beginning of a non-PHIDef VN?
3206  if (S.start == VNI->def && !VNI->isPHIDef()) {
3207  // Not live-in to any blocks.
3208  if (MBB == EndMBB)
3209  return;
3210  // Skip this block.
3211  ++MFI;
3212  }
3213 
3215  if (LaneMask.any()) {
3216  LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3217  OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3218  }
3219 
3220  while (true) {
3221  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3222  // We don't know how to track physregs into a landing pad.
3223  if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
3224  if (&*MFI == EndMBB)
3225  break;
3226  ++MFI;
3227  continue;
3228  }
3229 
3230  // Is VNI a PHI-def in the current block?
3231  bool IsPHI = VNI->isPHIDef() &&
3232  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3233 
3234  // Check that VNI is live-out of all predecessors.
3235  for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3236  SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3237  // Predecessor of landing pad live-out on last call.
3238  if (MFI->isEHPad()) {
3239  for (const MachineInstr &MI : llvm::reverse(*Pred)) {
3240  if (MI.isCall()) {
3241  PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3242  break;
3243  }
3244  }
3245  }
3246  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3247 
3248  // All predecessors must have a live-out value. However for a phi
3249  // instruction with subregister intervals
3250  // only one of the subregisters (not necessarily the current one) needs to
3251  // be defined.
3252  if (!PVNI && (LaneMask.none() || !IsPHI)) {
3253  if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3254  continue;
3255  report("Register not marked live out of predecessor", Pred);
3256  report_context(LR, Reg, LaneMask);
3257  report_context(*VNI);
3258  errs() << " live into " << printMBBReference(*MFI) << '@'
3259  << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3260  << PEnd << '\n';
3261  continue;
3262  }
3263 
3264  // Only PHI-defs can take different predecessor values.
3265  if (!IsPHI && PVNI != VNI) {
3266  report("Different value live out of predecessor", Pred);
3267  report_context(LR, Reg, LaneMask);
3268  errs() << "Valno #" << PVNI->id << " live out of "
3269  << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3270  << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3271  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3272  }
3273  }
3274  if (&*MFI == EndMBB)
3275  break;
3276  ++MFI;
3277  }
3278 }
3279 
3280 void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3281  LaneBitmask LaneMask) {
3282  for (const VNInfo *VNI : LR.valnos)
3283  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3284 
3285  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3286  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3287 }
3288 
3289 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3290  Register Reg = LI.reg();
3292  verifyLiveRange(LI, Reg);
3293 
3294  LaneBitmask Mask;
3296  for (const LiveInterval::SubRange &SR : LI.subranges()) {
3297  if ((Mask & SR.LaneMask).any()) {
3298  report("Lane masks of sub ranges overlap in live interval", MF);
3299  report_context(LI);
3300  }
3301  if ((SR.LaneMask & ~MaxMask).any()) {
3302  report("Subrange lanemask is invalid", MF);
3303  report_context(LI);
3304  }
3305  if (SR.empty()) {
3306  report("Subrange must not be empty", MF);
3307  report_context(SR, LI.reg(), SR.LaneMask);
3308  }
3309  Mask |= SR.LaneMask;
3310  verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3311  if (!LI.covers(SR)) {
3312  report("A Subrange is not covered by the main range", MF);
3313  report_context(LI);
3314  }
3315  }
3316 
3317  // Check the LI only has one connected component.
3318  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3319  unsigned NumComp = ConEQ.Classify(LI);
3320  if (NumComp > 1) {
3321  report("Multiple connected components in live interval", MF);
3322  report_context(LI);
3323  for (unsigned comp = 0; comp != NumComp; ++comp) {
3324  errs() << comp << ": valnos";
3325  for (const VNInfo *I : LI.valnos)
3326  if (comp == ConEQ.getEqClass(I))
3327  errs() << ' ' << I->id;
3328  errs() << '\n';
3329  }
3330  }
3331 }
3332 
3333 namespace {
3334 
3335  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3336  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3337  // value is zero.
3338  // We use a bool plus an integer to capture the stack state.
3339  struct StackStateOfBB {
3340  StackStateOfBB() = default;
3341  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3342  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3343  ExitIsSetup(ExitSetup) {}
3344 
3345  // Can be negative, which means we are setting up a frame.
3346  int EntryValue = 0;
3347  int ExitValue = 0;
3348  bool EntryIsSetup = false;
3349  bool ExitIsSetup = false;
3350  };
3351 
3352 } // end anonymous namespace
3353 
3354 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3355 /// by a FrameDestroy <n>, stack adjustments are identical on all
3356 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
3357 void MachineVerifier::verifyStackFrame() {
3358  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3359  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3360  if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3361  return;
3362 
3364  SPState.resize(MF->getNumBlockIDs());
3366 
3367  // Visit the MBBs in DFS order.
3368  for (df_ext_iterator<const MachineFunction *,
3370  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3371  DFI != DFE; ++DFI) {
3372  const MachineBasicBlock *MBB = *DFI;
3373 
3374  StackStateOfBB BBState;
3375  // Check the exit state of the DFS stack predecessor.
3376  if (DFI.getPathLength() >= 2) {
3377  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3378  assert(Reachable.count(StackPred) &&
3379  "DFS stack predecessor is already visited.\n");
3380  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3381  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3382  BBState.ExitValue = BBState.EntryValue;
3383  BBState.ExitIsSetup = BBState.EntryIsSetup;
3384  }
3385 
3386  // Update stack state by checking contents of MBB.
3387  for (const auto &I : *MBB) {
3388  if (I.getOpcode() == FrameSetupOpcode) {
3389  if (BBState.ExitIsSetup)
3390  report("FrameSetup is after another FrameSetup", &I);
3391  BBState.ExitValue -= TII->getFrameTotalSize(I);
3392  BBState.ExitIsSetup = true;
3393  }
3394 
3395  if (I.getOpcode() == FrameDestroyOpcode) {
3396  int Size = TII->getFrameTotalSize(I);
3397  if (!BBState.ExitIsSetup)
3398  report("FrameDestroy is not after a FrameSetup", &I);
3399  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3400  BBState.ExitValue;
3401  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3402  report("FrameDestroy <n> is after FrameSetup <m>", &I);
3403  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3404  << AbsSPAdj << ">.\n";
3405  }
3406  BBState.ExitValue += Size;
3407  BBState.ExitIsSetup = false;
3408  }
3409  }
3410  SPState[MBB->getNumber()] = BBState;
3411 
3412  // Make sure the exit state of any predecessor is consistent with the entry
3413  // state.
3414  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3415  if (Reachable.count(Pred) &&
3416  (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3417  SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3418  report("The exit stack state of a predecessor is inconsistent.", MBB);
3419  errs() << "Predecessor " << printMBBReference(*Pred)
3420  << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3421  << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3422  << printMBBReference(*MBB) << " has entry state ("
3423  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3424  }
3425  }
3426 
3427  // Make sure the entry state of any successor is consistent with the exit
3428  // state.
3429  for (const MachineBasicBlock *Succ : MBB->successors()) {
3430  if (Reachable.count(Succ) &&
3431  (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3432  SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3433  report("The entry stack state of a successor is inconsistent.", MBB);
3434  errs() << "Successor " << printMBBReference(*Succ)
3435  << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3436  << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3437  << printMBBReference(*MBB) << " has exit state ("
3438  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3439  }
3440  }
3441 
3442  // Make sure a basic block with return ends with zero stack adjustment.
3443  if (!MBB->empty() && MBB->back().isReturn()) {
3444  if (BBState.ExitIsSetup)
3445  report("A return block ends with a FrameSetup.", MBB);
3446  if (BBState.ExitValue)
3447  report("A return block ends with a nonzero stack adjustment.", MBB);
3448  }
3449  }
3450 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:637
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:809
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:381
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:288
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::LiveInterval::computeSubRangeUndefs
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
Definition: LiveInterval.cpp:962
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:192
llvm::MachineBasicBlock::pred_begin
pred_iterator pred_begin()
Definition: MachineBasicBlock.h:353
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
MathExtras.h
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:392
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LiveStacks::getInterval
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:68
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
ModRef.h
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1299
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:382
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1748
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:387
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:212
llvm::SmallPtrSetImpl::erase
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:379
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ID
Definition: AArch64BaseInfo.h:818
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llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:224
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Definition: LiveIntervals.h:239
llvm::ConstantInt::getBitWidth
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:136
MCInstrDesc.h
SetOperations.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:59
llvm::Function
Definition: Function.h:60
llvm::PseudoProbeReservedId::Last
@ Last
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:433
llvm::BitVector::clear
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:328
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:300
llvm::SlotIndex::getBoundaryIndex
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
Definition: SlotIndexes.h:253
llvm::set_union
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:23
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::LiveIntervals::isNotInMIMap
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
Definition: LiveIntervals.h:215
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:742
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:230
InlineAsm.h
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:365
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:117
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:225
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:431
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::LiveQueryResult::isDeadDef
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
llvm::LiveRange::Segment
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:133
RegisterBankInfo.h
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
INITIALIZE_PASS
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
Definition: MachineVerifier.cpp:322
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:240
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::MachineBasicBlock::isIRBlockAddressTaken
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
Definition: MachineBasicBlock.h:239
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:167
DenseMap.h
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:449
llvm::AttributeList
Definition: Attributes.h:431
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:67
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1659
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
EHPersonalities.h
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:298
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:770
llvm::SmallPtrSet< const MachineBasicBlock *, 8 >
llvm::SlotIndex::isEarlyClobber
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:234
llvm::Intrinsic::getAttributes
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
llvm::SlotIndexes::getMBBEndIdx
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:481
llvm::Packing::Dense
@ Dense
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
STLExtras.h
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:285
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:330
llvm::LiveQueryResult
Result of a LiveRange query.
Definition: LiveInterval.h:90
llvm::detail::DenseSetImpl::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1238
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
p
the resulting code requires compare and branches when and if * p
Definition: README.txt:396
UseOpIdx
unsigned UseOpIdx
Definition: RISCVInsertVSETVLI.cpp:600
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:249
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
DepthFirstIterator.h
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:220
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:526
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MCRegisterInfo::subregs
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
Definition: MCRegisterInfo.h:309
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:195
llvm::LiveIntervals::print
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Definition: LiveIntervals.cpp:148
isLiveOut
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
Definition: SIOptimizeExecMasking.cpp:316
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:22
llvm::verifyMachineFunction
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
Definition: MachineVerifier.cpp:329
llvm::df_ext_begin
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:242
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:365
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:119
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::APFloatBase::getSizeInBits
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:255
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1734
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
fcAllFlags
@ fcAllFlags
Definition: FloatingPointMode.h:219
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:385
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::LiveStacks::hasInterval
bool hasInterval(int Slot) const
Definition: LiveStacks.h:82
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
llvm::MachineFunctionProperties::Property::Selected
@ Selected
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::PGSOQueryType::Test
@ Test
llvm::LiveVariables::VarInfo
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:80
Constants.h
llvm::LiveRange::begin
iterator begin()
Definition: LiveInterval.h:215
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:381
llvm::MCRegisterInfo::subregs_inclusive
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
Definition: MCRegisterInfo.h:316
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:230
llvm::LiveIntervals::getCachedRegUnit
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
Definition: LiveIntervals.h:400
llvm::LiveRange::covers
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
Definition: LiveInterval.cpp:479
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::set_subtract
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:63
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:371
llvm::Pass::getAnalysisIfAvailable
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Definition: PassAnalysisSupport.h:211
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:108
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:930
Twine.h
llvm::BitVector::size
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:152
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:227
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:639
llvm::MachineBasicBlock::isSuccessor
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Definition: MachineBasicBlock.cpp:924
llvm::LiveRange::const_iterator
Segments::const_iterator const_iterator
Definition: LiveInterval.h:213
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:56
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LaneBitmask::getNone
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:431
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:748
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:328
LiveVariables.h
DenseSet.h
llvm::MachineBasicBlock::getAddressTakenIRBlock
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
Definition: MachineBasicBlock.h:242
TargetOpcodes.h
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MemoryEffects::doesNotAccessMemory
bool doesNotAccessMemory() const
Whether this function accesses no memory.
Definition: ModRef.h:191
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
pass
modulo schedule Modulo Schedule test pass
Definition: ModuloSchedule.cpp:2145
llvm::LiveRange::valnos
VNInfoList valnos
Definition: LiveInterval.h:204
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:100
MachineInstrBundle.h
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:142
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:390
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::PrintLaneMask
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:642
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:264
BitVector.h
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:854
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:529
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:319
llvm::SlotIndex::isRegister
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:238
SmallPtrSet.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::BitVector
Definition: BitVector.h:75
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
none
@ none
Definition: HWAddressSanitizer.cpp:188
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:342
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::MachineRegisterInfo::reservedRegsFrozen
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
Definition: MachineRegisterInfo.h:905
llvm::LiveQueryResult::valueIn
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
llvm::MachineFunctionAnalysisManager
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
Definition: MachinePassManager.h:41
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
LowLevelTypeImpl.h
llvm::initializeMachineVerifierPassPass
void initializeMachineVerifierPassPass(PassRegistry &)
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:142
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
llvm::SlotIndexes::MBBIndexEnd
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:514
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:183
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::MachineFunctionProperties::Property::FailsVerification
@ FailsVerification
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:238
llvm::SmallPtrSetImplBase::empty
bool empty() const
Definition: SmallPtrSet.h:92
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::BasicBlock::hasAddressTaken
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
Definition: BasicBlock.h:484
BasicBlock.h
llvm::ClrHandlerType::Filter
@ Filter
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
VI
@ VI
Definition: SIInstrInfo.cpp:7967
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::LiveRange::getVNInfoBefore
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:429
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:471
llvm::MachineBasicBlock::pred_end
pred_iterator pred_end()
Definition: MachineBasicBlock.h:355
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:110
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
LiveIntervals.h
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::LiveIntervals::getMBBEndIdx
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Definition: LiveIntervals.h:235
llvm::VNInfo::id
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:777
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::MCOperandInfo::isGenericType
bool isGenericType() const
Definition: MCInstrDesc.h:117
llvm::SlotIndexes::MBBIndexBegin
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:509
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::DenseMap
Definition: DenseMap.h:714
llvm::LiveRange::getNumValNums
unsigned getNumValNums() const
Definition: LiveInterval.h:313
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFunctionProperties::Property::TracksDebugUserValues
@ TracksDebugUserValues
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:53
llvm::isScopedEHPersonality
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
Definition: EHPersonalities.h:79
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:60
MCRegisterInfo.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::SmallPtrSetImpl::begin
iterator begin() const
Definition: SmallPtrSet.h:403
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:126
llvm::createMachineVerifierPass
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1868
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:198
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:541
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
MachineFunctionPass.h
llvm::MachineFunctionProperties::Property::RegBankSelected
@ RegBankSelected
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:664
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1861
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:369
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:435
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:270
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:602
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
CodeGenCommonISel.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:386
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:347
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:395
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:862
isStore
static bool isStore(int Opcode)
Definition: ARCInstrInfo.cpp:58
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:118
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:259
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:112
llvm::SmallPtrSetImpl::count
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:383
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:131
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::df_iterator_default_set
Definition: DepthFirstIterator.h:70
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1715
llvm::MachineOperand::isShuffleMask
bool isShuffleMask() const
Definition: MachineOperand.h:353
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::SmallPtrSetImplBase::clear
void clear()
Definition: SmallPtrSet.h:95
llvm::MachineBasicBlock::phis
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
Definition: MachineBasicBlock.h:333
llvm::ArrayRef< int >
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1115
llvm::logicalview::LVCompareKind::Types
@ Types
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:180
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:392
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:576
isLoad
static bool isLoad(int Opcode)
Definition: ARCInstrInfo.cpp:53
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:351
uint32_t
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:2013
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
TargetSubtargetInfo.h
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:896
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineFunctionProperties::Property::TiedOpsRewritten
@ TiedOpsRewritten
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:415
llvm::df_ext_end
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:247
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:693
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:919
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallPtrSetImplBase::size
size_type size() const
Definition: SmallPtrSet.h:93
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::MachineBasicBlock::isPredecessor
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
Definition: MachineBasicBlock.cpp:920
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::AtomicOrdering::Release
@ Release
llvm::VNInfo::isPHIDef
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeCalc::isJointlyDominated
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
Definition: LiveRangeCalc.cpp:432
llvm::Function::getMemoryEffects
MemoryEffects getMemoryEffects() const
Definition: Function.cpp:731
llvm::MCOperandInfo::getGenericTypeIndex
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:122
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:495
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
std
Definition: BitVector.h:851
llvm::MachineFunctionProperties::Property::NoPHIs
@ NoPHIs
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:457
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:280
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::RegisterBank::getName
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::LLT::getSizeInBytes
TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:162
llvm::RegisterBank::getSize
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:587
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
Casting.h
llvm::FixedStackPseudoSourceValue
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
Definition: PseudoSourceValue.h:94
Function.h
llvm::MachineFunction::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Definition: MachineFunction.cpp:571
llvm::SlotIndexes::MBBIndexIterator
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
Definition: SlotIndexes.h:492
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:673
verify
ppc ctr loops verify
Definition: PPCCTRLoopsVerify.cpp:76
StackMaps.h
llvm::LiveRange::getValNumInfo
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:317
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:291
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:445
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
LiveInterval.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:781
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:184
Instructions.h
PostOrderIterator.h
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:363
LiveStacks.h
RegisterBank.h
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::DstOp
Definition: MachineIRBuilder.h:67
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:717
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::df_ext_iterator
Definition: DepthFirstIterator.h:236
llvm::LiveVariables::getVarInfo
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Definition: LiveVariables.cpp:84
LaneBitmask.h
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:430
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::reverse
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:485
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AnalysisUsage::addUsedIfAvailable
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
Definition: PassAnalysisSupport.h:117
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::VNInfo::isUnused
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:123
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:642
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:63
SlotIndexes.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:248
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:385
raw_ostream.h
llvm::MachineFunction::empty
bool empty() const
Definition: MachineFunction.h:865
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:887
llvm::ConnectedVNInfoEqClasses
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:998
InitializePasses.h
llvm::LiveStacks
Definition: LiveStacks.h:35
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:311
llvm::LiveQueryResult::isKill
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::LaneBitmask::getAll
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SrcOp
Definition: MachineIRBuilder.h:128
llvm::LiveRange::end
iterator end()
Definition: LiveInterval.h:216
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:253
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775