91 struct MachineVerifier {
92 MachineVerifier(
Pass *
pass,
const char *b) : PASS(
pass), Banner(
b) {}
105 unsigned foundErrors;
108 bool isFunctionRegBankSelected;
109 bool isFunctionSelected;
110 bool isFunctionTracksDebugUserValues;
120 BlockSet FunctionBlocks;
124 RegVector regsDefined, regsDead, regsKilled;
125 RegMaskVector regMasks;
130 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
132 if (
Reg.isPhysical())
138 bool reachable =
false;
159 RegSet vregsRequired;
162 BlockSet Preds, Succs;
169 if (!
Reg.isVirtual())
171 if (regsLiveOut.count(Reg))
173 return vregsRequired.insert(Reg).second;
177 bool addRequired(
const RegSet &RS) {
178 bool Changed =
false;
180 Changed |= addRequired(Reg);
185 bool addRequired(
const RegMap &RM) {
186 bool Changed =
false;
187 for (
const auto &
I : RM)
188 Changed |= addRequired(
I.first);
194 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
202 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
205 bool isAllocatable(
Register Reg)
const {
206 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
216 void visitMachineFunctionBefore();
228 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
231 void visitMachineFunctionAfter();
236 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
244 void report_context(
const VNInfo &VNI)
const;
245 void report_context(
SlotIndex Pos)
const;
246 void report_context(
MCPhysReg PhysReg)
const;
247 void report_context_liverange(
const LiveRange &LR)
const;
248 void report_context_lanemask(
LaneBitmask LaneMask)
const;
249 void report_context_vreg(
Register VReg)
const;
250 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
261 Register VRegOrUnit,
bool SubRangeCheck =
false,
265 void calcRegsPassed();
268 void calcRegsRequired();
269 void verifyLiveVariables();
270 void verifyLiveIntervals();
274 void verifyLiveRangeSegment(
const LiveRange &,
280 void verifyStackFrame();
282 void verifySlotIndexes()
const;
289 const std::string Banner;
291 MachineVerifierPass(std::string banner = std::string())
308 MachineFunctionProperties::Property::FailsVerification))
311 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
320char MachineVerifierPass::ID = 0;
323 "Verify generated machine code",
false,
false)
326 return new MachineVerifierPass(Banner);
330 const std::string &Banner,
337 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
345 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
346 if (AbortOnErrors && FoundErrors)
348 return FoundErrors == 0;
351void MachineVerifier::verifySlotIndexes()
const {
352 if (Indexes ==
nullptr)
370 MRI->getNumVirtRegs())
371 report(
"Function has NoVRegs property but there are VReg operands", &MF);
390 if (isFunctionFailedISel)
415 verifyProperties(MF);
417 visitMachineFunctionBefore();
419 visitMachineBasicBlockBefore(&
MBB);
423 bool InBundle =
false;
426 if (
MI.getParent() != &
MBB) {
427 report(
"Bad instruction parent pointer", &
MBB);
428 errs() <<
"Instruction: " <<
MI;
433 if (InBundle && !
MI.isBundledWithPred())
434 report(
"Missing BundledPred flag, "
435 "BundledSucc was set on predecessor",
437 if (!InBundle &&
MI.isBundledWithPred())
438 report(
"BundledPred flag is set, "
439 "but BundledSucc not set on predecessor",
443 if (!
MI.isInsideBundle()) {
445 visitMachineBundleAfter(CurBundle);
447 visitMachineBundleBefore(CurBundle);
448 }
else if (!CurBundle)
449 report(
"No bundle header", &
MI);
450 visitMachineInstrBefore(&
MI);
451 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
453 if (
Op.getParent() != &
MI) {
456 report(
"Instruction has operand with wrong parent set", &
MI);
459 visitMachineOperand(&Op,
I);
463 InBundle =
MI.isBundledWithSucc();
466 visitMachineBundleAfter(CurBundle);
468 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
469 visitMachineBasicBlockAfter(&
MBB);
471 visitMachineFunctionAfter();
484void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
487 if (!foundErrors++) {
489 errs() <<
"# " << Banner <<
'\n';
490 if (LiveInts !=
nullptr)
495 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
496 <<
"- function: " << MF->
getName() <<
"\n";
510void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
512 report(msg,
MI->getParent());
513 errs() <<
"- instruction: ";
519void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
520 unsigned MONum,
LLT MOVRegType) {
523 errs() <<
"- operand " << MONum <<
": ";
529 report(
Msg.str().c_str(),
MI);
532void MachineVerifier::report_context(
SlotIndex Pos)
const {
533 errs() <<
"- at: " << Pos <<
'\n';
536void MachineVerifier::report_context(
const LiveInterval &LI)
const {
537 errs() <<
"- interval: " << LI <<
'\n';
542 report_context_liverange(LR);
543 report_context_vreg_regunit(VRegUnit);
545 report_context_lanemask(LaneMask);
549 errs() <<
"- segment: " << S <<
'\n';
552void MachineVerifier::report_context(
const VNInfo &VNI)
const {
553 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
556void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
557 errs() <<
"- liverange: " << LR <<
'\n';
560void MachineVerifier::report_context(
MCPhysReg PReg)
const {
564void MachineVerifier::report_context_vreg(
Register VReg)
const {
568void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
570 report_context_vreg(VRegOrUnit);
576void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
581 BBInfo &MInfo = MBBInfoMap[
MBB];
582 if (!MInfo.reachable) {
583 MInfo.reachable =
true;
589void MachineVerifier::visitMachineFunctionBefore() {
591 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
592 :
TRI->getReservedRegs(*MF);
595 markReachable(&MF->
front());
598 FunctionBlocks.clear();
599 for (
const auto &
MBB : *MF) {
600 FunctionBlocks.insert(&
MBB);
601 BBInfo &MInfo = MBBInfoMap[&
MBB];
605 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
609 report(
"MBB has duplicate entries in its successor list.", &
MBB);
613 MRI->verifyUseLists();
621 FirstTerminator =
nullptr;
622 FirstNonPHI =
nullptr;
624 if (!MF->getProperties().hasProperty(
629 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
632 report(
"MBB has allocatable live-in, but isn't entry, landing-pad, or "
633 "inlineasm-br-indirect-target.",
635 report_context(LI.PhysReg);
642 report(
"ir-block-address-taken is associated with basic block not used by "
651 LandingPadSuccs.
insert(succ);
652 if (!FunctionBlocks.count(succ))
653 report(
"MBB has successor that isn't part of the function.",
MBB);
654 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
655 report(
"Inconsistent CFG",
MBB);
656 errs() <<
"MBB is not in the predecessor list of the successor "
663 if (!FunctionBlocks.count(Pred))
664 report(
"MBB has predecessor that isn't part of the function.",
MBB);
665 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
666 report(
"Inconsistent CFG",
MBB);
667 errs() <<
"MBB is not in the successor list of the predecessor "
675 if (LandingPadSuccs.
size() > 1 &&
680 report(
"MBB has more than one landing pad successor",
MBB);
693 report(
"MBB exits via unconditional fall-through but ends with a "
694 "barrier instruction!",
MBB);
697 report(
"MBB exits via unconditional fall-through but has a condition!",
700 }
else if (
TBB && !FBB &&
Cond.empty()) {
703 report(
"MBB exits via unconditional branch but doesn't contain "
704 "any instructions!",
MBB);
706 report(
"MBB exits via unconditional branch but doesn't end with a "
707 "barrier instruction!",
MBB);
709 report(
"MBB exits via unconditional branch but the branch isn't a "
710 "terminator instruction!",
MBB);
712 }
else if (
TBB && !FBB && !
Cond.empty()) {
715 report(
"MBB exits via conditional branch/fall-through but doesn't "
716 "contain any instructions!",
MBB);
718 report(
"MBB exits via conditional branch/fall-through but ends with a "
719 "barrier instruction!",
MBB);
721 report(
"MBB exits via conditional branch/fall-through but the branch "
722 "isn't a terminator instruction!",
MBB);
724 }
else if (
TBB && FBB) {
728 report(
"MBB exits via conditional branch/branch but doesn't "
729 "contain any instructions!",
MBB);
731 report(
"MBB exits via conditional branch/branch but doesn't end with a "
732 "barrier instruction!",
MBB);
734 report(
"MBB exits via conditional branch/branch but the branch "
735 "isn't a terminator instruction!",
MBB);
738 report(
"MBB exits via conditional branch/branch but there's no "
742 report(
"analyzeBranch returned invalid data!",
MBB);
748 report(
"MBB exits via jump or conditional branch, but its target isn't a "
752 report(
"MBB exits via conditional branch, but its target isn't a CFG "
759 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
764 if (!
Cond.empty() && !FBB) {
767 report(
"MBB conditionally falls through out of function!",
MBB);
769 report(
"MBB exits via conditional branch/fall-through but the CFG "
770 "successors don't match the actual successors!",
777 if (SuccMBB ==
TBB || SuccMBB == FBB)
785 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
787 report(
"MBB has unexpected successors which are not branch targets, "
788 "fallthrough, EHPads, or inlineasm_br targets.",
794 if (
MRI->tracksLiveness()) {
797 report(
"MBB live-in list contains non-physical register",
MBB);
821void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
824 if (!(idx > lastIndex)) {
825 report(
"Instruction index out of order",
MI);
826 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
832 if (
MI->isTerminator()) {
833 if (!FirstTerminator)
834 FirstTerminator =
MI;
835 }
else if (FirstTerminator) {
838 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
839 report(
"Non-terminator instruction after the first terminator",
MI);
840 errs() <<
"First terminator was:\t" << *FirstTerminator;
849 if (
MI->getNumOperands() < 2) {
850 report(
"Too few operands on inline asm",
MI);
853 if (!
MI->getOperand(0).isSymbol())
854 report(
"Asm string must be an external symbol",
MI);
855 if (!
MI->getOperand(1).isImm())
856 report(
"Asm flags must be an immediate",
MI);
860 if (!isUInt<6>(
MI->getOperand(1).getImm()))
861 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
867 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
875 if (OpNo >
MI->getNumOperands())
876 report(
"Missing operands in last group",
MI);
879 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
883 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
886 report(
"Expected implicit register after groups", &MO, OpNo);
889 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
902 if (!IndirectTargetMBB) {
903 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
908 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
912 report(
"INLINEASM_BR indirect target predecessor list missing parent",
918bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
923 const auto Reg = Op.getReg();
924 if (Reg.isPhysical())
926 return !MRI.getType(Reg).isScalar();
929 report(
"All register operands must have scalar types", &
MI);
936bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
939 report(
"operand types must be all-vector or all-scalar",
MI);
949 report(
"operand types must preserve number of vector elements",
MI);
956void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
957 if (isFunctionSelected)
958 report(
"Unexpected generic instruction in a Selected function",
MI);
961 unsigned NumOps =
MI->getNumOperands();
964 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
974 report(
"Branch instruction is missing a basic block operand or "
975 "isIndirectBranch property",
988 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
989 Types.resize(std::max(TypeIdx + 1,
Types.size()));
993 report(
"generic instruction must use register operands",
MI);
1003 if (!Types[TypeIdx].
isValid())
1004 Types[TypeIdx] = OpTy;
1005 else if (Types[TypeIdx] != OpTy)
1006 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1009 report(
"Generic instruction is missing a virtual register type", MO,
I);
1014 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1017 report(
"Generic instruction cannot have physical register", MO,
I);
1029 unsigned Opc =
MI->getOpcode();
1031 case TargetOpcode::G_ASSERT_SEXT:
1032 case TargetOpcode::G_ASSERT_ZEXT: {
1033 std::string OpcName =
1034 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1035 if (!
MI->getOperand(2).isImm()) {
1036 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1042 LLT SrcTy =
MRI->getType(Src);
1043 int64_t
Imm =
MI->getOperand(2).getImm();
1045 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1050 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1058 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1059 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1065 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1067 Twine(OpcName,
" source and destination register classes must match"),
1075 case TargetOpcode::G_CONSTANT:
1076 case TargetOpcode::G_FCONSTANT: {
1077 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1079 report(
"Instruction cannot use a vector result type",
MI);
1081 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1082 if (!
MI->getOperand(1).isCImm()) {
1083 report(
"G_CONSTANT operand must be cimm",
MI);
1089 report(
"inconsistent constant size",
MI);
1091 if (!
MI->getOperand(1).isFPImm()) {
1092 report(
"G_FCONSTANT operand must be fpimm",
MI);
1099 report(
"inconsistent constant size",
MI);
1105 case TargetOpcode::G_LOAD:
1106 case TargetOpcode::G_STORE:
1107 case TargetOpcode::G_ZEXTLOAD:
1108 case TargetOpcode::G_SEXTLOAD: {
1109 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1110 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1112 report(
"Generic memory instruction must access a pointer",
MI);
1116 if (!
MI->hasOneMemOperand()) {
1117 report(
"Generic instruction accessing memory must have one mem operand",
1121 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1122 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1124 report(
"Generic extload must have a narrower memory type",
MI);
1125 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1127 report(
"load memory size cannot exceed result size",
MI);
1128 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1130 report(
"store memory size cannot exceed value size",
MI);
1134 if (Opc == TargetOpcode::G_STORE) {
1137 report(
"atomic store cannot use acquire ordering",
MI);
1142 report(
"atomic load cannot use release ordering",
MI);
1148 case TargetOpcode::G_PHI: {
1149 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1154 LLT Ty = MRI->getType(MO.getReg());
1155 if (!Ty.isValid() || (Ty != DstTy))
1159 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1164 case TargetOpcode::G_BITCAST: {
1165 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1166 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1171 report(
"bitcast cannot convert between pointers and other types",
MI);
1174 report(
"bitcast sizes must match",
MI);
1177 report(
"bitcast must change the type",
MI);
1181 case TargetOpcode::G_INTTOPTR:
1182 case TargetOpcode::G_PTRTOINT:
1183 case TargetOpcode::G_ADDRSPACE_CAST: {
1184 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1185 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1189 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1194 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1196 report(
"inttoptr result type must be a pointer",
MI);
1198 report(
"inttoptr source type must not be a pointer",
MI);
1199 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1201 report(
"ptrtoint source type must be a pointer",
MI);
1203 report(
"ptrtoint result type must not be a pointer",
MI);
1205 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1207 report(
"addrspacecast types must be pointers",
MI);
1210 report(
"addrspacecast must convert different address spaces",
MI);
1216 case TargetOpcode::G_PTR_ADD: {
1217 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1218 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1219 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1224 report(
"gep first operand must be a pointer",
MI);
1227 report(
"gep offset operand must not be a pointer",
MI);
1232 case TargetOpcode::G_PTRMASK: {
1233 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1234 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1235 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1240 report(
"ptrmask result type must be a pointer",
MI);
1243 report(
"ptrmask mask type must be an integer",
MI);
1245 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1248 case TargetOpcode::G_SEXT:
1249 case TargetOpcode::G_ZEXT:
1250 case TargetOpcode::G_ANYEXT:
1251 case TargetOpcode::G_TRUNC:
1252 case TargetOpcode::G_FPEXT:
1253 case TargetOpcode::G_FPTRUNC: {
1260 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1261 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1268 report(
"Generic extend/truncate can not operate on pointers",
MI);
1270 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1274 switch (
MI->getOpcode()) {
1276 if (DstSize <= SrcSize)
1277 report(
"Generic extend has destination type no larger than source",
MI);
1279 case TargetOpcode::G_TRUNC:
1280 case TargetOpcode::G_FPTRUNC:
1281 if (DstSize >= SrcSize)
1282 report(
"Generic truncate has destination type no smaller than source",
1288 case TargetOpcode::G_SELECT: {
1289 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1290 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1296 verifyVectorElementMatch(SelTy, CondTy,
MI);
1299 case TargetOpcode::G_MERGE_VALUES: {
1304 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1305 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1307 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1309 const unsigned NumOps =
MI->getNumOperands();
1311 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1313 for (
unsigned I = 2;
I != NumOps; ++
I) {
1314 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1315 report(
"G_MERGE_VALUES source types do not match",
MI);
1320 case TargetOpcode::G_UNMERGE_VALUES: {
1321 unsigned NumDsts =
MI->getNumOperands() - 1;
1322 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1323 for (
unsigned i = 1; i < NumDsts; ++i) {
1324 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1325 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1330 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1335 report(
"G_UNMERGE_VALUES source operand does not match vector "
1336 "destination operands",
1343 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1344 "destination operands",
1349 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1350 "destination operands",
1356 case TargetOpcode::G_BUILD_VECTOR: {
1359 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1360 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1362 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1367 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1370 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1373 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1374 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1378 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1381 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1382 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1384 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1387 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1388 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1391 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1396 case TargetOpcode::G_CONCAT_VECTORS: {
1399 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1400 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1402 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1405 if (
MI->getNumOperands() < 3)
1406 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1409 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1410 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1413 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1416 case TargetOpcode::G_ICMP:
1417 case TargetOpcode::G_FCMP: {
1418 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1419 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1423 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1427 case TargetOpcode::G_EXTRACT: {
1429 if (!
SrcOp.isReg()) {
1430 report(
"extract source must be a register",
MI);
1435 if (!OffsetOp.
isImm()) {
1436 report(
"extract offset must be a constant",
MI);
1440 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1442 if (SrcSize == DstSize)
1443 report(
"extract source must be larger than result",
MI);
1445 if (DstSize + OffsetOp.
getImm() > SrcSize)
1446 report(
"extract reads past end of register",
MI);
1449 case TargetOpcode::G_INSERT: {
1451 if (!
SrcOp.isReg()) {
1452 report(
"insert source must be a register",
MI);
1457 if (!OffsetOp.
isImm()) {
1458 report(
"insert offset must be a constant",
MI);
1462 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1465 if (DstSize <= SrcSize)
1466 report(
"inserted size must be smaller than total register",
MI);
1468 if (SrcSize + OffsetOp.
getImm() > DstSize)
1469 report(
"insert writes past end of register",
MI);
1473 case TargetOpcode::G_JUMP_TABLE: {
1474 if (!
MI->getOperand(1).isJTI())
1475 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1476 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1478 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1481 case TargetOpcode::G_BRJT: {
1482 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1483 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1485 if (!
MI->getOperand(1).isJTI())
1486 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1488 const auto &IdxOp =
MI->getOperand(2);
1489 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1490 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1493 case TargetOpcode::G_INTRINSIC:
1494 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1499 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1503 bool NoSideEffects =
MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1505 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1507 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1508 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
1509 if (NoSideEffects && DeclHasSideEffects) {
1510 report(
"G_INTRINSIC used with intrinsic that accesses memory",
MI);
1513 if (!NoSideEffects && !DeclHasSideEffects) {
1514 report(
"G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic",
MI);
1521 case TargetOpcode::G_SEXT_INREG: {
1522 if (!
MI->getOperand(2).isImm()) {
1523 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1527 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1528 int64_t
Imm =
MI->getOperand(2).getImm();
1530 report(
"G_SEXT_INREG size must be >= 1",
MI);
1532 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1535 case TargetOpcode::G_SHUFFLE_VECTOR: {
1538 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1542 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1543 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1544 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1546 if (Src0Ty != Src1Ty)
1547 report(
"Source operands must be the same type",
MI);
1550 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1559 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1560 report(
"Wrong result type for shufflemask",
MI);
1562 for (
int Idx : MaskIdxes) {
1566 if (
Idx >= 2 * SrcNumElts)
1567 report(
"Out of bounds shuffle index",
MI);
1572 case TargetOpcode::G_DYN_STACKALLOC: {
1578 report(
"dst operand 0 must be a pointer type",
MI);
1582 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
1583 report(
"src operand 1 must be a scalar reg type",
MI);
1587 if (!AlignOp.
isImm()) {
1588 report(
"src operand 2 must be an immediate type",
MI);
1593 case TargetOpcode::G_MEMCPY_INLINE:
1594 case TargetOpcode::G_MEMCPY:
1595 case TargetOpcode::G_MEMMOVE: {
1597 if (MMOs.
size() != 2) {
1598 report(
"memcpy/memmove must have 2 memory operands",
MI);
1604 report(
"wrong memory operand types",
MI);
1609 report(
"inconsistent memory operand sizes",
MI);
1611 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1612 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1615 report(
"memory instruction operand must be a pointer",
MI);
1620 report(
"inconsistent store address space",
MI);
1622 report(
"inconsistent load address space",
MI);
1624 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1625 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
1626 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
1630 case TargetOpcode::G_BZERO:
1631 case TargetOpcode::G_MEMSET: {
1633 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1634 if (MMOs.
size() != 1) {
1635 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1640 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1644 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1646 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1651 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1653 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
1654 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
1655 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
1659 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1660 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1661 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1662 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1663 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1665 report(
"Vector reduction requires a scalar destination type",
MI);
1667 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1669 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1672 case TargetOpcode::G_VECREDUCE_FADD:
1673 case TargetOpcode::G_VECREDUCE_FMUL:
1674 case TargetOpcode::G_VECREDUCE_FMAX:
1675 case TargetOpcode::G_VECREDUCE_FMIN:
1676 case TargetOpcode::G_VECREDUCE_ADD:
1677 case TargetOpcode::G_VECREDUCE_MUL:
1678 case TargetOpcode::G_VECREDUCE_AND:
1679 case TargetOpcode::G_VECREDUCE_OR:
1680 case TargetOpcode::G_VECREDUCE_XOR:
1681 case TargetOpcode::G_VECREDUCE_SMAX:
1682 case TargetOpcode::G_VECREDUCE_SMIN:
1683 case TargetOpcode::G_VECREDUCE_UMAX:
1684 case TargetOpcode::G_VECREDUCE_UMIN: {
1685 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1687 report(
"Vector reduction requires a scalar destination type",
MI);
1691 case TargetOpcode::G_SBFX:
1692 case TargetOpcode::G_UBFX: {
1693 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1695 report(
"Bitfield extraction is not supported on vectors",
MI);
1700 case TargetOpcode::G_SHL:
1701 case TargetOpcode::G_LSHR:
1702 case TargetOpcode::G_ASHR:
1703 case TargetOpcode::G_ROTR:
1704 case TargetOpcode::G_ROTL: {
1705 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1706 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1708 report(
"Shifts and rotates require operands to be either all scalars or "
1715 case TargetOpcode::G_LLROUND:
1716 case TargetOpcode::G_LROUND: {
1717 verifyAllRegOpsScalar(*
MI, *
MRI);
1720 case TargetOpcode::G_IS_FPCLASS: {
1721 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
1724 report(
"Destination must be a scalar or vector of scalars",
MI);
1727 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1730 report(
"Source must be a scalar or vector of scalars",
MI);
1733 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
1736 if (!TestMO.
isImm()) {
1737 report(
"floating-point class set (operand 2) must be an immediate",
MI);
1742 report(
"Incorrect floating-point class set (operand 2)",
MI);
1747 case TargetOpcode::G_ASSERT_ALIGN: {
1748 if (
MI->getOperand(2).getImm() < 1)
1749 report(
"alignment immediate must be >= 1",
MI);
1752 case TargetOpcode::G_CONSTANT_POOL: {
1753 if (!
MI->getOperand(1).isCPI())
1754 report(
"Src operand 1 must be a constant pool index",
MI);
1755 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1756 report(
"Dst operand 0 must be a pointer",
MI);
1764void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
1767 report(
"Too few operands",
MI);
1769 <<
MI->getNumOperands() <<
" given.\n";
1773 if (MF->getProperties().hasProperty(
1775 report(
"Found PHI instruction with NoPHIs property set",
MI);
1778 report(
"Found PHI instruction after non-PHI",
MI);
1779 }
else if (FirstNonPHI ==
nullptr)
1783 if (
MI->isInlineAsm())
1784 verifyInlineAsm(
MI);
1787 if (
TII->isUnspillableTerminator(
MI)) {
1788 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
1789 report(
"Unspillable Terminator does not define a reg",
MI);
1791 if (
Def.isVirtual() &&
1792 !MF->getProperties().hasProperty(
1794 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
1795 report(
"Unspillable Terminator expected to have at most one use!",
MI);
1801 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
1802 if (!
MI->getDebugLoc())
1803 report(
"Missing DebugLoc for debug instruction",
MI);
1807 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
1808 report(
"Metadata instruction should not have a value tracking number",
MI);
1812 if (
Op->isLoad() && !
MI->mayLoad())
1813 report(
"Missing mayLoad flag",
MI);
1814 if (
Op->isStore() && !
MI->mayStore())
1815 report(
"Missing mayStore flag",
MI);
1822 if (
MI->isDebugOrPseudoInstr()) {
1824 report(
"Debug instruction has a slot index",
MI);
1825 }
else if (
MI->isInsideBundle()) {
1827 report(
"Instruction inside bundle has a slot index",
MI);
1830 report(
"Missing slot index",
MI);
1836 verifyPreISelGenericInstruction(
MI);
1845 switch (
MI->getOpcode()) {
1846 case TargetOpcode::COPY: {
1852 LLT DstTy =
MRI->getType(DstReg);
1853 LLT SrcTy =
MRI->getType(SrcReg);
1856 if (SrcTy != DstTy) {
1857 report(
"Copy Instruction is illegal with mismatching types",
MI);
1858 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
1869 unsigned SrcSize = 0;
1870 unsigned DstSize = 0;
1873 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1875 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
1879 SrcSize =
TRI->getRegSizeInBits(SrcReg, *
MRI);
1883 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1885 DstSize =
TRI->getRegSizeInBits(*DstRC);
1889 DstSize =
TRI->getRegSizeInBits(DstReg, *
MRI);
1891 if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1892 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
1893 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
1894 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
1900 case TargetOpcode::STATEPOINT: {
1902 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
1903 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
1904 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1905 report(
"meta operands to STATEPOINT not constant!",
MI);
1909 auto VerifyStackMapConstant = [&](
unsigned Offset) {
1910 if (
Offset >=
MI->getNumOperands()) {
1911 report(
"stack map constant to STATEPOINT is out of range!",
MI);
1914 if (!
MI->getOperand(
Offset - 1).isImm() ||
1915 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
1917 report(
"stack map constant to STATEPOINT not well formed!",
MI);
1919 VerifyStackMapConstant(SO.getCCIdx());
1920 VerifyStackMapConstant(SO.getFlagsIdx());
1921 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1922 VerifyStackMapConstant(SO.getNumGCPtrIdx());
1923 VerifyStackMapConstant(SO.getNumAllocaIdx());
1924 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1928 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1929 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1930 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
1933 report(
"STATEPOINT defs expected to be tied",
MI);
1936 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1937 report(
"STATEPOINT def tied to non-gc operand",
MI);
1944 case TargetOpcode::INSERT_SUBREG: {
1945 unsigned InsertedSize;
1946 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
1947 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
1949 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
1950 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
1951 if (SubRegSize < InsertedSize) {
1952 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
1953 "size than the subreg it was inserted into",
MI);
1957 case TargetOpcode::REG_SEQUENCE: {
1958 unsigned NumOps =
MI->getNumOperands();
1959 if (!(NumOps & 1)) {
1960 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
1964 for (
unsigned I = 1;
I != NumOps;
I += 2) {
1969 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
1971 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
1972 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
1973 report(
"Invalid subregister index operand for REG_SEQUENCE",
1978 Register DstReg =
MI->getOperand(0).getReg();
1980 report(
"REG_SEQUENCE does not support physical register results",
MI);
1982 if (
MI->getOperand(0).getSubReg())
1983 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
1991MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
1995 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
1996 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
1999 if (MONum < NumDefs) {
2002 report(
"Explicit definition must be a register", MO, MONum);
2004 report(
"Explicit definition marked as use", MO, MONum);
2006 report(
"Explicit definition marked as implicit", MO, MONum);
2015 report(
"Explicit operand marked as def", MO, MONum);
2017 report(
"Explicit operand marked as implicit", MO, MONum);
2023 report(
"Expected a register operand.", MO, MONum);
2027 !
TII->isPCRelRegisterOperandLegal(*MO)))
2028 report(
"Expected a non-register operand.", MO, MONum);
2035 report(
"Tied use must be a register", MO, MONum);
2037 report(
"Operand should be tied", MO, MONum);
2038 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2039 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2042 if (!MOTied.
isReg())
2043 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2046 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2049 report(
"Explicit operand should not be tied", MO, MONum);
2053 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2060 if (
MI->isDebugInstr() && MO->
isUse()) {
2062 report(
"Register operand must be marked debug", MO, MONum);
2064 report(
"Register operand must not be marked debug", MO, MONum);
2070 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2071 checkLiveness(MO, MONum);
2075 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2079 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2081 if (!OtherMO.
isReg())
2082 report(
"Must be tied to a register", MO, MONum);
2084 report(
"Missing tie flags on tied operand", MO, MONum);
2085 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2086 report(
"Inconsistent tie links", MO, MONum);
2090 report(
"Explicit def tied to explicit use without tie constraint",
2094 report(
"Explicit def should be tied to implicit use", MO, MONum);
2107 if (MF->getProperties().hasProperty(
2109 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2110 Reg !=
MI->getOperand(DefIdx).getReg())
2111 report(
"Two-address instruction operands must be identical", MO, MONum);
2116 if (
Reg.isPhysical()) {
2118 report(
"Illegal subregister index for physical register", MO, MONum);
2123 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2124 if (!DRC->contains(Reg)) {
2125 report(
"Illegal physical register for instruction", MO, MONum);
2127 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2132 if (
MRI->isReserved(Reg)) {
2133 report(
"isRenamable set on reserved register", MO, MONum);
2150 report(
"Generic virtual register use cannot be undef", MO, MONum);
2157 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2158 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2160 if (isFunctionSelected) {
2161 report(
"Generic virtual register invalid in a Selected function",
2167 LLT Ty =
MRI->getType(Reg);
2169 report(
"Generic virtual register must have a valid type", MO,
2177 if (!RegBank && isFunctionRegBankSelected) {
2178 report(
"Generic virtual register must have a bank in a "
2179 "RegBankSelected function",
2185 if (RegBank && Ty.
isValid() &&
2187 report(
"Register bank is too small for virtual register", MO,
2189 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
2197 report(
"Generic virtual register does not allow subregister index", MO,
2207 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2208 report(
"Virtual register does not match instruction constraint", MO,
2210 errs() <<
"Expect register class "
2211 <<
TRI->getRegClassName(
2212 TII->getRegClass(MCID, MONum,
TRI, *MF))
2213 <<
" but got nothing\n";
2221 TRI->getSubClassWithSubReg(RC, SubIdx);
2223 report(
"Invalid subregister index for virtual register", MO, MONum);
2224 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2225 <<
" does not support subreg index " << SubIdx <<
"\n";
2229 report(
"Invalid register class for subregister index", MO, MONum);
2230 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2231 <<
" does not fully support subreg index " << SubIdx <<
"\n";
2237 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2240 TRI->getLargestLegalSuperClass(RC, *MF);
2242 report(
"No largest legal super class exists.", MO, MONum);
2245 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2247 report(
"No matching super-reg register class.", MO, MONum);
2252 report(
"Illegal virtual register for instruction", MO, MONum);
2253 errs() <<
"Expected a " <<
TRI->getRegClassName(DRC)
2254 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2269 report(
"PHI operand is not in the CFG", MO, MONum);
2280 bool loads =
MI->mayLoad();
2285 for (
auto *MMO :
MI->memoperands()) {
2287 if (PSV ==
nullptr)
continue;
2289 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2290 if (
Value ==
nullptr)
continue;
2291 if (
Value->getFrameIndex() != FI)
continue;
2300 report(
"Missing fixed stack memoperand.",
MI);
2302 if (loads && !LI.
liveAt(
Idx.getRegSlot(
true))) {
2303 report(
"Instruction loads from dead spill slot", MO, MONum);
2304 errs() <<
"Live stack: " << LI <<
'\n';
2307 report(
"Instruction stores to dead spill slot", MO, MONum);
2308 errs() <<
"Live stack: " << LI <<
'\n';
2314 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2315 report(
"CFI instruction has invalid index", MO, MONum);
2323void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2332 report(
"No live segment at use", MO, MONum);
2333 report_context_liverange(LR);
2334 report_context_vreg_regunit(VRegOrUnit);
2335 report_context(UseIdx);
2338 report(
"Live range continues after kill flag", MO, MONum);
2339 report_context_liverange(LR);
2340 report_context_vreg_regunit(VRegOrUnit);
2342 report_context_lanemask(LaneMask);
2343 report_context(UseIdx);
2347void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2362 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2364 (VNI->def != DefIdx &&
2365 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2366 report(
"Inconsistent valno->def", MO, MONum);
2367 report_context_liverange(LR);
2368 report_context_vreg_regunit(VRegOrUnit);
2370 report_context_lanemask(LaneMask);
2371 report_context(*VNI);
2372 report_context(DefIdx);
2375 report(
"No live segment at def", MO, MONum);
2376 report_context_liverange(LR);
2377 report_context_vreg_regunit(VRegOrUnit);
2379 report_context_lanemask(LaneMask);
2380 report_context(DefIdx);
2392 if (SubRangeCheck || MO->
getSubReg() == 0) {
2393 report(
"Live range continues after dead def flag", MO, MONum);
2394 report_context_liverange(LR);
2395 report_context_vreg_regunit(VRegOrUnit);
2397 report_context_lanemask(LaneMask);
2403void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2406 const unsigned SubRegIdx = MO->
getSubReg();
2409 if (LiveInts &&
Reg.isVirtual()) {
2414 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2416 report(
"Virtual register has no live interval", MO, MONum);
2423 addRegWithSubRegs(regsKilled, Reg);
2428 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2429 !
MI->isBundledWithPred()) {
2432 report(
"Kill missing from LiveVariables", MO, MONum);
2439 if (
Reg.isPhysical() && !isReserved(Reg)) {
2442 if (
MRI->isReservedRegUnit(*Units))
2445 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2449 if (
Reg.isVirtual()) {
2451 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2455 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2456 :
MRI->getMaxLaneMaskForVReg(Reg);
2459 if ((MOMask & SR.LaneMask).none())
2461 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2464 LiveInMask |= SR.LaneMask;
2467 if ((LiveInMask & MOMask).
none()) {
2468 report(
"No live subrange at use", MO, MONum);
2469 report_context(*LI);
2470 report_context(UseIdx);
2477 if (!regsLive.count(Reg)) {
2478 if (
Reg.isPhysical()) {
2480 bool Bad = !isReserved(Reg);
2485 if (regsLive.count(
SubReg)) {
2497 if (!MOP.isReg() || !MOP.isImplicit())
2500 if (!MOP.getReg().isPhysical())
2508 report(
"Using an undefined physical register", MO, MONum);
2509 }
else if (
MRI->def_empty(Reg)) {
2510 report(
"Reading virtual register without a def", MO, MONum);
2512 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2516 if (MInfo.regsKilled.count(Reg))
2517 report(
"Using a killed virtual register", MO, MONum);
2518 else if (!
MI->isPHI())
2519 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
2528 addRegWithSubRegs(regsDead, Reg);
2530 addRegWithSubRegs(regsDefined, Reg);
2533 if (
MRI->isSSA() &&
Reg.isVirtual() &&
2534 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
2535 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2542 if (
Reg.isVirtual()) {
2543 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2547 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2548 :
MRI->getMaxLaneMaskForVReg(Reg);
2550 if ((SR.LaneMask & MOMask).none())
2552 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg,
true, SR.LaneMask);
2564void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2565 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2566 set_union(MInfo.regsKilled, regsKilled);
2567 set_subtract(regsLive, regsKilled); regsKilled.clear();
2569 while (!regMasks.empty()) {
2572 if (
Reg.isPhysical() &&
2574 regsDead.push_back(Reg);
2577 set_union(regsLive, regsDefined); regsDefined.clear();
2582 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2587 if (!(stop > lastIndex)) {
2588 report(
"Block ends before last instruction index",
MBB);
2589 errs() <<
"Block ends at " << stop
2590 <<
" last instruction was at " << lastIndex <<
'\n';
2605 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2607 filterAndAdd(FromRegSet, VRegsBuffer);
2612 template <
typename RegSetT>
2613 bool filterAndAdd(
const RegSetT &FromRegSet,
2615 unsigned SparseUniverse = Sparse.size();
2616 unsigned NewSparseUniverse = SparseUniverse;
2617 unsigned NewDenseSize =
Dense.size();
2618 size_t Begin = ToVRegs.
size();
2620 if (!
Reg.isVirtual())
2623 if (
Index < SparseUniverseMax) {
2624 if (
Index < SparseUniverse && Sparse.test(
Index))
2626 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
2634 size_t End = ToVRegs.
size();
2641 Sparse.resize(NewSparseUniverse);
2642 Dense.reserve(NewDenseSize);
2643 for (
unsigned I = Begin;
I < End; ++
I) {
2646 if (
Index < SparseUniverseMax)
2655 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2675class FilteringVRegSet {
2682 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
2687 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
2690 return Filter.filterAndAdd(RS, VRegs);
2695 size_t size()
const {
return VRegs.
size(); }
2702void MachineVerifier::calcRegsPassed() {
2709 FilteringVRegSet VRegs;
2710 BBInfo &
Info = MBBInfoMap[MB];
2713 VRegs.addToFilter(
Info.regsKilled);
2714 VRegs.addToFilter(
Info.regsLiveOut);
2716 const BBInfo &PredInfo = MBBInfoMap[Pred];
2717 if (!PredInfo.reachable)
2720 VRegs.add(PredInfo.regsLiveOut);
2721 VRegs.add(PredInfo.vregsPassed);
2723 Info.vregsPassed.reserve(VRegs.size());
2724 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2731void MachineVerifier::calcRegsRequired() {
2734 for (
const auto &
MBB : *MF) {
2735 BBInfo &MInfo = MBBInfoMap[&
MBB];
2737 BBInfo &PInfo = MBBInfoMap[Pred];
2738 if (PInfo.addRequired(MInfo.vregsLiveIn))
2744 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
2746 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
2753 BBInfo &PInfo = MBBInfoMap[Pred];
2754 if (PInfo.addRequired(Reg))
2762 while (!todo.
empty()) {
2765 BBInfo &MInfo = MBBInfoMap[
MBB];
2769 BBInfo &SInfo = MBBInfoMap[Pred];
2770 if (SInfo.addRequired(MInfo.vregsRequired))
2779 BBInfo &MInfo = MBBInfoMap[&
MBB];
2789 report(
"Expected first PHI operand to be a register def", &MODef, 0);
2794 report(
"Unexpected flag on PHI operand", &MODef, 0);
2797 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
2799 for (
unsigned I = 1,
E = Phi.getNumOperands();
I !=
E;
I += 2) {
2802 report(
"Expected PHI operand to be a register", &MO0,
I);
2807 report(
"Unexpected flag on PHI operand", &MO0,
I);
2811 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
2817 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
2821 if (MInfo.reachable) {
2823 BBInfo &PrInfo = MBBInfoMap[&Pre];
2824 if (!MO0.
isUndef() && PrInfo.reachable &&
2825 !PrInfo.isLiveOut(MO0.
getReg()))
2826 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
2831 if (MInfo.reachable) {
2833 if (!seen.
count(Pred)) {
2834 report(
"Missing PHI operand", &Phi);
2836 <<
" is a predecessor according to the CFG.\n";
2843void MachineVerifier::visitMachineFunctionAfter() {
2853 for (
const auto &
MBB : *MF) {
2854 BBInfo &MInfo = MBBInfoMap[&
MBB];
2855 for (
Register VReg : MInfo.vregsRequired)
2856 if (MInfo.regsKilled.count(VReg)) {
2857 report(
"Virtual register killed in block, but needed live out.", &
MBB);
2859 <<
" is used after the block.\n";
2864 BBInfo &MInfo = MBBInfoMap[&MF->front()];
2865 for (
Register VReg : MInfo.vregsRequired) {
2866 report(
"Virtual register defs don't dominate all uses.", MF);
2867 report_context_vreg(VReg);
2872 verifyLiveVariables();
2874 verifyLiveIntervals();
2883 if (
MRI->tracksLiveness())
2884 for (
const auto &
MBB : *MF)
2888 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2891 BBInfo &PInfo = MBBInfoMap[Pred];
2892 if (!PInfo.regsLiveOut.count(LiveInReg)) {
2893 report(
"Live in register not found to be live out from predecessor.",
2895 errs() <<
TRI->getName(LiveInReg)
2896 <<
" not found to be live out from "
2902 for (
auto CSInfo : MF->getCallSitesInfo())
2903 if (!CSInfo.first->isCall())
2904 report(
"Call site info referencing instruction that is not call", MF);
2908 if (MF->getFunction().getSubprogram()) {
2910 for (
const auto &
MBB : *MF) {
2911 for (
const auto &
MI :
MBB) {
2912 if (
auto Num =
MI.peekDebugInstrNum()) {
2915 report(
"Instruction has a duplicated value tracking number", &
MI);
2922void MachineVerifier::verifyLiveVariables() {
2923 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
2924 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
2927 for (
const auto &
MBB : *MF) {
2928 BBInfo &MInfo = MBBInfoMap[&
MBB];
2931 if (MInfo.vregsRequired.count(Reg)) {
2933 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
2935 <<
" must be live through the block.\n";
2939 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
2941 <<
" is not needed live through the block.\n";
2948void MachineVerifier::verifyLiveIntervals() {
2949 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
2950 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
2954 if (
MRI->reg_nodbg_empty(Reg))
2958 report(
"Missing live interval for virtual register", MF);
2964 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
2965 verifyLiveInterval(LI);
2969 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
2971 verifyLiveRange(*LR, i);
2974void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
2983 report(
"Value not live at VNInfo def and not marked unused", MF);
2984 report_context(LR, Reg, LaneMask);
2985 report_context(*VNI);
2989 if (DefVNI != VNI) {
2990 report(
"Live segment at def has different VNInfo", MF);
2991 report_context(LR, Reg, LaneMask);
2992 report_context(*VNI);
2998 report(
"Invalid VNInfo definition index", MF);
2999 report_context(LR, Reg, LaneMask);
3000 report_context(*VNI);
3006 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
3007 report_context(LR, Reg, LaneMask);
3008 report_context(*VNI);
3016 report(
"No instruction at VNInfo def index",
MBB);
3017 report_context(LR, Reg, LaneMask);
3018 report_context(*VNI);
3023 bool hasDef =
false;
3024 bool isEarlyClobber =
false;
3026 if (!MOI->isReg() || !MOI->isDef())
3028 if (
Reg.isVirtual()) {
3029 if (MOI->getReg() != Reg)
3032 if (!MOI->getReg().isPhysical() || !
TRI->hasRegUnit(MOI->getReg(), Reg))
3035 if (LaneMask.
any() &&
3036 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3039 if (MOI->isEarlyClobber())
3040 isEarlyClobber =
true;
3044 report(
"Defining instruction does not modify register",
MI);
3045 report_context(LR, Reg, LaneMask);
3046 report_context(*VNI);
3051 if (isEarlyClobber) {
3053 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3054 report_context(LR, Reg, LaneMask);
3055 report_context(*VNI);
3058 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3059 report_context(LR, Reg, LaneMask);
3060 report_context(*VNI);
3065void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3071 assert(VNI &&
"Live segment has no valno");
3074 report(
"Foreign valno in live segment", MF);
3075 report_context(LR, Reg, LaneMask);
3077 report_context(*VNI);
3081 report(
"Live segment valno is marked unused", MF);
3082 report_context(LR, Reg, LaneMask);
3088 report(
"Bad start of live segment, no basic block", MF);
3089 report_context(LR, Reg, LaneMask);
3095 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3096 report_context(LR, Reg, LaneMask);
3103 report(
"Bad end of live segment, no basic block", MF);
3104 report_context(LR, Reg, LaneMask);
3122 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3123 report_context(LR, Reg, LaneMask);
3130 report(
"Live segment ends at B slot of an instruction", EndMBB);
3131 report_context(LR, Reg, LaneMask);
3139 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3140 report_context(LR, Reg, LaneMask);
3149 if (MF->getProperties().hasProperty(
3152 if (
I+1 == LR.
end() || (
I+1)->start != S.
end) {
3153 report(
"Live segment ending at early clobber slot must be "
3154 "redefined by an EC def in the same instruction", EndMBB);
3155 report_context(LR, Reg, LaneMask);
3162 if (
Reg.isVirtual()) {
3165 bool hasRead =
false;
3166 bool hasSubRegDef =
false;
3167 bool hasDeadDef =
false;
3169 if (!MOI->isReg() || MOI->getReg() != Reg)
3171 unsigned Sub = MOI->getSubReg();
3176 hasSubRegDef =
true;
3185 if (LaneMask.
any() && (LaneMask & SLM).none())
3187 if (MOI->readsReg())
3194 if (LaneMask.
none() && !hasDeadDef) {
3195 report(
"Instruction ending live segment on dead slot has no dead flag",
3197 report_context(LR, Reg, LaneMask);
3204 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
3206 report(
"Instruction ending live segment doesn't read the register",
3208 report_context(LR, Reg, LaneMask);
3227 if (LaneMask.
any()) {
3235 if (!
Reg.isVirtual() && MFI->isEHPad()) {
3236 if (&*MFI == EndMBB)
3250 if (MFI->isEHPad()) {
3264 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3267 report(
"Register not marked live out of predecessor", Pred);
3268 report_context(LR, Reg, LaneMask);
3269 report_context(*VNI);
3277 if (!IsPHI && PVNI != VNI) {
3278 report(
"Different value live out of predecessor", Pred);
3279 report_context(LR, Reg, LaneMask);
3280 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3286 if (&*MFI == EndMBB)
3295 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3298 verifyLiveRangeSegment(LR,
I, Reg, LaneMask);
3301void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3304 verifyLiveRange(LI, Reg);
3309 if ((Mask & SR.LaneMask).any()) {
3310 report(
"Lane masks of sub ranges overlap in live interval", MF);
3313 if ((SR.LaneMask & ~MaxMask).any()) {
3314 report(
"Subrange lanemask is invalid", MF);
3318 report(
"Subrange must not be empty", MF);
3319 report_context(SR, LI.
reg(), SR.LaneMask);
3321 Mask |= SR.LaneMask;
3322 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3324 report(
"A Subrange is not covered by the main range", MF);
3331 unsigned NumComp = ConEQ.Classify(LI);
3333 report(
"Multiple connected components in live interval", MF);
3335 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3336 errs() << comp <<
": valnos";
3338 if (comp == ConEQ.getEqClass(
I))
3339 errs() <<
' ' <<
I->id;
3351 struct StackStateOfBB {
3352 StackStateOfBB() =
default;
3353 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3354 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3355 ExitIsSetup(ExitSetup) {}
3360 bool EntryIsSetup =
false;
3361 bool ExitIsSetup =
false;
3369void MachineVerifier::verifyStackFrame() {
3370 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3371 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3372 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3376 SPState.
resize(MF->getNumBlockIDs());
3383 DFI != DFE; ++DFI) {
3386 StackStateOfBB BBState;
3388 if (DFI.getPathLength() >= 2) {
3391 "DFS stack predecessor is already visited.\n");
3392 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3393 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3394 BBState.ExitValue = BBState.EntryValue;
3395 BBState.ExitIsSetup = BBState.EntryIsSetup;
3399 for (
const auto &
I : *
MBB) {
3400 if (
I.getOpcode() == FrameSetupOpcode) {
3401 if (BBState.ExitIsSetup)
3402 report(
"FrameSetup is after another FrameSetup", &
I);
3403 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3404 BBState.ExitIsSetup =
true;
3407 if (
I.getOpcode() == FrameDestroyOpcode) {
3408 int Size =
TII->getFrameTotalSize(
I);
3409 if (!BBState.ExitIsSetup)
3410 report(
"FrameDestroy is not after a FrameSetup", &
I);
3411 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3413 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3414 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3415 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3416 << AbsSPAdj <<
">.\n";
3418 BBState.ExitValue +=
Size;
3419 BBState.ExitIsSetup =
false;
3427 if (Reachable.
count(Pred) &&
3428 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3429 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3430 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3432 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3433 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3435 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3442 if (Reachable.
count(Succ) &&
3443 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3444 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3445 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3447 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3448 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3450 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3456 if (BBState.ExitIsSetup)
3457 report(
"A return block ends with a FrameSetup.",
MBB);
3458 if (BBState.ExitValue)
3459 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
SmallVector< MachineOperand, 4 > Cond
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
modulo schedule Modulo Schedule test pass
return ToRemove size() > 0
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr unsigned getAddressSpace() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
const char * getName() const
Get a user friendly name of this register bank.
Wrapper class representing virtual and physical registers.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
auto reverse(ContainerTy &&C)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.