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86 struct MachineVerifier {
87 MachineVerifier(
Pass *
pass,
const char *
b) : PASS(
pass), Banner(
b) {}
102 bool isFunctionRegBankSelected;
103 bool isFunctionSelected;
113 BlockSet FunctionBlocks;
117 RegVector regsDefined, regsDead, regsKilled;
118 RegMaskVector regMasks;
123 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
125 if (
Reg.isPhysical())
131 bool reachable =
false;
152 RegSet vregsRequired;
155 BlockSet Preds, Succs;
162 if (!
Reg.isVirtual())
164 if (regsLiveOut.count(
Reg))
166 return vregsRequired.insert(
Reg).second;
170 bool addRequired(
const RegSet &RS) {
171 bool Changed =
false;
173 Changed |= addRequired(
Reg);
178 bool addRequired(
const RegMap &
RM) {
179 bool Changed =
false;
180 for (
const auto &
I :
RM)
181 Changed |= addRequired(
I.first);
187 return regsLiveOut.count(
Reg) || vregsPassed.count(
Reg);
195 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
209 void visitMachineFunctionBefore();
216 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
219 void visitMachineFunctionAfter();
224 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
232 void report_context(
const VNInfo &VNI)
const;
233 void report_context(
SlotIndex Pos)
const;
234 void report_context(
MCPhysReg PhysReg)
const;
235 void report_context_liverange(
const LiveRange &LR)
const;
236 void report_context_lanemask(
LaneBitmask LaneMask)
const;
237 void report_context_vreg(
Register VReg)
const;
238 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
249 Register VRegOrUnit,
bool SubRangeCheck =
false,
253 void calcRegsPassed();
256 void calcRegsRequired();
257 void verifyLiveVariables();
258 void verifyLiveIntervals();
262 void verifyLiveRangeSegment(
const LiveRange &,
268 void verifyStackFrame();
270 void verifySlotIndexes()
const;
277 const std::string Banner;
279 MachineVerifierPass(std::string banner = std::string())
290 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
302 "Verify generated machine code",
false,
false)
305 return new MachineVerifierPass(Banner);
309 const std::string &Banner,
316 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
324 unsigned FoundErrors = MachineVerifier(
p, Banner).
verify(MF);
325 if (AbortOnErrors && FoundErrors)
327 return FoundErrors == 0;
330 void MachineVerifier::verifySlotIndexes()
const {
331 if (Indexes ==
nullptr)
338 assert(!Last.isValid() ||
I->first > Last);
350 report(
"Function has NoVRegs property but there are VReg operands", &MF);
368 if (isFunctionFailedISel)
391 verifyProperties(MF);
393 visitMachineFunctionBefore();
395 visitMachineBasicBlockBefore(&
MBB);
399 bool InBundle =
false;
402 if (
MI.getParent() != &
MBB) {
403 report(
"Bad instruction parent pointer", &
MBB);
404 errs() <<
"Instruction: " <<
MI;
409 if (InBundle && !
MI.isBundledWithPred())
410 report(
"Missing BundledPred flag, "
411 "BundledSucc was set on predecessor",
413 if (!InBundle &&
MI.isBundledWithPred())
414 report(
"BundledPred flag is set, "
415 "but BundledSucc not set on predecessor",
419 if (!
MI.isInsideBundle()) {
421 visitMachineBundleAfter(CurBundle);
423 visitMachineBundleBefore(CurBundle);
424 }
else if (!CurBundle)
425 report(
"No bundle header", &
MI);
426 visitMachineInstrBefore(&
MI);
427 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
429 if (
Op.getParent() != &
MI) {
432 report(
"Instruction has operand with wrong parent set", &
MI);
435 visitMachineOperand(&
Op,
I);
439 InBundle =
MI.isBundledWithSucc();
442 visitMachineBundleAfter(CurBundle);
444 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
445 visitMachineBasicBlockAfter(&
MBB);
447 visitMachineFunctionAfter();
460 void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
463 if (!foundErrors++) {
465 errs() <<
"# " << Banner <<
'\n';
466 if (LiveInts !=
nullptr)
471 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
472 <<
"- function: " << MF->
getName() <<
"\n";
486 void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
488 report(msg,
MI->getParent());
489 errs() <<
"- instruction: ";
495 void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
496 unsigned MONum,
LLT MOVRegType) {
499 errs() <<
"- operand " << MONum <<
": ";
505 report(Msg.
str().c_str(),
MI);
508 void MachineVerifier::report_context(
SlotIndex Pos)
const {
509 errs() <<
"- at: " << Pos <<
'\n';
512 void MachineVerifier::report_context(
const LiveInterval &LI)
const {
513 errs() <<
"- interval: " << LI <<
'\n';
518 report_context_liverange(LR);
519 report_context_vreg_regunit(VRegUnit);
521 report_context_lanemask(LaneMask);
525 errs() <<
"- segment: " <<
S <<
'\n';
528 void MachineVerifier::report_context(
const VNInfo &VNI)
const {
529 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
532 void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
533 errs() <<
"- liverange: " << LR <<
'\n';
536 void MachineVerifier::report_context(
MCPhysReg PReg)
const {
540 void MachineVerifier::report_context_vreg(
Register VReg)
const {
544 void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
546 report_context_vreg(VRegOrUnit);
552 void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
557 BBInfo &MInfo = MBBInfoMap[
MBB];
558 if (!MInfo.reachable) {
559 MInfo.reachable =
true;
565 void MachineVerifier::visitMachineFunctionBefore() {
571 markReachable(&MF->
front());
574 FunctionBlocks.clear();
575 for (
const auto &
MBB : *MF) {
576 FunctionBlocks.insert(&
MBB);
577 BBInfo &MInfo = MBBInfoMap[&
MBB];
581 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
585 report(
"MBB has duplicate entries in its successor list.", &
MBB);
597 FirstTerminator =
nullptr;
598 FirstNonPHI =
nullptr;
600 if (!MF->getProperties().hasProperty(
605 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
607 report(
"MBB has allocatable live-in, but isn't entry or landing-pad.",
MBB);
608 report_context(LI.PhysReg);
617 LandingPadSuccs.
insert(succ);
618 if (!FunctionBlocks.count(succ))
619 report(
"MBB has successor that isn't part of the function.",
MBB);
620 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
621 report(
"Inconsistent CFG",
MBB);
622 errs() <<
"MBB is not in the predecessor list of the successor "
629 if (!FunctionBlocks.count(Pred))
630 report(
"MBB has predecessor that isn't part of the function.",
MBB);
631 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
632 report(
"Inconsistent CFG",
MBB);
633 errs() <<
"MBB is not in the successor list of the predecessor "
641 if (LandingPadSuccs.
size() > 1 &&
644 BB && isa<SwitchInst>(
BB->getTerminator())) &&
646 report(
"MBB has more than one landing pad successor",
MBB);
659 report(
"MBB exits via unconditional fall-through but ends with a "
660 "barrier instruction!",
MBB);
663 report(
"MBB exits via unconditional fall-through but has a condition!",
666 }
else if (TBB && !FBB &&
Cond.empty()) {
669 report(
"MBB exits via unconditional branch but doesn't contain "
670 "any instructions!",
MBB);
672 report(
"MBB exits via unconditional branch but doesn't end with a "
673 "barrier instruction!",
MBB);
675 report(
"MBB exits via unconditional branch but the branch isn't a "
676 "terminator instruction!",
MBB);
678 }
else if (TBB && !FBB && !
Cond.empty()) {
681 report(
"MBB exits via conditional branch/fall-through but doesn't "
682 "contain any instructions!",
MBB);
684 report(
"MBB exits via conditional branch/fall-through but ends with a "
685 "barrier instruction!",
MBB);
687 report(
"MBB exits via conditional branch/fall-through but the branch "
688 "isn't a terminator instruction!",
MBB);
690 }
else if (TBB && FBB) {
694 report(
"MBB exits via conditional branch/branch but doesn't "
695 "contain any instructions!",
MBB);
697 report(
"MBB exits via conditional branch/branch but doesn't end with a "
698 "barrier instruction!",
MBB);
700 report(
"MBB exits via conditional branch/branch but the branch "
701 "isn't a terminator instruction!",
MBB);
704 report(
"MBB exits via conditional branch/branch but there's no "
708 report(
"analyzeBranch returned invalid data!",
MBB);
714 report(
"MBB exits via jump or conditional branch, but its target isn't a "
718 report(
"MBB exits via conditional branch, but its target isn't a CFG "
725 bool Fallthrough = !TBB || (!
Cond.empty() && !FBB);
730 if (!
Cond.empty() && !FBB) {
733 report(
"MBB conditionally falls through out of function!",
MBB);
735 report(
"MBB exits via conditional branch/fall-through but the CFG "
736 "successors don't match the actual successors!",
743 if (SuccMBB == TBB || SuccMBB == FBB)
751 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
753 report(
"MBB has unexpected successors which are not branch targets, "
754 "fallthrough, EHPads, or inlineasm_br targets.",
763 report(
"MBB live-in list contains non-physical register",
MBB);
787 void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
790 if (!(idx > lastIndex)) {
791 report(
"Instruction index out of order",
MI);
792 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
798 if (
MI->isTerminator()) {
799 if (!FirstTerminator)
800 FirstTerminator =
MI;
801 }
else if (FirstTerminator) {
802 report(
"Non-terminator instruction after the first terminator",
MI);
803 errs() <<
"First terminator was:\t" << *FirstTerminator;
811 if (
MI->getNumOperands() < 2) {
812 report(
"Too few operands on inline asm",
MI);
815 if (!
MI->getOperand(0).isSymbol())
816 report(
"Asm string must be an external symbol",
MI);
817 if (!
MI->getOperand(1).isImm())
818 report(
"Asm flags must be an immediate",
MI);
822 if (!isUInt<6>(
MI->getOperand(1).getImm()))
823 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
829 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
837 if (OpNo >
MI->getNumOperands())
838 report(
"Missing operands in last group",
MI);
841 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
845 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; ++OpNo) {
848 report(
"Expected implicit register after groups", &MO, OpNo);
855 bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
858 report(
"operand types must be all-vector or all-scalar",
MI);
868 report(
"operand types must preserve number of vector elements",
MI);
875 void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
876 if (isFunctionSelected)
877 report(
"Unexpected generic instruction in a Selected function",
MI);
880 unsigned NumOps =
MI->getNumOperands();
883 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
893 report(
"Branch instruction is missing a basic block operand or "
894 "isIndirectBranch property",
912 report(
"generic instruction must use register operands",
MI);
922 if (!Types[TypeIdx].isValid())
923 Types[TypeIdx] = OpTy;
924 else if (Types[TypeIdx] != OpTy)
925 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
928 report(
"Generic instruction is missing a virtual register type", MO,
I);
933 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
936 report(
"Generic instruction cannot have physical register", MO,
I);
948 unsigned Opc =
MI->getOpcode();
950 case TargetOpcode::G_ASSERT_SEXT:
951 case TargetOpcode::G_ASSERT_ZEXT: {
952 std::string OpcName =
953 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
954 if (!
MI->getOperand(2).isImm()) {
955 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
962 int64_t Imm =
MI->getOperand(2).getImm();
964 report(
Twine(OpcName,
" size must be >= 1"),
MI);
969 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
975 Twine(OpcName,
" source and destination register banks must match"),
982 Twine(OpcName,
" source and destination register classes must match"),
988 case TargetOpcode::G_CONSTANT:
989 case TargetOpcode::G_FCONSTANT: {
992 report(
"Instruction cannot use a vector result type",
MI);
994 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
995 if (!
MI->getOperand(1).isCImm()) {
996 report(
"G_CONSTANT operand must be cimm",
MI);
1002 report(
"inconsistent constant size",
MI);
1004 if (!
MI->getOperand(1).isFPImm()) {
1005 report(
"G_FCONSTANT operand must be fpimm",
MI);
1012 report(
"inconsistent constant size",
MI);
1018 case TargetOpcode::G_LOAD:
1019 case TargetOpcode::G_STORE:
1020 case TargetOpcode::G_ZEXTLOAD:
1021 case TargetOpcode::G_SEXTLOAD: {
1025 report(
"Generic memory instruction must access a pointer",
MI);
1029 if (!
MI->hasOneMemOperand()) {
1030 report(
"Generic instruction accessing memory must have one mem operand",
1034 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1035 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1037 report(
"Generic extload must have a narrower memory type",
MI);
1038 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1040 report(
"load memory size cannot exceed result size",
MI);
1041 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1043 report(
"store memory size cannot exceed value size",
MI);
1049 case TargetOpcode::G_PHI: {
1055 LLT Ty = MRI->getType(MO.getReg());
1056 if (!Ty.isValid() || (Ty != DstTy))
1060 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1065 case TargetOpcode::G_BITCAST: {
1072 report(
"bitcast cannot convert between pointers and other types",
MI);
1075 report(
"bitcast sizes must match",
MI);
1078 report(
"bitcast must change the type",
MI);
1082 case TargetOpcode::G_INTTOPTR:
1083 case TargetOpcode::G_PTRTOINT:
1084 case TargetOpcode::G_ADDRSPACE_CAST: {
1090 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1095 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1097 report(
"inttoptr result type must be a pointer",
MI);
1099 report(
"inttoptr source type must not be a pointer",
MI);
1100 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1102 report(
"ptrtoint source type must be a pointer",
MI);
1104 report(
"ptrtoint result type must not be a pointer",
MI);
1106 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1108 report(
"addrspacecast types must be pointers",
MI);
1111 report(
"addrspacecast must convert different address spaces",
MI);
1117 case TargetOpcode::G_PTR_ADD: {
1125 report(
"gep first operand must be a pointer",
MI);
1128 report(
"gep offset operand must not be a pointer",
MI);
1133 case TargetOpcode::G_PTRMASK: {
1141 report(
"ptrmask result type must be a pointer",
MI);
1144 report(
"ptrmask mask type must be an integer",
MI);
1146 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1149 case TargetOpcode::G_SEXT:
1150 case TargetOpcode::G_ZEXT:
1151 case TargetOpcode::G_ANYEXT:
1152 case TargetOpcode::G_TRUNC:
1153 case TargetOpcode::G_FPEXT:
1154 case TargetOpcode::G_FPTRUNC: {
1169 report(
"Generic extend/truncate can not operate on pointers",
MI);
1171 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1175 switch (
MI->getOpcode()) {
1177 if (DstSize <= SrcSize)
1178 report(
"Generic extend has destination type no larger than source",
MI);
1180 case TargetOpcode::G_TRUNC:
1181 case TargetOpcode::G_FPTRUNC:
1182 if (DstSize >= SrcSize)
1183 report(
"Generic truncate has destination type no smaller than source",
1189 case TargetOpcode::G_SELECT: {
1197 verifyVectorElementMatch(SelTy, CondTy,
MI);
1200 case TargetOpcode::G_MERGE_VALUES: {
1208 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1210 const unsigned NumOps =
MI->getNumOperands();
1212 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1214 for (
unsigned I = 2;
I != NumOps; ++
I) {
1216 report(
"G_MERGE_VALUES source types do not match",
MI);
1221 case TargetOpcode::G_UNMERGE_VALUES: {
1225 for (
unsigned i = 0;
i <
MI->getNumOperands()-1; ++
i) {
1227 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1231 report(
"G_UNMERGE_VALUES source operand does not cover dest operands",
1236 case TargetOpcode::G_BUILD_VECTOR: {
1242 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1247 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1250 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1252 for (
unsigned i = 2;
i <
MI->getNumOperands(); ++
i) {
1255 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1260 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1266 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1268 for (
unsigned i = 2;
i <
MI->getNumOperands(); ++
i) {
1271 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1275 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1280 case TargetOpcode::G_CONCAT_VECTORS: {
1286 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1289 if (
MI->getNumOperands() < 3)
1290 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1292 for (
unsigned i = 2;
i <
MI->getNumOperands(); ++
i) {
1295 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1299 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1302 case TargetOpcode::G_ICMP:
1303 case TargetOpcode::G_FCMP: {
1309 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1313 case TargetOpcode::G_EXTRACT: {
1315 if (!
SrcOp.isReg()) {
1316 report(
"extract source must be a register",
MI);
1321 if (!OffsetOp.
isImm()) {
1322 report(
"extract offset must be a constant",
MI);
1328 if (SrcSize == DstSize)
1329 report(
"extract source must be larger than result",
MI);
1331 if (DstSize + OffsetOp.
getImm() > SrcSize)
1332 report(
"extract reads past end of register",
MI);
1335 case TargetOpcode::G_INSERT: {
1337 if (!
SrcOp.isReg()) {
1338 report(
"insert source must be a register",
MI);
1343 if (!OffsetOp.
isImm()) {
1344 report(
"insert offset must be a constant",
MI);
1351 if (DstSize <= SrcSize)
1352 report(
"inserted size must be smaller than total register",
MI);
1354 if (SrcSize + OffsetOp.
getImm() > DstSize)
1355 report(
"insert writes past end of register",
MI);
1359 case TargetOpcode::G_JUMP_TABLE: {
1360 if (!
MI->getOperand(1).isJTI())
1361 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1364 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1367 case TargetOpcode::G_BRJT: {
1369 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1371 if (!
MI->getOperand(1).isJTI())
1372 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1374 const auto &IdxOp =
MI->getOperand(2);
1376 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1379 case TargetOpcode::G_INTRINSIC:
1380 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1385 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1389 bool NoSideEffects =
MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1391 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1396 if (NoSideEffects && DeclHasSideEffects) {
1397 report(
"G_INTRINSIC used with intrinsic that accesses memory",
MI);
1400 if (!NoSideEffects && !DeclHasSideEffects) {
1401 report(
"G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic",
MI);
1408 case TargetOpcode::G_SEXT_INREG: {
1409 if (!
MI->getOperand(2).isImm()) {
1410 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1415 int64_t Imm =
MI->getOperand(2).getImm();
1417 report(
"G_SEXT_INREG size must be >= 1",
MI);
1419 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1422 case TargetOpcode::G_SHUFFLE_VECTOR: {
1425 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1433 if (Src0Ty != Src1Ty)
1434 report(
"Source operands must be the same type",
MI);
1437 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1446 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1447 report(
"Wrong result type for shufflemask",
MI);
1449 for (
int Idx : MaskIdxes) {
1453 if (Idx >= 2 * SrcNumElts)
1454 report(
"Out of bounds shuffle index",
MI);
1459 case TargetOpcode::G_DYN_STACKALLOC: {
1465 report(
"dst operand 0 must be a pointer type",
MI);
1470 report(
"src operand 1 must be a scalar reg type",
MI);
1474 if (!AlignOp.
isImm()) {
1475 report(
"src operand 2 must be an immediate type",
MI);
1480 case TargetOpcode::G_MEMCPY:
1481 case TargetOpcode::G_MEMMOVE: {
1483 if (MMOs.
size() != 2) {
1484 report(
"memcpy/memmove must have 2 memory operands",
MI);
1490 report(
"wrong memory operand types",
MI);
1494 if (MMOs[0]->getSize() != MMOs[1]->getSize())
1495 report(
"inconsistent memory operand sizes",
MI);
1501 report(
"memory instruction operand must be a pointer",
MI);
1506 report(
"inconsistent store address space",
MI);
1508 report(
"inconsistent load address space",
MI);
1512 case TargetOpcode::G_BZERO:
1513 case TargetOpcode::G_MEMSET: {
1515 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1516 if (MMOs.
size() != 1) {
1517 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1522 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1528 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1533 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1537 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1538 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1543 report(
"Vector reduction requires a scalar destination type",
MI);
1545 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1547 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1550 case TargetOpcode::G_VECREDUCE_FADD:
1551 case TargetOpcode::G_VECREDUCE_FMUL:
1552 case TargetOpcode::G_VECREDUCE_FMAX:
1553 case TargetOpcode::G_VECREDUCE_FMIN:
1554 case TargetOpcode::G_VECREDUCE_ADD:
1555 case TargetOpcode::G_VECREDUCE_MUL:
1556 case TargetOpcode::G_VECREDUCE_AND:
1557 case TargetOpcode::G_VECREDUCE_OR:
1558 case TargetOpcode::G_VECREDUCE_XOR:
1559 case TargetOpcode::G_VECREDUCE_SMAX:
1560 case TargetOpcode::G_VECREDUCE_SMIN:
1561 case TargetOpcode::G_VECREDUCE_UMAX:
1562 case TargetOpcode::G_VECREDUCE_UMIN: {
1566 report(
"Vector reduction requires a scalar destination type",
MI);
1568 report(
"Vector reduction requires vector source=",
MI);
1572 case TargetOpcode::G_SBFX:
1573 case TargetOpcode::G_UBFX: {
1576 report(
"Bitfield extraction is not supported on vectors",
MI);
1581 case TargetOpcode::G_ROTR:
1582 case TargetOpcode::G_ROTL: {
1586 report(
"Rotate requires operands to be either all scalars or all vectors",
1598 void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
1601 report(
"Too few operands",
MI);
1603 <<
MI->getNumOperands() <<
" given.\n";
1607 if (MF->getProperties().hasProperty(
1609 report(
"Found PHI instruction with NoPHIs property set",
MI);
1612 report(
"Found PHI instruction after non-PHI",
MI);
1613 }
else if (FirstNonPHI ==
nullptr)
1617 if (
MI->isInlineAsm())
1618 verifyInlineAsm(
MI);
1621 if (
TII->isUnspillableTerminator(
MI)) {
1622 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
1623 report(
"Unspillable Terminator does not define a reg",
MI);
1625 if (
Def.isVirtual() &&
1627 report(
"Unspillable Terminator expected to have at most one use!",
MI);
1633 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
1634 if (!
MI->getDebugLoc())
1635 report(
"Missing DebugLoc for debug instruction",
MI);
1639 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
1640 report(
"Metadata instruction should not have a value tracking number",
MI);
1644 if (
Op->isLoad() && !
MI->mayLoad())
1645 report(
"Missing mayLoad flag",
MI);
1646 if (
Op->isStore() && !
MI->mayStore())
1647 report(
"Missing mayStore flag",
MI);
1654 if (
MI->isDebugInstr()) {
1656 report(
"Debug instruction has a slot index",
MI);
1657 }
else if (
MI->isInsideBundle()) {
1659 report(
"Instruction inside bundle has a slot index",
MI);
1662 report(
"Missing slot index",
MI);
1668 verifyPreISelGenericInstruction(
MI);
1677 switch (
MI->getOpcode()) {
1678 case TargetOpcode::COPY: {
1687 if (SrcTy != DstTy) {
1688 report(
"Copy Instruction is illegal with mismatching types",
MI);
1689 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
1697 assert(SrcSize &&
"Expecting size here");
1698 assert(DstSize &&
"Expecting size here");
1699 if (SrcSize != DstSize)
1700 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
1701 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
1702 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
1708 case TargetOpcode::STATEPOINT: {
1710 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
1711 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
1712 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1713 report(
"meta operands to STATEPOINT not constant!",
MI);
1717 auto VerifyStackMapConstant = [&](
unsigned Offset) {
1718 if (
Offset >=
MI->getNumOperands()) {
1719 report(
"stack map constant to STATEPOINT is out of range!",
MI);
1722 if (!
MI->getOperand(
Offset - 1).isImm() ||
1723 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
1725 report(
"stack map constant to STATEPOINT not well formed!",
MI);
1727 VerifyStackMapConstant(SO.getCCIdx());
1728 VerifyStackMapConstant(SO.getFlagsIdx());
1729 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1730 VerifyStackMapConstant(SO.getNumGCPtrIdx());
1731 VerifyStackMapConstant(SO.getNumAllocaIdx());
1732 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1736 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1737 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1738 for (
unsigned Idx = 0; Idx <
MI->getNumDefs(); Idx++) {
1740 if (!
MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
1741 report(
"STATEPOINT defs expected to be tied",
MI);
1744 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1745 report(
"STATEPOINT def tied to non-gc operand",
MI);
1756 MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
1760 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
1761 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
1764 if (MONum < NumDefs) {
1767 report(
"Explicit definition must be a register", MO, MONum);
1769 report(
"Explicit definition marked as use", MO, MONum);
1771 report(
"Explicit definition marked as implicit", MO, MONum);
1780 report(
"Explicit operand marked as def", MO, MONum);
1782 report(
"Explicit operand marked as implicit", MO, MONum);
1788 report(
"Expected a register operand.", MO, MONum);
1792 !
TII->isPCRelRegisterOperandLegal(*MO)))
1793 report(
"Expected a non-register operand.", MO, MONum);
1800 report(
"Tied use must be a register", MO, MONum);
1802 report(
"Operand should be tied", MO, MONum);
1803 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
1804 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
1807 if (!MOTied.
isReg())
1808 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
1811 report(
"Tied physical registers must match.", &MOTied, TiedTo);
1814 report(
"Explicit operand should not be tied", MO, MONum);
1818 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
1827 checkLiveness(MO, MONum);
1831 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
1833 if (!OtherMO.
isReg())
1834 report(
"Must be tied to a register", MO, MONum);
1836 report(
"Missing tie flags on tied operand", MO, MONum);
1837 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
1838 report(
"Inconsistent tie links", MO, MONum);
1842 report(
"Explicit def tied to explicit use without tie constraint",
1846 report(
"Explicit def should be tied to implicit use", MO, MONum);
1859 if (MF->getProperties().hasProperty(
1861 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1862 Reg !=
MI->getOperand(DefIdx).getReg())
1863 report(
"Two-address instruction operands must be identical", MO, MONum);
1870 report(
"Illegal subregister index for physical register", MO, MONum);
1875 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
1876 if (!DRC->contains(
Reg)) {
1877 report(
"Illegal physical register for instruction", MO, MONum);
1885 report(
"isRenamable set on reserved register", MO, MONum);
1890 report(
"Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
1906 report(
"Generic virtual register use cannot be undef", MO, MONum);
1909 if (isFunctionSelected) {
1910 report(
"Generic virtual register invalid in a Selected function",
1918 report(
"Generic virtual register must have a valid type", MO,
1926 if (!RegBank && isFunctionRegBankSelected) {
1927 report(
"Generic virtual register must have a bank in a "
1928 "RegBankSelected function",
1934 if (RegBank && Ty.
isValid() &&
1936 report(
"Register bank is too small for virtual register", MO,
1938 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
1944 report(
"Generic virtual register does not allow subregister index", MO,
1954 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
1955 report(
"Virtual register does not match instruction constraint", MO,
1957 errs() <<
"Expect register class "
1959 TII->getRegClass(MCID, MONum,
TRI, *MF))
1960 <<
" but got nothing\n";
1970 report(
"Invalid subregister index for virtual register", MO, MONum);
1972 <<
" does not support subreg index " << SubIdx <<
"\n";
1976 report(
"Invalid register class for subregister index", MO, MONum);
1978 <<
" does not fully support subreg index " << SubIdx <<
"\n";
1984 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
1989 report(
"No largest legal super class exists.", MO, MONum);
1994 report(
"No matching super-reg register class.", MO, MONum);
1999 report(
"Illegal virtual register for instruction", MO, MONum);
2016 report(
"PHI operand is not in the CFG", MO, MONum);
2027 bool loads =
MI->mayLoad();
2032 for (
auto *MMO :
MI->memoperands()) {
2034 if (PSV ==
nullptr)
continue;
2036 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2037 if (
Value ==
nullptr)
continue;
2038 if (
Value->getFrameIndex() != FI)
continue;
2047 report(
"Missing fixed stack memoperand.",
MI);
2050 report(
"Instruction loads from dead spill slot", MO, MONum);
2051 errs() <<
"Live stack: " << LI <<
'\n';
2054 report(
"Instruction stores to dead spill slot", MO, MONum);
2055 errs() <<
"Live stack: " << LI <<
'\n';
2065 void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2074 report(
"No live segment at use", MO, MONum);
2075 report_context_liverange(LR);
2076 report_context_vreg_regunit(VRegOrUnit);
2077 report_context(UseIdx);
2080 report(
"Live range continues after kill flag", MO, MONum);
2081 report_context_liverange(LR);
2082 report_context_vreg_regunit(VRegOrUnit);
2084 report_context_lanemask(LaneMask);
2085 report_context(UseIdx);
2089 void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2096 assert(VNI &&
"NULL valno is not allowed");
2097 if (VNI->def != DefIdx) {
2098 report(
"Inconsistent valno->def", MO, MONum);
2099 report_context_liverange(LR);
2100 report_context_vreg_regunit(VRegOrUnit);
2102 report_context_lanemask(LaneMask);
2103 report_context(*VNI);
2104 report_context(DefIdx);
2107 report(
"No live segment at def", MO, MONum);
2108 report_context_liverange(LR);
2109 report_context_vreg_regunit(VRegOrUnit);
2111 report_context_lanemask(LaneMask);
2112 report_context(DefIdx);
2119 "Expecting a virtual register.");
2125 if (SubRangeCheck || MO->
getSubReg() == 0) {
2126 report(
"Live range continues after dead def flag", MO, MONum);
2127 report_context_liverange(LR);
2128 report_context_vreg_regunit(VRegOrUnit);
2130 report_context_lanemask(LaneMask);
2136 void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2143 addRegWithSubRegs(regsKilled,
Reg);
2149 report(
"Kill missing from LiveVariables", MO, MONum);
2156 if (
Reg.isPhysical() && !isReserved(
Reg)) {
2162 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2170 checkLivenessAtUse(MO, MONum, UseIdx, LI,
Reg);
2179 if ((MOMask & SR.LaneMask).none())
2181 checkLivenessAtUse(MO, MONum, UseIdx, SR,
Reg, SR.LaneMask);
2184 LiveInMask |= SR.LaneMask;
2187 if ((LiveInMask & MOMask).none()) {
2188 report(
"No live subrange at use", MO, MONum);
2190 report_context(UseIdx);
2194 report(
"Virtual register has no live interval", MO, MONum);
2200 if (!regsLive.count(
Reg)) {
2203 bool Bad = !isReserved(
Reg);
2208 if (regsLive.count(
SubReg)) {
2220 if (!MOP.isReg() || !MOP.isImplicit())
2231 report(
"Using an undefined physical register", MO, MONum);
2233 report(
"Reading virtual register without a def", MO, MONum);
2235 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2239 if (MInfo.regsKilled.count(
Reg))
2240 report(
"Using a killed virtual register", MO, MONum);
2241 else if (!
MI->isPHI())
2242 MInfo.vregsLiveIn.insert(std::make_pair(
Reg,
MI));
2251 addRegWithSubRegs(regsDead,
Reg);
2253 addRegWithSubRegs(regsDefined,
Reg);
2258 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2268 checkLivenessAtDef(MO, MONum, DefIdx, LI,
Reg);
2276 if ((SR.LaneMask & MOMask).none())
2278 checkLivenessAtDef(MO, MONum, DefIdx, SR,
Reg,
true, SR.LaneMask);
2282 report(
"Virtual register has no Live interval", MO, MONum);
2293 void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2294 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2295 set_union(MInfo.regsKilled, regsKilled);
2296 set_subtract(regsLive, regsKilled); regsKilled.clear();
2298 while (!regMasks.empty()) {
2301 if (
Reg.isPhysical() &&
2303 regsDead.push_back(
Reg);
2306 set_union(regsLive, regsDefined); regsDefined.clear();
2311 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2316 if (!(stop > lastIndex)) {
2317 report(
"Block ends before last instruction index",
MBB);
2318 errs() <<
"Block ends at " << stop
2319 <<
" last instruction was at " << lastIndex <<
'\n';
2334 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2336 filterAndAdd(FromRegSet, VRegsBuffer);
2341 template <
typename RegSetT>
2342 bool filterAndAdd(
const RegSetT &FromRegSet,
2344 unsigned SparseUniverse = Sparse.size();
2345 unsigned NewSparseUniverse = SparseUniverse;
2346 unsigned NewDenseSize = Dense.size();
2347 size_t Begin = ToVRegs.size();
2349 if (!
Reg.isVirtual())
2352 if (
Index < SparseUniverseMax) {
2353 if (
Index < SparseUniverse && Sparse.test(
Index))
2357 if (Dense.count(
Reg))
2361 ToVRegs.push_back(
Reg);
2363 size_t End = ToVRegs.size();
2370 Sparse.
resize(NewSparseUniverse);
2371 Dense.reserve(NewDenseSize);
2372 for (
unsigned I = Begin;
I < End; ++
I) {
2375 if (
Index < SparseUniverseMax)
2384 static constexpr
unsigned SparseUniverseMax = 10 * 1024 * 8;
2404 class FilteringVRegSet {
2411 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
2416 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
2419 return Filter.filterAndAdd(RS, VRegs);
2421 using const_iterator = decltype(VRegs)::const_iterator;
2422 const_iterator
begin()
const {
return VRegs.begin(); }
2423 const_iterator
end()
const {
return VRegs.end(); }
2424 size_t size()
const {
return VRegs.size(); }
2431 void MachineVerifier::calcRegsPassed() {
2438 FilteringVRegSet VRegs;
2439 BBInfo &
Info = MBBInfoMap[MB];
2442 VRegs.addToFilter(
Info.regsKilled);
2443 VRegs.addToFilter(
Info.regsLiveOut);
2445 const BBInfo &PredInfo = MBBInfoMap[Pred];
2446 if (!PredInfo.reachable)
2449 VRegs.add(PredInfo.regsLiveOut);
2450 VRegs.add(PredInfo.vregsPassed);
2452 Info.vregsPassed.reserve(VRegs.size());
2453 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2460 void MachineVerifier::calcRegsRequired() {
2463 for (
const auto &
MBB : *MF) {
2464 BBInfo &MInfo = MBBInfoMap[&
MBB];
2466 BBInfo &PInfo = MBBInfoMap[Pred];
2467 if (PInfo.addRequired(MInfo.vregsLiveIn))
2473 for (
unsigned i = 1,
e =
MI.getNumOperands();
i !=
e;
i += 2) {
2475 if (!
MI.getOperand(
i).isReg() || !
MI.getOperand(
i).readsReg())
2482 BBInfo &PInfo = MBBInfoMap[Pred];
2483 if (PInfo.addRequired(
Reg))
2491 while (!todo.
empty()) {
2494 BBInfo &MInfo = MBBInfoMap[
MBB];
2498 BBInfo &SInfo = MBBInfoMap[Pred];
2499 if (SInfo.addRequired(MInfo.vregsRequired))
2508 BBInfo &MInfo = MBBInfoMap[&
MBB];
2518 report(
"Expected first PHI operand to be a register def", &MODef, 0);
2523 report(
"Unexpected flag on PHI operand", &MODef, 0);
2526 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
2528 for (
unsigned I = 1,
E = Phi.getNumOperands();
I !=
E;
I += 2) {
2531 report(
"Expected PHI operand to be a register", &MO0,
I);
2536 report(
"Unexpected flag on PHI operand", &MO0,
I);
2540 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
2546 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
2550 if (MInfo.reachable) {
2552 BBInfo &PrInfo = MBBInfoMap[&Pre];
2553 if (!MO0.
isUndef() && PrInfo.reachable &&
2554 !PrInfo.isLiveOut(MO0.
getReg()))
2555 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
2560 if (MInfo.reachable) {
2562 if (!seen.
count(Pred)) {
2563 report(
"Missing PHI operand", &Phi);
2565 <<
" is a predecessor according to the CFG.\n";
2572 void MachineVerifier::visitMachineFunctionAfter() {
2582 for (
const auto &
MBB : *MF) {
2583 BBInfo &MInfo = MBBInfoMap[&
MBB];
2584 for (
Register VReg : MInfo.vregsRequired)
2585 if (MInfo.regsKilled.count(VReg)) {
2586 report(
"Virtual register killed in block, but needed live out.", &
MBB);
2588 <<
" is used after the block.\n";
2593 BBInfo &MInfo = MBBInfoMap[&MF->front()];
2594 for (
Register VReg : MInfo.vregsRequired) {
2595 report(
"Virtual register defs don't dominate all uses.", MF);
2596 report_context_vreg(VReg);
2601 verifyLiveVariables();
2603 verifyLiveIntervals();
2613 for (
const auto &
MBB : *MF)
2617 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2620 BBInfo &PInfo = MBBInfoMap[Pred];
2621 if (!PInfo.regsLiveOut.count(LiveInReg)) {
2622 report(
"Live in register not found to be live out from predecessor.",
2625 <<
" not found to be live out from "
2631 for (
auto CSInfo : MF->getCallSitesInfo())
2632 if (!CSInfo.first->isCall())
2633 report(
"Call site info referencing instruction that is not call", MF);
2637 if (MF->getFunction().getSubprogram()) {
2639 for (
auto &
MBB : *MF) {
2640 for (
auto &
MI :
MBB) {
2641 if (
auto Num =
MI.peekDebugInstrNum()) {
2644 report(
"Instruction has a duplicated value tracking number", &
MI);
2651 void MachineVerifier::verifyLiveVariables() {
2652 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
2656 for (
const auto &
MBB : *MF) {
2657 BBInfo &MInfo = MBBInfoMap[&
MBB];
2660 if (MInfo.vregsRequired.count(
Reg)) {
2662 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
2664 <<
" must be live through the block.\n";
2668 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
2670 <<
" is not needed live through the block.\n";
2677 void MachineVerifier::verifyLiveIntervals() {
2678 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
2687 report(
"Missing live interval for virtual register", MF);
2693 assert(
Reg == LI.
reg() &&
"Invalid reg to interval mapping");
2694 verifyLiveInterval(LI);
2700 verifyLiveRange(*LR,
i);
2703 void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
2712 report(
"Value not live at VNInfo def and not marked unused", MF);
2713 report_context(LR,
Reg, LaneMask);
2714 report_context(*VNI);
2718 if (DefVNI != VNI) {
2719 report(
"Live segment at def has different VNInfo", MF);
2720 report_context(LR,
Reg, LaneMask);
2721 report_context(*VNI);
2727 report(
"Invalid VNInfo definition index", MF);
2728 report_context(LR,
Reg, LaneMask);
2729 report_context(*VNI);
2735 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
2736 report_context(LR,
Reg, LaneMask);
2737 report_context(*VNI);
2745 report(
"No instruction at VNInfo def index",
MBB);
2746 report_context(LR,
Reg, LaneMask);
2747 report_context(*VNI);
2752 bool hasDef =
false;
2753 bool isEarlyClobber =
false;
2755 if (!MOI->isReg() || !MOI->isDef())
2758 if (MOI->getReg() !=
Reg)
2765 if (LaneMask.
any() &&
2769 if (MOI->isEarlyClobber())
2770 isEarlyClobber =
true;
2774 report(
"Defining instruction does not modify register",
MI);
2775 report_context(LR,
Reg, LaneMask);
2776 report_context(*VNI);
2781 if (isEarlyClobber) {
2783 report(
"Early clobber def must be at an early-clobber slot",
MBB);
2784 report_context(LR,
Reg, LaneMask);
2785 report_context(*VNI);
2788 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
2789 report_context(LR,
Reg, LaneMask);
2790 report_context(*VNI);
2795 void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
2801 assert(VNI &&
"Live segment has no valno");
2804 report(
"Foreign valno in live segment", MF);
2805 report_context(LR,
Reg, LaneMask);
2807 report_context(*VNI);
2811 report(
"Live segment valno is marked unused", MF);
2812 report_context(LR,
Reg, LaneMask);
2818 report(
"Bad start of live segment, no basic block", MF);
2819 report_context(LR,
Reg, LaneMask);
2824 if (
S.start != MBBStartIdx &&
S.start != VNI->
def) {
2825 report(
"Live segment must begin at MBB entry or valno def",
MBB);
2826 report_context(LR,
Reg, LaneMask);
2833 report(
"Bad end of live segment, no basic block", MF);
2834 report_context(LR,
Reg, LaneMask);
2852 report(
"Live segment doesn't end at a valid instruction", EndMBB);
2853 report_context(LR,
Reg, LaneMask);
2859 if (
S.end.isBlock()) {
2860 report(
"Live segment ends at B slot of an instruction", EndMBB);
2861 report_context(LR,
Reg, LaneMask);
2865 if (
S.end.isDead()) {
2869 report(
"Live segment ending at dead slot spans instructions", EndMBB);
2870 report_context(LR,
Reg, LaneMask);
2877 if (
S.end.isEarlyClobber()) {
2878 if (
I+1 == LR.
end() || (
I+1)->start !=
S.end) {
2879 report(
"Live segment ending at early clobber slot must be "
2880 "redefined by an EC def in the same instruction", EndMBB);
2881 report_context(LR,
Reg, LaneMask);
2891 bool hasRead =
false;
2892 bool hasSubRegDef =
false;
2893 bool hasDeadDef =
false;
2895 if (!MOI->isReg() || MOI->getReg() !=
Reg)
2897 unsigned Sub = MOI->getSubReg();
2902 hasSubRegDef =
true;
2911 if (LaneMask.
any() && (LaneMask & SLM).none())
2913 if (MOI->readsReg())
2916 if (
S.end.isDead()) {
2920 if (LaneMask.
none() && !hasDeadDef) {
2921 report(
"Instruction ending live segment on dead slot has no dead flag",
2923 report_context(LR,
Reg, LaneMask);
2932 report(
"Instruction ending live segment doesn't read the register",
2934 report_context(LR,
Reg, LaneMask);
2953 if (LaneMask.
any()) {
2962 if (&*MFI == EndMBB)
2981 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
2984 report(
"Register not marked live out of predecessor", Pred);
2985 report_context(LR,
Reg, LaneMask);
2986 report_context(*VNI);
2994 if (!IsPHI && PVNI != VNI) {
2995 report(
"Different value live out of predecessor", Pred);
2996 report_context(LR,
Reg, LaneMask);
2997 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3003 if (&*MFI == EndMBB)
3012 verifyLiveRangeValue(LR, VNI,
Reg, LaneMask);
3015 verifyLiveRangeSegment(LR,
I,
Reg, LaneMask);
3018 void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3021 verifyLiveRange(LI,
Reg);
3026 if ((
Mask & SR.LaneMask).any()) {
3027 report(
"Lane masks of sub ranges overlap in live interval", MF);
3030 if ((SR.LaneMask & ~MaxMask).any()) {
3031 report(
"Subrange lanemask is invalid", MF);
3035 report(
"Subrange must not be empty", MF);
3036 report_context(SR, LI.
reg(), SR.LaneMask);
3038 Mask |= SR.LaneMask;
3039 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3041 report(
"A Subrange is not covered by the main range", MF);
3048 unsigned NumComp = ConEQ.Classify(LI);
3050 report(
"Multiple connected components in live interval", MF);
3052 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3053 errs() << comp <<
": valnos";
3055 if (comp == ConEQ.getEqClass(
I))
3056 errs() <<
' ' <<
I->id;
3068 struct StackStateOfBB {
3069 StackStateOfBB() =
default;
3070 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3071 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3072 ExitIsSetup(ExitSetup) {}
3077 bool EntryIsSetup =
false;
3078 bool ExitIsSetup =
false;
3086 void MachineVerifier::verifyStackFrame() {
3087 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3088 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3089 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3093 SPState.
resize(MF->getNumBlockIDs());
3100 DFI != DFE; ++DFI) {
3103 StackStateOfBB BBState;
3105 if (DFI.getPathLength() >= 2) {
3108 "DFS stack predecessor is already visited.\n");
3109 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3110 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3111 BBState.ExitValue = BBState.EntryValue;
3112 BBState.ExitIsSetup = BBState.EntryIsSetup;
3116 for (
const auto &
I : *
MBB) {
3117 if (
I.getOpcode() == FrameSetupOpcode) {
3118 if (BBState.ExitIsSetup)
3119 report(
"FrameSetup is after another FrameSetup", &
I);
3120 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3121 BBState.ExitIsSetup =
true;
3124 if (
I.getOpcode() == FrameDestroyOpcode) {
3125 int Size =
TII->getFrameTotalSize(
I);
3126 if (!BBState.ExitIsSetup)
3127 report(
"FrameDestroy is not after a FrameSetup", &
I);
3128 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3130 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3131 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3132 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3133 << AbsSPAdj <<
">.\n";
3135 BBState.ExitValue +=
Size;
3136 BBState.ExitIsSetup =
false;
3144 if (Reachable.
count(Pred) &&
3145 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3146 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3147 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3149 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3150 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3152 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3159 if (Reachable.
count(Succ) &&
3160 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3161 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3162 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3164 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3165 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3167 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3173 if (BBState.ExitIsSetup)
3174 report(
"A return block ends with a FrameSetup.",
MBB);
3175 if (BBState.ExitValue)
3176 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
unsigned succ_size() const
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
unsigned getOpcode() const
Return the opcode number for this descriptor.
bool hasProperty(Property P) const
pred_iterator pred_begin()
def_iterator def_begin(Register RegNo) const
LiveInterval & getInterval(int Slot)
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getScalarSizeInBits() const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
@ SjLj
setjmp/longjmp based exceptions
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isPreISelGenericOptimizationHint(unsigned Opcode)
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
void clear()
clear - Removes all bits from the bitvector. Does not change capacity.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
This class is intended to be used as a base class for asm properties and features specific to the tar...
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
Intrinsic::ID getIntrinsicID() const
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isDeadDef() const
Return true if this instruction has a dead def.
This represents a simple continuous liveness interval for a value.
iterator_range< const_set_bits_iterator > set_bits() const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
SlotIndex def
The index of the defining instruction.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLT getScalarType() const
iterator_range< livein_iterator > liveins() const
const_iterator end(StringRef path)
Get end iterator over path.
A description of a memory reference used in the backend.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const APFloat & getValueAPF() const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Result of a LiveRange query.
std::pair< iterator, bool > insert(const ValueT &V)
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const fltSemantics & getSemantics() const
unsigned const TargetRegisterInfo * TRI
the resulting code requires compare and branches when and if * p
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
@ MO_Register
Register operand.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
LLVM Basic Block Representation.
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
This holds information about one operand of a machine instruction, indicating the register class for ...
unsigned pred_size() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
This is the shared class of boolean and integer constants.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
const MachineBasicBlock & front() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
TargetInstrInfo - Interface to description of machine instruction set.
bool hasInterval(int Slot) const
bool liveAt(SlotIndex index) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class implements the register bank concept.
VarInfo - This represents the regions where a virtual register is live in the program.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
size_type size() const
size - Returns the number of bits in this bitvector.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Segments::const_iterator const_iterator
@ MO_FrameIndex
Abstract Stack Frame Index.
unsigned getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static constexpr LaneBitmask getNone()
Represent the analysis usage information of a pass.
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
const MachineFunctionProperties & getProperties() const
Get the function properties.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
modulo schedule Modulo Schedule test pass
Pair of physical register and lane mask.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
ConstantFP - Floating Point Values [float, double].
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
static use_nodbg_iterator use_nodbg_end()
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Analysis containing CSE Info
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Special value supplied for machine level alias analysis.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
SlotIndex - An opaque wrapper around machine indexes.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void initializeMachineVerifierPassPass(PassRegistry &)
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
std::string str() const
Return the twine contents as a std::string.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
bool isOptionalDef() const
Set if this operand is a optional def.
unsigned getAddressSpace() const
Implements a dense probed hash-table based set.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
This class represents the liveness of a register, stack slot, etc.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
unsigned id
The ID number of this value.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
bool isGenericType() const
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
uint8_t OperandType
Information about the type of the operand.
unsigned getNumValNums() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
constexpr bool any() const
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool isValid() const
isValid - Returns true until all the operands have been visited.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
succ_iterator succ_begin()
bool isEarlyClobber() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
ArrayRef< int > getShuffleMask() const
const MCOperandInfo * OpInfo
Register getReg() const
getReg - Returns the register number.
iterator_range< pred_iterator > predecessors()
Base class for user error types.
static def_iterator def_end()
bool isReturn(QueryType Type=AnyInBundle) const
static bool isStore(int Opcode)
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
LiveInterval & getInterval(Register Reg)
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
bool isShuffleMask() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
SmallVector< MachineOperand, 4 > Cond
iterator_range< succ_iterator > successors()
bool isEHPad() const
Returns true if the block is a landing pad.
static bool isLoad(int Opcode)
StringRef - Represent a constant reference to a string, i.e.
constexpr bool none() const
MachineBasicBlock MachineBasicBlock::iterator MBBI
bool isIntrinsicID() const
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
self_iterator getIterator()
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
A live range for subregisters.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
unsigned getGenericTypeIndex() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
bool test(unsigned Idx) const
MI-level Statepoint operands.
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
void setPreservesAll()
Set by analyses that do not transform their input at all.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Iterator for intrusive lists based on ilist_node.
const char * getName() const
Get a user friendly name of this register bank.
uint64_t getSize() const
Return the size in bytes of the memory reference.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
VNInfo - Value Number Information.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
ExceptionHandling getExceptionHandlingType() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Pass interface - Implemented by all 'passes'.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
LLVM_NODISCARD bool empty() const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
size_t size() const
size - Get the array size.
Align max(MaybeAlign Lhs, Align Rhs)
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
bool isInternalRead() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
FunctionPass class - This class is used to implement most global optimizations.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
bool isUnused() const
Returns true if this value is unused.
bool hasInterval(Register Reg) const
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
@ MO_RegisterMask
Mask of preserved registers.
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
LLVM Value Representation.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static constexpr LaneBitmask getAll()
MCRegAliasIterator enumerates all registers aliasing Reg.
void verifyUseLists() const
Verify the use list of all registers.
const PseudoSourceValue * getPseudoValue() const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
iterator_range< subrange_iterator > subranges()