LLVM  15.0.0git
Thumb1FrameLowering.cpp
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1 //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb1 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb1FrameLowering.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMSubtarget.h"
18 #include "Thumb1InstrInfo.h"
19 #include "ThumbRegisterInfo.h"
20 #include "Utils/ARMBaseInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/IR/DebugLoc.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCDwarf.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/Support/Compiler.h"
43 #include <bitset>
44 #include <cassert>
45 #include <iterator>
46 #include <vector>
47 
48 using namespace llvm;
49 
51  : ARMFrameLowering(sti) {}
52 
54  const MachineFrameInfo &MFI = MF.getFrameInfo();
55  unsigned CFSize = MFI.getMaxCallFrameSize();
56  // It's not always a good idea to include the call frame as part of the
57  // stack frame. ARM (especially Thumb) has small immediate offset to
58  // address the stack frame. So a large call frame can cause poor codegen
59  // and may even makes it impossible to scavenge a register.
60  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
61  return false;
62 
63  return !MFI.hasVarSizedObjects();
64 }
65 
66 static void
69  const TargetInstrInfo &TII, const DebugLoc &dl,
70  const ThumbRegisterInfo &MRI, int NumBytes,
71  unsigned ScratchReg, unsigned MIFlags) {
72  // If it would take more than three instructions to adjust the stack pointer
73  // using tADDspi/tSUBspi, load an immediate instead.
74  if (std::abs(NumBytes) > 508 * 3) {
75  // We use a different codepath here from the normal
76  // emitThumbRegPlusImmediate so we don't have to deal with register
77  // scavenging. (Scavenging could try to use the emergency spill slot
78  // before we've actually finished setting up the stack.)
79  if (ScratchReg == ARM::NoRegister)
80  report_fatal_error("Failed to emit Thumb1 stack adjustment");
81  MachineFunction &MF = *MBB.getParent();
83  if (ST.genExecuteOnly()) {
84  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
85  .addImm(NumBytes).setMIFlags(MIFlags);
86  } else {
87  MRI.emitLoadConstPool(MBB, MBBI, dl, ScratchReg, 0, NumBytes, ARMCC::AL,
88  0, MIFlags);
89  }
90  BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
91  .addReg(ARM::SP)
92  .addReg(ScratchReg, RegState::Kill)
94  .setMIFlags(MIFlags);
95  return;
96  }
97  // FIXME: This is assuming the heuristics in emitThumbRegPlusImmediate
98  // won't change.
99  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
100  MRI, MIFlags);
101 
102 }
103 
106  const TargetInstrInfo &TII, const DebugLoc &dl,
107  const ThumbRegisterInfo &MRI, int NumBytes,
108  unsigned MIFlags = MachineInstr::NoFlags) {
109  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
110  MRI, MIFlags);
111 }
112 
113 
117  const Thumb1InstrInfo &TII =
118  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
119  const ThumbRegisterInfo *RegInfo =
120  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
121  if (!hasReservedCallFrame(MF)) {
122  // If we have alloca, convert as follows:
123  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
124  // ADJCALLSTACKUP -> add, sp, sp, amount
125  MachineInstr &Old = *I;
126  DebugLoc dl = Old.getDebugLoc();
127  unsigned Amount = TII.getFrameSize(Old);
128  if (Amount != 0) {
129  // We need to keep the stack aligned properly. To do this, we round the
130  // amount of space needed for the outgoing arguments up to the next
131  // alignment boundary.
132  Amount = alignTo(Amount, getStackAlign());
133 
134  // Replace the pseudo instruction with a new instruction...
135  unsigned Opc = Old.getOpcode();
136  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
137  emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
138  } else {
139  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
140  emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
141  }
142  }
143  }
144  return MBB.erase(I);
145 }
146 
148  MachineBasicBlock &MBB) const {
150  MachineFrameInfo &MFI = MF.getFrameInfo();
152  MachineModuleInfo &MMI = MF.getMMI();
153  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
154  const ThumbRegisterInfo *RegInfo =
155  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
156  const Thumb1InstrInfo &TII =
157  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
158 
159  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
160  unsigned NumBytes = MFI.getStackSize();
161  assert(NumBytes >= ArgRegsSaveSize &&
162  "ArgRegsSaveSize is included in NumBytes");
163  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
164 
165  // Debug location must be unknown since the first debug location is used
166  // to determine the end of the prologue.
167  DebugLoc dl;
168 
169  Register FramePtr = RegInfo->getFrameRegister(MF);
170  Register BasePtr = RegInfo->getBaseRegister();
171  int CFAOffset = 0;
172 
173  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
174  NumBytes = (NumBytes + 3) & ~3;
175  MFI.setStackSize(NumBytes);
176 
177  // Determine the sizes of each callee-save spill areas and record which frame
178  // belongs to which callee-save spill areas.
179  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
180  int FramePtrSpillFI = 0;
181 
182  if (ArgRegsSaveSize) {
183  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
184  ARM::NoRegister, MachineInstr::FrameSetup);
185  CFAOffset += ArgRegsSaveSize;
186  unsigned CFIIndex =
187  MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
188  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
189  .addCFIIndex(CFIIndex)
191  }
192 
193  if (!AFI->hasStackFrame()) {
194  if (NumBytes - ArgRegsSaveSize != 0) {
195  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
196  -(NumBytes - ArgRegsSaveSize),
197  ARM::NoRegister, MachineInstr::FrameSetup);
198  CFAOffset += NumBytes - ArgRegsSaveSize;
199  unsigned CFIIndex = MF.addFrameInst(
200  MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
201  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
202  .addCFIIndex(CFIIndex)
204  }
205  return;
206  }
207 
208  for (const CalleeSavedInfo &I : CSI) {
209  Register Reg = I.getReg();
210  int FI = I.getFrameIdx();
211  switch (Reg) {
212  case ARM::R8:
213  case ARM::R9:
214  case ARM::R10:
215  case ARM::R11:
216  if (STI.splitFramePushPop(MF)) {
217  GPRCS2Size += 4;
218  break;
219  }
221  case ARM::R4:
222  case ARM::R5:
223  case ARM::R6:
224  case ARM::R7:
225  case ARM::LR:
226  if (Reg == FramePtr)
227  FramePtrSpillFI = FI;
228  GPRCS1Size += 4;
229  break;
230  default:
231  DPRCSSize += 8;
232  }
233  }
234 
235  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
236  ++MBBI;
237  }
238 
239  // Determine starting offsets of spill areas.
240  unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
241  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
242  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
243  bool HasFP = hasFP(MF);
244  if (HasFP)
245  AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
246  NumBytes);
247  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
248  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
249  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
250  NumBytes = DPRCSOffset;
251 
252  int FramePtrOffsetInBlock = 0;
253  unsigned adjustedGPRCS1Size = GPRCS1Size;
254  if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
255  tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
256  FramePtrOffsetInBlock = NumBytes;
257  adjustedGPRCS1Size += NumBytes;
258  NumBytes = 0;
259  }
260 
261  if (adjustedGPRCS1Size) {
262  CFAOffset += adjustedGPRCS1Size;
263  unsigned CFIIndex =
264  MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
265  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
266  .addCFIIndex(CFIIndex)
268  }
269  for (const CalleeSavedInfo &I : CSI) {
270  Register Reg = I.getReg();
271  int FI = I.getFrameIdx();
272  switch (Reg) {
273  case ARM::R8:
274  case ARM::R9:
275  case ARM::R10:
276  case ARM::R11:
277  case ARM::R12:
278  if (STI.splitFramePushPop(MF))
279  break;
281  case ARM::R0:
282  case ARM::R1:
283  case ARM::R2:
284  case ARM::R3:
285  case ARM::R4:
286  case ARM::R5:
287  case ARM::R6:
288  case ARM::R7:
289  case ARM::LR:
290  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
291  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
292  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
293  .addCFIIndex(CFIIndex)
295  break;
296  }
297  }
298 
299  // Adjust FP so it point to the stack slot that contains the previous FP.
300  if (HasFP) {
301  FramePtrOffsetInBlock +=
302  MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
303  BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
304  .addReg(ARM::SP)
305  .addImm(FramePtrOffsetInBlock / 4)
307  .add(predOps(ARMCC::AL));
308  if(FramePtrOffsetInBlock) {
309  CFAOffset -= FramePtrOffsetInBlock;
310  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
311  nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
312  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
313  .addCFIIndex(CFIIndex)
315  } else {
316  unsigned CFIIndex =
318  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
319  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
320  .addCFIIndex(CFIIndex)
322  }
323  if (NumBytes > 508)
324  // If offset is > 508 then sp cannot be adjusted in a single instruction,
325  // try restoring from fp instead.
326  AFI->setShouldRestoreSPFromFP(true);
327  }
328 
329  // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
330  // and tMOVr instructions. We don't need to add any call frame information
331  // in-between these instructions, because they do not modify the high
332  // registers.
333  while (true) {
335  // Skip a run of tMOVr instructions
336  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
337  MBBI++;
338  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
339  MBBI++;
340  } else {
341  // We have reached an instruction which is not a push, so the previous
342  // run of tMOVr instructions (which may have been empty) was not part of
343  // the prologue. Reset MBBI back to the last PUSH of the prologue.
344  MBBI = OldMBBI;
345  break;
346  }
347  }
348 
349  // Emit call frame information for the callee-saved high registers.
350  for (auto &I : CSI) {
351  Register Reg = I.getReg();
352  int FI = I.getFrameIdx();
353  switch (Reg) {
354  case ARM::R8:
355  case ARM::R9:
356  case ARM::R10:
357  case ARM::R11:
358  case ARM::R12: {
359  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
360  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
361  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
362  .addCFIIndex(CFIIndex)
364  break;
365  }
366  default:
367  break;
368  }
369  }
370 
371  if (NumBytes) {
372  // Insert it after all the callee-save spills.
373  //
374  // For a large stack frame, we might need a scratch register to store
375  // the size of the frame. We know all callee-save registers are free
376  // at this point in the prologue, so pick one.
377  unsigned ScratchRegister = ARM::NoRegister;
378  for (auto &I : CSI) {
379  Register Reg = I.getReg();
380  if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
381  ScratchRegister = Reg;
382  break;
383  }
384  }
385  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
386  ScratchRegister, MachineInstr::FrameSetup);
387  if (!HasFP) {
388  CFAOffset += NumBytes;
389  unsigned CFIIndex = MF.addFrameInst(
390  MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
391  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
392  .addCFIIndex(CFIIndex)
394  }
395  }
396 
397  if (STI.isTargetELF() && HasFP)
399  AFI->getFramePtrSpillOffset());
400 
401  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
402  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
403  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
404 
405  if (RegInfo->hasStackRealignment(MF)) {
406  const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
407  // Emit the following sequence, using R4 as a temporary, since we cannot use
408  // SP as a source or destination register for the shifts:
409  // mov r4, sp
410  // lsrs r4, r4, #NrBitsToZero
411  // lsls r4, r4, #NrBitsToZero
412  // mov sp, r4
413  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
414  .addReg(ARM::SP, RegState::Kill)
415  .add(predOps(ARMCC::AL));
416 
417  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
418  .addDef(ARM::CPSR)
420  .addImm(NrBitsToZero)
421  .add(predOps(ARMCC::AL));
422 
423  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
424  .addDef(ARM::CPSR)
426  .addImm(NrBitsToZero)
427  .add(predOps(ARMCC::AL));
428 
429  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
431  .add(predOps(ARMCC::AL));
432 
433  AFI->setShouldRestoreSPFromFP(true);
434  }
435 
436  // If we need a base pointer, set it up here. It's whatever the value
437  // of the stack pointer is at this point. Any variable size objects
438  // will be allocated after this, so we can still use the base pointer
439  // to reference locals.
440  if (RegInfo->hasBasePointer(MF))
441  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
442  .addReg(ARM::SP)
443  .add(predOps(ARMCC::AL));
444 
445  // If the frame has variable sized objects then the epilogue must restore
446  // the sp from fp. We can assume there's an FP here since hasFP already
447  // checks for hasVarSizedObjects.
448  if (MFI.hasVarSizedObjects())
449  AFI->setShouldRestoreSPFromFP(true);
450 
451  // In some cases, virtual registers have been introduced, e.g. by uses of
452  // emitThumbRegPlusImmInReg.
454 }
455 
457  MachineBasicBlock &MBB) const {
459  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
460  MachineFrameInfo &MFI = MF.getFrameInfo();
462  const ThumbRegisterInfo *RegInfo =
463  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
464  const Thumb1InstrInfo &TII =
465  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
466 
467  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
468  int NumBytes = (int)MFI.getStackSize();
469  assert((unsigned)NumBytes >= ArgRegsSaveSize &&
470  "ArgRegsSaveSize is included in NumBytes");
471  Register FramePtr = RegInfo->getFrameRegister(MF);
472 
473  if (!AFI->hasStackFrame()) {
474  if (NumBytes - ArgRegsSaveSize != 0)
475  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
476  NumBytes - ArgRegsSaveSize, ARM::NoRegister,
478  } else {
479  // Unwind MBBI to point to first LDR / VLDRD.
480  if (MBBI != MBB.begin()) {
481  do
482  --MBBI;
483  while (MBBI != MBB.begin() && MBBI->getFlag(MachineInstr::FrameDestroy));
484  if (!MBBI->getFlag(MachineInstr::FrameDestroy))
485  ++MBBI;
486  }
487 
488  // Move SP to start of FP callee save spill area.
489  NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
492  ArgRegsSaveSize);
493 
494  if (AFI->shouldRestoreSPFromFP()) {
495  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
496  // Reset SP based on frame pointer only if the stack frame extends beyond
497  // frame pointer stack slot, the target is ELF and the function has FP, or
498  // the target uses var sized objects.
499  if (NumBytes) {
500  assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
501  "No scratch register to restore SP from FP!");
503  TII, *RegInfo, MachineInstr::FrameDestroy);
504  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
505  .addReg(ARM::R4)
508  } else
509  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
510  .addReg(FramePtr)
513  } else {
514  // For a large stack frame, we might need a scratch register to store
515  // the size of the frame. We know all callee-save registers are free
516  // at this point in the epilogue, so pick one.
517  unsigned ScratchRegister = ARM::NoRegister;
518  bool HasFP = hasFP(MF);
519  for (auto &I : MFI.getCalleeSavedInfo()) {
520  Register Reg = I.getReg();
521  if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
522  ScratchRegister = Reg;
523  break;
524  }
525  }
526  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
527  &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
528  MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
529  if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
530  emitPrologueEpilogueSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes,
531  ScratchRegister, MachineInstr::FrameDestroy);
532  } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
533  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes,
534  ScratchRegister, MachineInstr::FrameDestroy);
535  }
536  }
537 
538  if (needPopSpecialFixUp(MF)) {
539  bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
540  (void)Done;
541  assert(Done && "Emission of the special fixup failed!?");
542  }
543 }
544 
546  if (!needPopSpecialFixUp(*MBB.getParent()))
547  return true;
548 
549  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
550  return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
551 }
552 
553 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
554  ARMFunctionInfo *AFI =
555  const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
556  if (AFI->getArgRegsSaveSize())
557  return true;
558 
559  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
560  for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
561  if (CSI.getReg() == ARM::LR)
562  return true;
563 
564  return false;
565 }
566 
567 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
568  const BitVector &PopFriendly,
569  const LivePhysRegs &UsedRegs, unsigned &PopReg,
570  unsigned &TmpReg, MachineRegisterInfo &MRI) {
571  PopReg = TmpReg = 0;
572  for (auto Reg : GPRsNoLRSP.set_bits()) {
573  if (UsedRegs.available(MRI, Reg)) {
574  // Remember the first pop-friendly register and exit.
575  if (PopFriendly.test(Reg)) {
576  PopReg = Reg;
577  TmpReg = 0;
578  break;
579  }
580  // Otherwise, remember that the register will be available to
581  // save a pop-friendly register.
582  TmpReg = Reg;
583  }
584  }
585 }
586 
587 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
588  bool DoIt) const {
589  MachineFunction &MF = *MBB.getParent();
591  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
592  const TargetInstrInfo &TII = *STI.getInstrInfo();
593  const ThumbRegisterInfo *RegInfo =
594  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
595 
596  // If MBBI is a return instruction, or is a tPOP followed by a return
597  // instruction in the successor BB, we may be able to directly restore
598  // LR in the PC.
599  // This is only possible with v5T ops (v4T can't change the Thumb bit via
600  // a POP PC instruction), and only if we do not need to emit any SP update.
601  // Otherwise, we need a temporary register to pop the value
602  // and copy that value into LR.
603  auto MBBI = MBB.getFirstTerminator();
604  bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
605  if (CanRestoreDirectly) {
606  if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
607  CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
608  MBBI->getOpcode() == ARM::tPOP_RET);
609  else {
610  auto MBBI_prev = MBBI;
611  MBBI_prev--;
612  assert(MBBI_prev->getOpcode() == ARM::tPOP);
613  assert(MBB.succ_size() == 1);
614  if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
615  MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
616  else
617  CanRestoreDirectly = false;
618  }
619  }
620 
621  if (CanRestoreDirectly) {
622  if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
623  return true;
624  MachineInstrBuilder MIB =
625  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
628  // Copy implicit ops and popped registers, if any.
629  for (auto MO: MBBI->operands())
630  if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
631  MIB.add(MO);
632  MIB.addReg(ARM::PC, RegState::Define);
633  // Erase the old instruction (tBX_RET or tPOP).
634  MBB.erase(MBBI);
635  return true;
636  }
637 
638  // Look for a temporary register to use.
639  // First, compute the liveness information.
641  LivePhysRegs UsedRegs(TRI);
642  UsedRegs.addLiveOuts(MBB);
643  // The semantic of pristines changed recently and now,
644  // the callee-saved registers that are touched in the function
645  // are not part of the pristines set anymore.
646  // Add those callee-saved now.
647  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
648  for (unsigned i = 0; CSRegs[i]; ++i)
649  UsedRegs.addReg(CSRegs[i]);
650 
651  DebugLoc dl = DebugLoc();
652  if (MBBI != MBB.end()) {
653  dl = MBBI->getDebugLoc();
654  auto InstUpToMBBI = MBB.end();
655  while (InstUpToMBBI != MBBI)
656  // The pre-decrement is on purpose here.
657  // We want to have the liveness right before MBBI.
658  UsedRegs.stepBackward(*--InstUpToMBBI);
659  }
660 
661  // Look for a register that can be directly use in the POP.
662  unsigned PopReg = 0;
663  // And some temporary register, just in case.
664  unsigned TemporaryReg = 0;
665  BitVector PopFriendly =
666  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
667  // R7 may be used as a frame pointer, hence marked as not generally
668  // allocatable, however there's no reason to not use it as a temporary for
669  // restoring LR.
670  if (STI.getFramePointerReg() == ARM::R7)
671  PopFriendly.set(ARM::R7);
672 
673  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
674  // Rebuild the GPRs from the high registers because they are removed
675  // form the GPR reg class for thumb1.
676  BitVector GPRsNoLRSP =
677  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
678  GPRsNoLRSP |= PopFriendly;
679  GPRsNoLRSP.reset(ARM::LR);
680  GPRsNoLRSP.reset(ARM::SP);
681  GPRsNoLRSP.reset(ARM::PC);
682  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg,
683  MF.getRegInfo());
684 
685  // If we couldn't find a pop-friendly register, try restoring LR before
686  // popping the other callee-saved registers, so we could use one of them as a
687  // temporary.
688  bool UseLDRSP = false;
689  if (!PopReg && MBBI != MBB.begin()) {
690  auto PrevMBBI = MBBI;
691  PrevMBBI--;
692  if (PrevMBBI->getOpcode() == ARM::tPOP) {
693  UsedRegs.stepBackward(*PrevMBBI);
694  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg,
695  TemporaryReg, MF.getRegInfo());
696  if (PopReg) {
697  MBBI = PrevMBBI;
698  UseLDRSP = true;
699  }
700  }
701  }
702 
703  if (!DoIt && !PopReg && !TemporaryReg)
704  return false;
705 
706  assert((PopReg || TemporaryReg) && "Cannot get LR");
707 
708  if (UseLDRSP) {
709  assert(PopReg && "Do not know how to get LR");
710  // Load the LR via LDR tmp, [SP, #off]
711  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
712  .addReg(PopReg, RegState::Define)
713  .addReg(ARM::SP)
714  .addImm(MBBI->getNumExplicitOperands() - 2)
717  // Move from the temporary register to the LR.
718  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
719  .addReg(ARM::LR, RegState::Define)
720  .addReg(PopReg, RegState::Kill)
723  // Advance past the pop instruction.
724  MBBI++;
725  // Increment the SP.
726  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
727  ArgRegsSaveSize + 4, ARM::NoRegister,
729  return true;
730  }
731 
732  if (TemporaryReg) {
733  assert(!PopReg && "Unnecessary MOV is about to be inserted");
734  PopReg = PopFriendly.find_first();
735  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
736  .addReg(TemporaryReg, RegState::Define)
737  .addReg(PopReg, RegState::Kill)
740  }
741 
742  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
743  // We couldn't use the direct restoration above, so
744  // perform the opposite conversion: tPOP_RET to tPOP.
745  MachineInstrBuilder MIB =
746  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
749  bool Popped = false;
750  for (auto MO: MBBI->operands())
751  if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
752  MO.getReg() != ARM::PC) {
753  MIB.add(MO);
754  if (!MO.isImplicit())
755  Popped = true;
756  }
757  // Is there anything left to pop?
758  if (!Popped)
759  MBB.erase(MIB.getInstr());
760  // Erase the old instruction.
761  MBB.erase(MBBI);
762  MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
765  }
766 
767  assert(PopReg && "Do not know how to get LR");
768  BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
770  .addReg(PopReg, RegState::Define)
772 
773  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize,
774  ARM::NoRegister, MachineInstr::FrameDestroy);
775 
776  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
777  .addReg(ARM::LR, RegState::Define)
778  .addReg(PopReg, RegState::Kill)
781 
782  if (TemporaryReg)
783  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
784  .addReg(PopReg, RegState::Define)
785  .addReg(TemporaryReg, RegState::Kill)
788 
789  return true;
790 }
791 
792 using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
793 
794 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
795 // or OrderEnd if no further registers are in that set. This does not advance
796 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
797 static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
798  const ARMRegSet &EnabledRegs,
799  const unsigned *OrderEnd) {
800  while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
801  ++CurrentReg;
802  return CurrentReg;
803 }
804 
808  if (CSI.empty())
809  return false;
810 
811  DebugLoc DL;
812  const TargetInstrInfo &TII = *STI.getInstrInfo();
813  MachineFunction &MF = *MBB.getParent();
814  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
816 
817  ARMRegSet LoRegsToSave; // r0-r7, lr
818  ARMRegSet HiRegsToSave; // r8-r11
819  ARMRegSet CopyRegs; // Registers which can be used after pushing
820  // LoRegs for saving HiRegs.
821 
822  for (const CalleeSavedInfo &I : llvm::reverse(CSI)) {
823  Register Reg = I.getReg();
824 
825  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
826  LoRegsToSave[Reg] = true;
827  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
828  HiRegsToSave[Reg] = true;
829  } else {
830  llvm_unreachable("callee-saved register of unexpected class");
831  }
832 
833  if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
834  !MF.getRegInfo().isLiveIn(Reg) &&
835  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
836  CopyRegs[Reg] = true;
837  }
838 
839  // Unused argument registers can be used for the high register saving.
840  for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
841  if (!MF.getRegInfo().isLiveIn(ArgReg))
842  CopyRegs[ArgReg] = true;
843 
844  // Push the low registers and lr
845  const MachineRegisterInfo &MRI = MF.getRegInfo();
846  if (!LoRegsToSave.none()) {
847  MachineInstrBuilder MIB =
848  BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
849  for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
850  if (LoRegsToSave[Reg]) {
851  bool isKill = !MRI.isLiveIn(Reg);
852  if (isKill && !MRI.isReserved(Reg))
853  MBB.addLiveIn(Reg);
854 
855  MIB.addReg(Reg, getKillRegState(isKill));
856  }
857  }
859  }
860 
861  // Push the high registers. There are no store instructions that can access
862  // these registers directly, so we have to move them to low registers, and
863  // push them. This might take multiple pushes, as it is possible for there to
864  // be fewer low registers available than high registers which need saving.
865 
866  // These are in reverse order so that in the case where we need to use
867  // multiple PUSH instructions, the order of the registers on the stack still
868  // matches the unwind info. They need to be swicthed back to ascending order
869  // before adding to the PUSH instruction.
870  static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
871  ARM::R5, ARM::R4, ARM::R3,
872  ARM::R2, ARM::R1, ARM::R0};
873  static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
874 
875  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
876  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
877 
878  // Find the first register to save.
879  const unsigned *HiRegToSave = findNextOrderedReg(
880  std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
881 
882  while (HiRegToSave != AllHighRegsEnd) {
883  // Find the first low register to use.
884  const unsigned *CopyReg =
885  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
886 
887  // Create the PUSH, but don't insert it yet (the MOVs need to come first).
888  MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH))
891 
892  SmallVector<unsigned, 4> RegsToPush;
893  while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
894  if (HiRegsToSave[*HiRegToSave]) {
895  bool isKill = !MRI.isLiveIn(*HiRegToSave);
896  if (isKill && !MRI.isReserved(*HiRegToSave))
897  MBB.addLiveIn(*HiRegToSave);
898 
899  // Emit a MOV from the high reg to the low reg.
900  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
901  .addReg(*CopyReg, RegState::Define)
902  .addReg(*HiRegToSave, getKillRegState(isKill))
905 
906  // Record the register that must be added to the PUSH.
907  RegsToPush.push_back(*CopyReg);
908 
909  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
910  HiRegToSave =
911  findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
912  }
913  }
914 
915  // Add the low registers to the PUSH, in ascending order.
916  for (unsigned Reg : llvm::reverse(RegsToPush))
917  PushMIB.addReg(Reg, RegState::Kill);
918 
919  // Insert the PUSH instruction after the MOVs.
920  MBB.insert(MI, PushMIB);
921  }
922 
923  return true;
924 }
925 
929  if (CSI.empty())
930  return false;
931 
932  MachineFunction &MF = *MBB.getParent();
934  const TargetInstrInfo &TII = *STI.getInstrInfo();
935  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
937 
938  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
939  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
940 
941  ARMRegSet LoRegsToRestore;
942  ARMRegSet HiRegsToRestore;
943  // Low registers (r0-r7) which can be used to restore the high registers.
944  ARMRegSet CopyRegs;
945 
946  for (CalleeSavedInfo I : CSI) {
947  Register Reg = I.getReg();
948 
949  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
950  LoRegsToRestore[Reg] = true;
951  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
952  HiRegsToRestore[Reg] = true;
953  } else {
954  llvm_unreachable("callee-saved register of unexpected class");
955  }
956 
957  // If this is a low register not used as the frame pointer, we may want to
958  // use it for restoring the high registers.
959  if ((ARM::tGPRRegClass.contains(Reg)) &&
960  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
961  CopyRegs[Reg] = true;
962  }
963 
964  // If this is a return block, we may be able to use some unused return value
965  // registers for restoring the high regs.
967  if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
968  CopyRegs[ARM::R0] = true;
969  CopyRegs[ARM::R1] = true;
970  CopyRegs[ARM::R2] = true;
971  CopyRegs[ARM::R3] = true;
972  for (auto Op : Terminator->implicit_operands()) {
973  if (Op.isReg())
974  CopyRegs[Op.getReg()] = false;
975  }
976  }
977 
978  static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
979  ARM::R4, ARM::R5, ARM::R6, ARM::R7};
980  static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
981 
982  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
983  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
984 
985  // Find the first register to restore.
986  auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
987  HiRegsToRestore, AllHighRegsEnd);
988 
989  while (HiRegToRestore != AllHighRegsEnd) {
990  assert(!CopyRegs.none());
991  // Find the first low register to use.
992  auto CopyReg =
993  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
994 
995  // Create the POP instruction.
996  MachineInstrBuilder PopMIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPOP))
999 
1000  while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
1001  // Add the low register to the POP.
1002  PopMIB.addReg(*CopyReg, RegState::Define);
1003 
1004  // Create the MOV from low to high register.
1005  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
1006  .addReg(*HiRegToRestore, RegState::Define)
1007  .addReg(*CopyReg, RegState::Kill)
1008  .add(predOps(ARMCC::AL))
1010 
1011  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
1012  HiRegToRestore =
1013  findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
1014  }
1015  }
1016 
1017  MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP))
1018  .add(predOps(ARMCC::AL))
1020 
1021  bool NeedsPop = false;
1022  for (CalleeSavedInfo &Info : llvm::reverse(CSI)) {
1023  Register Reg = Info.getReg();
1024 
1025  // High registers (excluding lr) have already been dealt with
1026  if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
1027  continue;
1028 
1029  if (Reg == ARM::LR) {
1030  Info.setRestored(false);
1031  if (!MBB.succ_empty() ||
1032  MI->getOpcode() == ARM::TCRETURNdi ||
1033  MI->getOpcode() == ARM::TCRETURNri)
1034  // LR may only be popped into PC, as part of return sequence.
1035  // If this isn't the return sequence, we'll need emitPopSpecialFixUp
1036  // to restore LR the hard way.
1037  // FIXME: if we don't pass any stack arguments it would be actually
1038  // advantageous *and* correct to do the conversion to an ordinary call
1039  // instruction here.
1040  continue;
1041  // Special epilogue for vararg functions. See emitEpilogue
1042  if (isVarArg)
1043  continue;
1044  // ARMv4T requires BX, see emitEpilogue
1045  if (!STI.hasV5TOps())
1046  continue;
1047 
1048  // CMSE entry functions must return via BXNS, see emitEpilogue.
1049  if (AFI->isCmseNSEntryFunction())
1050  continue;
1051 
1052  // Pop LR into PC.
1053  Reg = ARM::PC;
1054  (*MIB).setDesc(TII.get(ARM::tPOP_RET));
1055  if (MI != MBB.end())
1056  MIB.copyImplicitOps(*MI);
1057  MI = MBB.erase(MI);
1058  }
1059  MIB.addReg(Reg, getDefRegState(true));
1060  NeedsPop = true;
1061  }
1062 
1063  // It's illegal to emit pop instruction without operands.
1064  if (NeedsPop)
1065  MBB.insert(MI, &*MIB);
1066  else
1067  MF.deleteMachineInstr(MIB);
1068 
1069  return true;
1070 }
llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: Thumb1FrameLowering.cpp:926
i
i
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ARMSubtarget.h
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Definition: Alignment.h:156
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Definition: MachineFrameInfo.h:354
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Definition: MachineBasicBlock.h:354
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Definition: ARMMachineFunctionInfo.h:27
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Definition: IRTranslator.cpp:104
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Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
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Definition: AddressRanges.h:17
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:315
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Definition: ARMMachineFunctionInfo.h:213
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Definition: ARMSubtarget.h:47
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Definition: MachineRegisterInfo.h:50
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const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
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Definition: ARMMachineFunctionInfo.h:185
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BitVector & set()
Definition: BitVector.h:344
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Definition: ARMMachineFunctionInfo.h:212
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Definition: Thumb1FrameLowering.cpp:50
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Definition: MachineInstrBuilder.h:247
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ErrorHandling.h
llvm::X86Disassembler::Reg
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All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
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Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:256
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Definition: ARMMachineFunctionInfo.h:206
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Definition: Thumb1FrameLowering.cpp:67
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Definition: BitVector.h:133
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Return the correction for frame offsets.
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unsigned getGPRCalleeSavedArea2Size() const
Definition: ARMMachineFunctionInfo.h:207
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A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
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virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
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Definition: TargetRegisterInfo.h:234
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bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: Thumb1FrameLowering.cpp:545
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void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:580
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auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
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Get end iterator over path.
Definition: Path.cpp:235
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Get begin iterator over path.
Definition: Path.cpp:226
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const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:264
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Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:646
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empty - Check if the array is empty.
Definition: ArrayRef.h:159
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.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:540
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Definition: MachineInstr.h:86
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Definition: ARMBaseRegisterInfo.h:209
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Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
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unsigned getDPRCalleeSavedAreaSize() const
Definition: ARMMachineFunctionInfo.h:209
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Definition: ARMMachineFunctionInfo.h:170
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virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
findTemporariesForLR
static void findTemporariesForLR(const BitVector &GPRsNoLRSP, const BitVector &PopFriendly, const LivePhysRegs &UsedRegs, unsigned &PopReg, unsigned &TmpReg, MachineRegisterInfo &MRI)
Definition: Thumb1FrameLowering.cpp:567
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:442
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
R2
#define R2(n)
llvm::Thumb1FrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: Thumb1FrameLowering.cpp:147
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::ARMFunctionInfo::setShouldRestoreSPFromFP
void setShouldRestoreSPFromFP(bool s)
Definition: ARMMachineFunctionInfo.h:186
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:306
llvm::Thumb1FrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: Thumb1FrameLowering.cpp:456
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::ARMBaseRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:481
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaSize
void setDPRCalleeSavedAreaSize(unsigned s)
Definition: ARMMachineFunctionInfo.h:215
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:209
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
MCContext.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineFunction::deleteMachineInstr
void deleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
Definition: MachineFunction.cpp:418
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:747
emitCallSPUpdate
static void emitCallSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags)
Definition: Thumb1FrameLowering.cpp:104
FramePtr
static const unsigned FramePtr
Definition: XCoreFrameLowering.cpp:34
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::ARMFunctionInfo::getFramePtrSpillOffset
unsigned getFramePtrSpillOffset() const
Definition: ARMMachineFunctionInfo.h:191
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
ARMBaseInfo.h
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:75
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:577
DebugLoc.h
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
ThumbRegisterInfo.h
llvm::BitVector
Definition: BitVector.h:75
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:533
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::ARMFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: ARMFrameLowering.cpp:201
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:607
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:420
ARMBaseRegisterInfo.h
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::BitVector::any
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:163
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::LivePhysRegs::available
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
Definition: LivePhysRegs.cpp:141
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:432
MCRegisterInfo.h
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:374
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:342
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
ARMBaseInstrInfo.h
llvm::tryFoldSPUpdateIntoPushPop
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
Definition: ARMBaseInstrInfo.cpp:2518
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:526
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
R6
#define R6(n)
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ARMFunctionInfo::setFramePtrSpillOffset
void setFramePtrSpillOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:192
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:357
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:779
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:238
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:276
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
Compiler.h
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMFunctionInfo::setGPRCalleeSavedArea2Offset
void setGPRCalleeSavedArea2Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:202
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:201
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::ARMFunctionInfo::setGPRCalleeSavedArea1Offset
void setGPRCalleeSavedArea1Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:201
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:593
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:377
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:127
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:432
ARMRegSet
std::bitset< ARM::NUM_TARGET_REGS > ARMRegSet
Definition: Thumb1FrameLowering.cpp:792
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:33
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1312
MachineFrameInfo.h
llvm::Thumb1InstrInfo
Definition: Thumb1InstrInfo.h:22
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaOffset
void setDPRCalleeSavedAreaOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:203
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:257
llvm::Thumb1FrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: Thumb1FrameLowering.cpp:53
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:385
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
SmallVector.h
llvm::ARMFrameLowering::STI
const ARMSubtarget & STI
Definition: ARMFrameLowering.h:23
llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: Thumb1FrameLowering.cpp:115
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
MachineInstrBuilder.h
llvm::ARMFunctionInfo::hasStackFrame
bool hasStackFrame() const
Definition: ARMMachineFunctionInfo.h:182
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:293
llvm::ThumbRegisterInfo
Definition: ThumbRegisterInfo.h:25
llvm::emitThumbRegPlusImmediate
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Definition: ThumbRegisterInfo.cpp:185
llvm::ARMFunctionInfo::getArgRegsSaveSize
unsigned getArgRegsSaveSize() const
Definition: ARMMachineFunctionInfo.h:176
MachineOperand.h
llvm::ARMBaseRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:412
llvm::isARMLowRegister
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
llvm::MachineFrameInfo::setOffsetAdjustment
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
Definition: MachineFrameInfo.h:589
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:564
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:542
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::Thumb1FrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: Thumb1FrameLowering.cpp:805
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
findNextOrderedReg
static const unsigned * findNextOrderedReg(const unsigned *CurrentReg, const ARMRegSet &EnabledRegs, const unsigned *OrderEnd)
Definition: Thumb1FrameLowering.cpp:797
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:157
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:280
LivePhysRegs.h