LLVM  14.0.0git
Thumb1FrameLowering.cpp
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1 //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb1 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb1FrameLowering.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMSubtarget.h"
18 #include "Thumb1InstrInfo.h"
19 #include "ThumbRegisterInfo.h"
20 #include "Utils/ARMBaseInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/IR/DebugLoc.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCDwarf.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/Support/Compiler.h"
43 #include <bitset>
44 #include <cassert>
45 #include <iterator>
46 #include <vector>
47 
48 using namespace llvm;
49 
51  : ARMFrameLowering(sti) {}
52 
54  const MachineFrameInfo &MFI = MF.getFrameInfo();
55  unsigned CFSize = MFI.getMaxCallFrameSize();
56  // It's not always a good idea to include the call frame as part of the
57  // stack frame. ARM (especially Thumb) has small immediate offset to
58  // address the stack frame. So a large call frame can cause poor codegen
59  // and may even makes it impossible to scavenge a register.
60  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
61  return false;
62 
63  return !MFI.hasVarSizedObjects();
64 }
65 
66 static void
69  const TargetInstrInfo &TII, const DebugLoc &dl,
70  const ThumbRegisterInfo &MRI, int NumBytes,
71  unsigned ScratchReg, unsigned MIFlags) {
72  // If it would take more than three instructions to adjust the stack pointer
73  // using tADDspi/tSUBspi, load an immediate instead.
74  if (std::abs(NumBytes) > 508 * 3) {
75  // We use a different codepath here from the normal
76  // emitThumbRegPlusImmediate so we don't have to deal with register
77  // scavenging. (Scavenging could try to use the emergency spill slot
78  // before we've actually finished setting up the stack.)
79  if (ScratchReg == ARM::NoRegister)
80  report_fatal_error("Failed to emit Thumb1 stack adjustment");
81  MachineFunction &MF = *MBB.getParent();
83  if (ST.genExecuteOnly()) {
84  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
85  .addImm(NumBytes).setMIFlags(MIFlags);
86  } else {
87  MRI.emitLoadConstPool(MBB, MBBI, dl, ScratchReg, 0, NumBytes, ARMCC::AL,
88  0, MIFlags);
89  }
90  BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
91  .addReg(ARM::SP)
92  .addReg(ScratchReg, RegState::Kill)
94  .setMIFlags(MIFlags);
95  return;
96  }
97  // FIXME: This is assuming the heuristics in emitThumbRegPlusImmediate
98  // won't change.
99  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
100  MRI, MIFlags);
101 
102 }
103 
106  const TargetInstrInfo &TII, const DebugLoc &dl,
107  const ThumbRegisterInfo &MRI, int NumBytes,
108  unsigned MIFlags = MachineInstr::NoFlags) {
109  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
110  MRI, MIFlags);
111 }
112 
113 
117  const Thumb1InstrInfo &TII =
118  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
119  const ThumbRegisterInfo *RegInfo =
120  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
121  if (!hasReservedCallFrame(MF)) {
122  // If we have alloca, convert as follows:
123  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
124  // ADJCALLSTACKUP -> add, sp, sp, amount
125  MachineInstr &Old = *I;
126  DebugLoc dl = Old.getDebugLoc();
127  unsigned Amount = TII.getFrameSize(Old);
128  if (Amount != 0) {
129  // We need to keep the stack aligned properly. To do this, we round the
130  // amount of space needed for the outgoing arguments up to the next
131  // alignment boundary.
132  Amount = alignTo(Amount, getStackAlign());
133 
134  // Replace the pseudo instruction with a new instruction...
135  unsigned Opc = Old.getOpcode();
136  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
137  emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
138  } else {
139  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
140  emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
141  }
142  }
143  }
144  return MBB.erase(I);
145 }
146 
148  MachineBasicBlock &MBB) const {
150  MachineFrameInfo &MFI = MF.getFrameInfo();
152  MachineModuleInfo &MMI = MF.getMMI();
153  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
154  const ThumbRegisterInfo *RegInfo =
155  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
156  const Thumb1InstrInfo &TII =
157  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
158 
159  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
160  unsigned NumBytes = MFI.getStackSize();
161  assert(NumBytes >= ArgRegsSaveSize &&
162  "ArgRegsSaveSize is included in NumBytes");
163  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
164 
165  // Debug location must be unknown since the first debug location is used
166  // to determine the end of the prologue.
167  DebugLoc dl;
168 
169  Register FramePtr = RegInfo->getFrameRegister(MF);
170  unsigned BasePtr = RegInfo->getBaseRegister();
171  int CFAOffset = 0;
172 
173  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
174  NumBytes = (NumBytes + 3) & ~3;
175  MFI.setStackSize(NumBytes);
176 
177  // Determine the sizes of each callee-save spill areas and record which frame
178  // belongs to which callee-save spill areas.
179  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
180  int FramePtrSpillFI = 0;
181 
182  if (ArgRegsSaveSize) {
183  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
184  ARM::NoRegister, MachineInstr::FrameSetup);
185  CFAOffset += ArgRegsSaveSize;
186  unsigned CFIIndex =
187  MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
188  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
189  .addCFIIndex(CFIIndex)
191  }
192 
193  if (!AFI->hasStackFrame()) {
194  if (NumBytes - ArgRegsSaveSize != 0) {
195  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
196  -(NumBytes - ArgRegsSaveSize),
197  ARM::NoRegister, MachineInstr::FrameSetup);
198  CFAOffset += NumBytes - ArgRegsSaveSize;
199  unsigned CFIIndex = MF.addFrameInst(
200  MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
201  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
202  .addCFIIndex(CFIIndex)
204  }
205  return;
206  }
207 
208  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
209  unsigned Reg = CSI[i].getReg();
210  int FI = CSI[i].getFrameIdx();
211  switch (Reg) {
212  case ARM::R8:
213  case ARM::R9:
214  case ARM::R10:
215  case ARM::R11:
216  if (STI.splitFramePushPop(MF)) {
217  GPRCS2Size += 4;
218  break;
219  }
221  case ARM::R4:
222  case ARM::R5:
223  case ARM::R6:
224  case ARM::R7:
225  case ARM::LR:
226  if (Reg == FramePtr)
227  FramePtrSpillFI = FI;
228  GPRCS1Size += 4;
229  break;
230  default:
231  DPRCSSize += 8;
232  }
233  }
234 
235  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
236  ++MBBI;
237  }
238 
239  // Determine starting offsets of spill areas.
240  unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
241  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
242  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
243  bool HasFP = hasFP(MF);
244  if (HasFP)
245  AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
246  NumBytes);
247  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
248  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
249  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
250  NumBytes = DPRCSOffset;
251 
252  int FramePtrOffsetInBlock = 0;
253  unsigned adjustedGPRCS1Size = GPRCS1Size;
254  if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
255  tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
256  FramePtrOffsetInBlock = NumBytes;
257  adjustedGPRCS1Size += NumBytes;
258  NumBytes = 0;
259  }
260 
261  if (adjustedGPRCS1Size) {
262  CFAOffset += adjustedGPRCS1Size;
263  unsigned CFIIndex =
264  MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
265  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
266  .addCFIIndex(CFIIndex)
268  }
269  for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
270  E = CSI.end(); I != E; ++I) {
271  unsigned Reg = I->getReg();
272  int FI = I->getFrameIdx();
273  switch (Reg) {
274  case ARM::R8:
275  case ARM::R9:
276  case ARM::R10:
277  case ARM::R11:
278  case ARM::R12:
279  if (STI.splitFramePushPop(MF))
280  break;
282  case ARM::R0:
283  case ARM::R1:
284  case ARM::R2:
285  case ARM::R3:
286  case ARM::R4:
287  case ARM::R5:
288  case ARM::R6:
289  case ARM::R7:
290  case ARM::LR:
291  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
292  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
293  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
294  .addCFIIndex(CFIIndex)
296  break;
297  }
298  }
299 
300  // Adjust FP so it point to the stack slot that contains the previous FP.
301  if (HasFP) {
302  FramePtrOffsetInBlock +=
303  MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
304  BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
305  .addReg(ARM::SP)
306  .addImm(FramePtrOffsetInBlock / 4)
308  .add(predOps(ARMCC::AL));
309  if(FramePtrOffsetInBlock) {
310  CFAOffset -= FramePtrOffsetInBlock;
311  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
312  nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
313  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
314  .addCFIIndex(CFIIndex)
316  } else {
317  unsigned CFIIndex =
319  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
320  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
321  .addCFIIndex(CFIIndex)
323  }
324  if (NumBytes > 508)
325  // If offset is > 508 then sp cannot be adjusted in a single instruction,
326  // try restoring from fp instead.
327  AFI->setShouldRestoreSPFromFP(true);
328  }
329 
330  // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
331  // and tMOVr instructions. We don't need to add any call frame information
332  // in-between these instructions, because they do not modify the high
333  // registers.
334  while (true) {
336  // Skip a run of tMOVr instructions
337  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
338  MBBI++;
339  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
340  MBBI++;
341  } else {
342  // We have reached an instruction which is not a push, so the previous
343  // run of tMOVr instructions (which may have been empty) was not part of
344  // the prologue. Reset MBBI back to the last PUSH of the prologue.
345  MBBI = OldMBBI;
346  break;
347  }
348  }
349 
350  // Emit call frame information for the callee-saved high registers.
351  for (auto &I : CSI) {
352  unsigned Reg = I.getReg();
353  int FI = I.getFrameIdx();
354  switch (Reg) {
355  case ARM::R8:
356  case ARM::R9:
357  case ARM::R10:
358  case ARM::R11:
359  case ARM::R12: {
360  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
361  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
362  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
363  .addCFIIndex(CFIIndex)
365  break;
366  }
367  default:
368  break;
369  }
370  }
371 
372  if (NumBytes) {
373  // Insert it after all the callee-save spills.
374  //
375  // For a large stack frame, we might need a scratch register to store
376  // the size of the frame. We know all callee-save registers are free
377  // at this point in the prologue, so pick one.
378  unsigned ScratchRegister = ARM::NoRegister;
379  for (auto &I : CSI) {
380  unsigned Reg = I.getReg();
381  if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
382  ScratchRegister = Reg;
383  break;
384  }
385  }
386  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
387  ScratchRegister, MachineInstr::FrameSetup);
388  if (!HasFP) {
389  CFAOffset += NumBytes;
390  unsigned CFIIndex = MF.addFrameInst(
391  MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
392  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
393  .addCFIIndex(CFIIndex)
395  }
396  }
397 
398  if (STI.isTargetELF() && HasFP)
400  AFI->getFramePtrSpillOffset());
401 
402  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
403  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
404  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
405 
406  if (RegInfo->hasStackRealignment(MF)) {
407  const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
408  // Emit the following sequence, using R4 as a temporary, since we cannot use
409  // SP as a source or destination register for the shifts:
410  // mov r4, sp
411  // lsrs r4, r4, #NrBitsToZero
412  // lsls r4, r4, #NrBitsToZero
413  // mov sp, r4
414  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
415  .addReg(ARM::SP, RegState::Kill)
416  .add(predOps(ARMCC::AL));
417 
418  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
419  .addDef(ARM::CPSR)
421  .addImm(NrBitsToZero)
422  .add(predOps(ARMCC::AL));
423 
424  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
425  .addDef(ARM::CPSR)
427  .addImm(NrBitsToZero)
428  .add(predOps(ARMCC::AL));
429 
430  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
432  .add(predOps(ARMCC::AL));
433 
434  AFI->setShouldRestoreSPFromFP(true);
435  }
436 
437  // If we need a base pointer, set it up here. It's whatever the value
438  // of the stack pointer is at this point. Any variable size objects
439  // will be allocated after this, so we can still use the base pointer
440  // to reference locals.
441  if (RegInfo->hasBasePointer(MF))
442  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
443  .addReg(ARM::SP)
444  .add(predOps(ARMCC::AL));
445 
446  // If the frame has variable sized objects then the epilogue must restore
447  // the sp from fp. We can assume there's an FP here since hasFP already
448  // checks for hasVarSizedObjects.
449  if (MFI.hasVarSizedObjects())
450  AFI->setShouldRestoreSPFromFP(true);
451 
452  // In some cases, virtual registers have been introduced, e.g. by uses of
453  // emitThumbRegPlusImmInReg.
455 }
456 
457 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
458  if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
459  isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
460  return true;
461  else if (MI.getOpcode() == ARM::tPOP) {
462  return true;
463  } else if (MI.getOpcode() == ARM::tMOVr) {
464  Register Dst = MI.getOperand(0).getReg();
465  Register Src = MI.getOperand(1).getReg();
466  return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
467  ARM::hGPRRegClass.contains(Dst));
468  }
469  return false;
470 }
471 
473  MachineBasicBlock &MBB) const {
475  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
476  MachineFrameInfo &MFI = MF.getFrameInfo();
478  const ThumbRegisterInfo *RegInfo =
479  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
480  const Thumb1InstrInfo &TII =
481  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
482 
483  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
484  int NumBytes = (int)MFI.getStackSize();
485  assert((unsigned)NumBytes >= ArgRegsSaveSize &&
486  "ArgRegsSaveSize is included in NumBytes");
487  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
488  Register FramePtr = RegInfo->getFrameRegister(MF);
489 
490  if (!AFI->hasStackFrame()) {
491  if (NumBytes - ArgRegsSaveSize != 0)
492  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
493  NumBytes - ArgRegsSaveSize, ARM::NoRegister,
495  } else {
496  // Unwind MBBI to point to first LDR / VLDRD.
497  if (MBBI != MBB.begin()) {
498  do
499  --MBBI;
500  while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
501  if (!isCSRestore(*MBBI, CSRegs))
502  ++MBBI;
503  }
504 
505  // Move SP to start of FP callee save spill area.
506  NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
509  ArgRegsSaveSize);
510 
511  if (AFI->shouldRestoreSPFromFP()) {
512  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
513  // Reset SP based on frame pointer only if the stack frame extends beyond
514  // frame pointer stack slot, the target is ELF and the function has FP, or
515  // the target uses var sized objects.
516  if (NumBytes) {
517  assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
518  "No scratch register to restore SP from FP!");
520  TII, *RegInfo);
521  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
522  .addReg(ARM::R4)
523  .add(predOps(ARMCC::AL));
524  } else
525  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
526  .addReg(FramePtr)
527  .add(predOps(ARMCC::AL));
528  } else {
529  // For a large stack frame, we might need a scratch register to store
530  // the size of the frame. We know all callee-save registers are free
531  // at this point in the epilogue, so pick one.
532  unsigned ScratchRegister = ARM::NoRegister;
533  bool HasFP = hasFP(MF);
534  for (auto &I : MFI.getCalleeSavedInfo()) {
535  unsigned Reg = I.getReg();
536  if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
537  ScratchRegister = Reg;
538  break;
539  }
540  }
541  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
542  &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
543  MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
544  if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
545  emitPrologueEpilogueSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes,
546  ScratchRegister, MachineInstr::NoFlags);
547  } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
548  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes,
549  ScratchRegister, MachineInstr::NoFlags);
550  }
551  }
552 
553  if (needPopSpecialFixUp(MF)) {
554  bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
555  (void)Done;
556  assert(Done && "Emission of the special fixup failed!?");
557  }
558 }
559 
561  if (!needPopSpecialFixUp(*MBB.getParent()))
562  return true;
563 
564  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
565  return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
566 }
567 
568 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
569  ARMFunctionInfo *AFI =
570  const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
571  if (AFI->getArgRegsSaveSize())
572  return true;
573 
574  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
575  for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
576  if (CSI.getReg() == ARM::LR)
577  return true;
578 
579  return false;
580 }
581 
582 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
583  const BitVector &PopFriendly,
584  const LivePhysRegs &UsedRegs, unsigned &PopReg,
585  unsigned &TmpReg, MachineRegisterInfo &MRI) {
586  PopReg = TmpReg = 0;
587  for (auto Reg : GPRsNoLRSP.set_bits()) {
588  if (UsedRegs.available(MRI, Reg)) {
589  // Remember the first pop-friendly register and exit.
590  if (PopFriendly.test(Reg)) {
591  PopReg = Reg;
592  TmpReg = 0;
593  break;
594  }
595  // Otherwise, remember that the register will be available to
596  // save a pop-friendly register.
597  TmpReg = Reg;
598  }
599  }
600 }
601 
602 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
603  bool DoIt) const {
604  MachineFunction &MF = *MBB.getParent();
606  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
607  const TargetInstrInfo &TII = *STI.getInstrInfo();
608  const ThumbRegisterInfo *RegInfo =
609  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
610 
611  // If MBBI is a return instruction, or is a tPOP followed by a return
612  // instruction in the successor BB, we may be able to directly restore
613  // LR in the PC.
614  // This is only possible with v5T ops (v4T can't change the Thumb bit via
615  // a POP PC instruction), and only if we do not need to emit any SP update.
616  // Otherwise, we need a temporary register to pop the value
617  // and copy that value into LR.
618  auto MBBI = MBB.getFirstTerminator();
619  bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
620  if (CanRestoreDirectly) {
621  if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
622  CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
623  MBBI->getOpcode() == ARM::tPOP_RET);
624  else {
625  auto MBBI_prev = MBBI;
626  MBBI_prev--;
627  assert(MBBI_prev->getOpcode() == ARM::tPOP);
628  assert(MBB.succ_size() == 1);
629  if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
630  MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
631  else
632  CanRestoreDirectly = false;
633  }
634  }
635 
636  if (CanRestoreDirectly) {
637  if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
638  return true;
639  MachineInstrBuilder MIB =
640  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
641  .add(predOps(ARMCC::AL));
642  // Copy implicit ops and popped registers, if any.
643  for (auto MO: MBBI->operands())
644  if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
645  MIB.add(MO);
646  MIB.addReg(ARM::PC, RegState::Define);
647  // Erase the old instruction (tBX_RET or tPOP).
648  MBB.erase(MBBI);
649  return true;
650  }
651 
652  // Look for a temporary register to use.
653  // First, compute the liveness information.
655  LivePhysRegs UsedRegs(TRI);
656  UsedRegs.addLiveOuts(MBB);
657  // The semantic of pristines changed recently and now,
658  // the callee-saved registers that are touched in the function
659  // are not part of the pristines set anymore.
660  // Add those callee-saved now.
661  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
662  for (unsigned i = 0; CSRegs[i]; ++i)
663  UsedRegs.addReg(CSRegs[i]);
664 
665  DebugLoc dl = DebugLoc();
666  if (MBBI != MBB.end()) {
667  dl = MBBI->getDebugLoc();
668  auto InstUpToMBBI = MBB.end();
669  while (InstUpToMBBI != MBBI)
670  // The pre-decrement is on purpose here.
671  // We want to have the liveness right before MBBI.
672  UsedRegs.stepBackward(*--InstUpToMBBI);
673  }
674 
675  // Look for a register that can be directly use in the POP.
676  unsigned PopReg = 0;
677  // And some temporary register, just in case.
678  unsigned TemporaryReg = 0;
679  BitVector PopFriendly =
680  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
681  // R7 may be used as a frame pointer, hence marked as not generally
682  // allocatable, however there's no reason to not use it as a temporary for
683  // restoring LR.
684  if (STI.getFramePointerReg() == ARM::R7)
685  PopFriendly.set(ARM::R7);
686 
687  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
688  // Rebuild the GPRs from the high registers because they are removed
689  // form the GPR reg class for thumb1.
690  BitVector GPRsNoLRSP =
691  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
692  GPRsNoLRSP |= PopFriendly;
693  GPRsNoLRSP.reset(ARM::LR);
694  GPRsNoLRSP.reset(ARM::SP);
695  GPRsNoLRSP.reset(ARM::PC);
696  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg,
697  MF.getRegInfo());
698 
699  // If we couldn't find a pop-friendly register, try restoring LR before
700  // popping the other callee-saved registers, so we could use one of them as a
701  // temporary.
702  bool UseLDRSP = false;
703  if (!PopReg && MBBI != MBB.begin()) {
704  auto PrevMBBI = MBBI;
705  PrevMBBI--;
706  if (PrevMBBI->getOpcode() == ARM::tPOP) {
707  UsedRegs.stepBackward(*PrevMBBI);
708  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg,
709  TemporaryReg, MF.getRegInfo());
710  if (PopReg) {
711  MBBI = PrevMBBI;
712  UseLDRSP = true;
713  }
714  }
715  }
716 
717  if (!DoIt && !PopReg && !TemporaryReg)
718  return false;
719 
720  assert((PopReg || TemporaryReg) && "Cannot get LR");
721 
722  if (UseLDRSP) {
723  assert(PopReg && "Do not know how to get LR");
724  // Load the LR via LDR tmp, [SP, #off]
725  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
726  .addReg(PopReg, RegState::Define)
727  .addReg(ARM::SP)
728  .addImm(MBBI->getNumExplicitOperands() - 2)
729  .add(predOps(ARMCC::AL));
730  // Move from the temporary register to the LR.
731  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
732  .addReg(ARM::LR, RegState::Define)
733  .addReg(PopReg, RegState::Kill)
734  .add(predOps(ARMCC::AL));
735  // Advance past the pop instruction.
736  MBBI++;
737  // Increment the SP.
738  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
739  ArgRegsSaveSize + 4, ARM::NoRegister,
741  return true;
742  }
743 
744  if (TemporaryReg) {
745  assert(!PopReg && "Unnecessary MOV is about to be inserted");
746  PopReg = PopFriendly.find_first();
747  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
748  .addReg(TemporaryReg, RegState::Define)
749  .addReg(PopReg, RegState::Kill)
750  .add(predOps(ARMCC::AL));
751  }
752 
753  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
754  // We couldn't use the direct restoration above, so
755  // perform the opposite conversion: tPOP_RET to tPOP.
756  MachineInstrBuilder MIB =
757  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
758  .add(predOps(ARMCC::AL));
759  bool Popped = false;
760  for (auto MO: MBBI->operands())
761  if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
762  MO.getReg() != ARM::PC) {
763  MIB.add(MO);
764  if (!MO.isImplicit())
765  Popped = true;
766  }
767  // Is there anything left to pop?
768  if (!Popped)
769  MBB.erase(MIB.getInstr());
770  // Erase the old instruction.
771  MBB.erase(MBBI);
772  MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
773  .add(predOps(ARMCC::AL));
774  }
775 
776  assert(PopReg && "Do not know how to get LR");
777  BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
779  .addReg(PopReg, RegState::Define);
780 
781  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize,
782  ARM::NoRegister, MachineInstr::NoFlags);
783 
784  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
785  .addReg(ARM::LR, RegState::Define)
786  .addReg(PopReg, RegState::Kill)
787  .add(predOps(ARMCC::AL));
788 
789  if (TemporaryReg)
790  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
791  .addReg(PopReg, RegState::Define)
792  .addReg(TemporaryReg, RegState::Kill)
793  .add(predOps(ARMCC::AL));
794 
795  return true;
796 }
797 
798 using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
799 
800 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
801 // or OrderEnd if no further registers are in that set. This does not advance
802 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
803 static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
804  const ARMRegSet &EnabledRegs,
805  const unsigned *OrderEnd) {
806  while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
807  ++CurrentReg;
808  return CurrentReg;
809 }
810 
814  if (CSI.empty())
815  return false;
816 
817  DebugLoc DL;
818  const TargetInstrInfo &TII = *STI.getInstrInfo();
819  MachineFunction &MF = *MBB.getParent();
820  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
822 
823  ARMRegSet LoRegsToSave; // r0-r7, lr
824  ARMRegSet HiRegsToSave; // r8-r11
825  ARMRegSet CopyRegs; // Registers which can be used after pushing
826  // LoRegs for saving HiRegs.
827 
828  for (unsigned i = CSI.size(); i != 0; --i) {
829  unsigned Reg = CSI[i-1].getReg();
830 
831  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
832  LoRegsToSave[Reg] = true;
833  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
834  HiRegsToSave[Reg] = true;
835  } else {
836  llvm_unreachable("callee-saved register of unexpected class");
837  }
838 
839  if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
840  !MF.getRegInfo().isLiveIn(Reg) &&
841  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
842  CopyRegs[Reg] = true;
843  }
844 
845  // Unused argument registers can be used for the high register saving.
846  for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
847  if (!MF.getRegInfo().isLiveIn(ArgReg))
848  CopyRegs[ArgReg] = true;
849 
850  // Push the low registers and lr
851  const MachineRegisterInfo &MRI = MF.getRegInfo();
852  if (!LoRegsToSave.none()) {
853  MachineInstrBuilder MIB =
854  BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
855  for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
856  if (LoRegsToSave[Reg]) {
857  bool isKill = !MRI.isLiveIn(Reg);
858  if (isKill && !MRI.isReserved(Reg))
859  MBB.addLiveIn(Reg);
860 
861  MIB.addReg(Reg, getKillRegState(isKill));
862  }
863  }
865  }
866 
867  // Push the high registers. There are no store instructions that can access
868  // these registers directly, so we have to move them to low registers, and
869  // push them. This might take multiple pushes, as it is possible for there to
870  // be fewer low registers available than high registers which need saving.
871 
872  // These are in reverse order so that in the case where we need to use
873  // multiple PUSH instructions, the order of the registers on the stack still
874  // matches the unwind info. They need to be swicthed back to ascending order
875  // before adding to the PUSH instruction.
876  static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
877  ARM::R5, ARM::R4, ARM::R3,
878  ARM::R2, ARM::R1, ARM::R0};
879  static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
880 
881  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
882  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
883 
884  // Find the first register to save.
885  const unsigned *HiRegToSave = findNextOrderedReg(
886  std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
887 
888  while (HiRegToSave != AllHighRegsEnd) {
889  // Find the first low register to use.
890  const unsigned *CopyReg =
891  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
892 
893  // Create the PUSH, but don't insert it yet (the MOVs need to come first).
894  MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH))
897 
898  SmallVector<unsigned, 4> RegsToPush;
899  while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
900  if (HiRegsToSave[*HiRegToSave]) {
901  bool isKill = !MRI.isLiveIn(*HiRegToSave);
902  if (isKill && !MRI.isReserved(*HiRegToSave))
903  MBB.addLiveIn(*HiRegToSave);
904 
905  // Emit a MOV from the high reg to the low reg.
906  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
907  .addReg(*CopyReg, RegState::Define)
908  .addReg(*HiRegToSave, getKillRegState(isKill))
911 
912  // Record the register that must be added to the PUSH.
913  RegsToPush.push_back(*CopyReg);
914 
915  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
916  HiRegToSave =
917  findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
918  }
919  }
920 
921  // Add the low registers to the PUSH, in ascending order.
922  for (unsigned Reg : llvm::reverse(RegsToPush))
923  PushMIB.addReg(Reg, RegState::Kill);
924 
925  // Insert the PUSH instruction after the MOVs.
926  MBB.insert(MI, PushMIB);
927  }
928 
929  return true;
930 }
931 
935  if (CSI.empty())
936  return false;
937 
938  MachineFunction &MF = *MBB.getParent();
940  const TargetInstrInfo &TII = *STI.getInstrInfo();
941  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
943 
944  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
945  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
946 
947  ARMRegSet LoRegsToRestore;
948  ARMRegSet HiRegsToRestore;
949  // Low registers (r0-r7) which can be used to restore the high registers.
950  ARMRegSet CopyRegs;
951 
952  for (CalleeSavedInfo I : CSI) {
953  unsigned Reg = I.getReg();
954 
955  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
956  LoRegsToRestore[Reg] = true;
957  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
958  HiRegsToRestore[Reg] = true;
959  } else {
960  llvm_unreachable("callee-saved register of unexpected class");
961  }
962 
963  // If this is a low register not used as the frame pointer, we may want to
964  // use it for restoring the high registers.
965  if ((ARM::tGPRRegClass.contains(Reg)) &&
966  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
967  CopyRegs[Reg] = true;
968  }
969 
970  // If this is a return block, we may be able to use some unused return value
971  // registers for restoring the high regs.
973  if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
974  CopyRegs[ARM::R0] = true;
975  CopyRegs[ARM::R1] = true;
976  CopyRegs[ARM::R2] = true;
977  CopyRegs[ARM::R3] = true;
978  for (auto Op : Terminator->implicit_operands()) {
979  if (Op.isReg())
980  CopyRegs[Op.getReg()] = false;
981  }
982  }
983 
984  static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
985  ARM::R4, ARM::R5, ARM::R6, ARM::R7};
986  static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
987 
988  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
989  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
990 
991  // Find the first register to restore.
992  auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
993  HiRegsToRestore, AllHighRegsEnd);
994 
995  while (HiRegToRestore != AllHighRegsEnd) {
996  assert(!CopyRegs.none());
997  // Find the first low register to use.
998  auto CopyReg =
999  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
1000 
1001  // Create the POP instruction.
1002  MachineInstrBuilder PopMIB =
1003  BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
1004 
1005  while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
1006  // Add the low register to the POP.
1007  PopMIB.addReg(*CopyReg, RegState::Define);
1008 
1009  // Create the MOV from low to high register.
1010  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
1011  .addReg(*HiRegToRestore, RegState::Define)
1012  .addReg(*CopyReg, RegState::Kill)
1013  .add(predOps(ARMCC::AL));
1014 
1015  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
1016  HiRegToRestore =
1017  findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
1018  }
1019  }
1020 
1021  MachineInstrBuilder MIB =
1022  BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
1023 
1024  bool NeedsPop = false;
1025  for (unsigned i = CSI.size(); i != 0; --i) {
1026  CalleeSavedInfo &Info = CSI[i-1];
1027  unsigned Reg = Info.getReg();
1028 
1029  // High registers (excluding lr) have already been dealt with
1030  if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
1031  continue;
1032 
1033  if (Reg == ARM::LR) {
1034  Info.setRestored(false);
1035  if (!MBB.succ_empty() ||
1036  MI->getOpcode() == ARM::TCRETURNdi ||
1037  MI->getOpcode() == ARM::TCRETURNri)
1038  // LR may only be popped into PC, as part of return sequence.
1039  // If this isn't the return sequence, we'll need emitPopSpecialFixUp
1040  // to restore LR the hard way.
1041  // FIXME: if we don't pass any stack arguments it would be actually
1042  // advantageous *and* correct to do the conversion to an ordinary call
1043  // instruction here.
1044  continue;
1045  // Special epilogue for vararg functions. See emitEpilogue
1046  if (isVarArg)
1047  continue;
1048  // ARMv4T requires BX, see emitEpilogue
1049  if (!STI.hasV5TOps())
1050  continue;
1051 
1052  // CMSE entry functions must return via BXNS, see emitEpilogue.
1053  if (AFI->isCmseNSEntryFunction())
1054  continue;
1055 
1056  // Pop LR into PC.
1057  Reg = ARM::PC;
1058  (*MIB).setDesc(TII.get(ARM::tPOP_RET));
1059  if (MI != MBB.end())
1060  MIB.copyImplicitOps(*MI);
1061  MI = MBB.erase(MI);
1062  }
1063  MIB.addReg(Reg, getDefRegState(true));
1064  NeedsPop = true;
1065  }
1066 
1067  // It's illegal to emit pop instruction without operands.
1068  if (NeedsPop)
1069  MBB.insert(MI, &*MIB);
1070  else
1071  MF.DeleteMachineInstr(MIB);
1072 
1073  return true;
1074 }
llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: Thumb1FrameLowering.cpp:932
i
i
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ARMSubtarget.h
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Definition: Alignment.h:148
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Definition: MachineFrameInfo.h:353
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Definition: ARMMachineFunctionInfo.h:27
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Definition: IRTranslator.cpp:103
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Definition: ARMSubtarget.h:609
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Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
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---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:315
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Definition: ARMMachineFunctionInfo.h:197
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Definition: ARMSubtarget.h:46
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Definition: MachineRegisterInfo.h:52
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const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
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Definition: ARMMachineFunctionInfo.h:169
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Definition: BitVector.h:343
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Definition: ARMMachineFunctionInfo.h:196
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Definition: Thumb1FrameLowering.cpp:50
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Definition: MachineInstrBuilder.h:247
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llvm::SmallVector< unsigned, 4 >
ErrorHandling.h
llvm::TargetRegisterInfo::getAllocatableSet
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Definition: TargetRegisterInfo.cpp:255
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Definition: ARMMachineFunctionInfo.h:190
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Definition: Thumb1FrameLowering.cpp:67
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Definition: BitVector.h:132
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Return the correction for frame offsets.
Definition: MachineFrameInfo.h:562
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Definition: ARMMachineFunctionInfo.h:191
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Definition: LivePhysRegs.h:48
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Definition: TargetSubtargetInfo.h:124
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Definition: TargetRegisterInfo.h:233
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bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: Thumb1FrameLowering.cpp:560
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Set the size of the stack.
Definition: MachineFrameInfo.h:556
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Get end iterator over path.
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Definition: Path.cpp:224
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:565
Thumb1InstrInfo.h
Thumb1FrameLowering.h
STLExtras.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:622
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:502
MachineRegisterInfo.h
llvm::ARMBaseRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: ARMBaseRegisterInfo.h:182
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::ARMFunctionInfo::getDPRCalleeSavedAreaSize
unsigned getDPRCalleeSavedAreaSize() const
Definition: ARMMachineFunctionInfo.h:193
llvm::ARMFunctionInfo::isCmseNSEntryFunction
bool isCmseNSEntryFunction() const
Definition: ARMMachineFunctionInfo.h:154
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
findTemporariesForLR
static void findTemporariesForLR(const BitVector &GPRsNoLRSP, const BitVector &PopFriendly, const LivePhysRegs &UsedRegs, unsigned &PopReg, unsigned &TmpReg, MachineRegisterInfo &MRI)
Definition: Thumb1FrameLowering.cpp:582
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:836
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
R2
#define R2(n)
llvm::Thumb1FrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: Thumb1FrameLowering.cpp:147
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::ARMFunctionInfo::setShouldRestoreSPFromFP
void setShouldRestoreSPFromFP(bool s)
Definition: ARMMachineFunctionInfo.h:170
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::Thumb1FrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: Thumb1FrameLowering.cpp:472
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::ARMBaseRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:479
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:915
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaSize
void setDPRCalleeSavedAreaSize(unsigned s)
Definition: ARMMachineFunctionInfo.h:199
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:207
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
MCContext.h
llvm::MachineFunction::DeleteMachineInstr
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
Definition: MachineFunction.cpp:393
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:717
emitCallSPUpdate
static void emitCallSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags)
Definition: Thumb1FrameLowering.cpp:104
FramePtr
static const unsigned FramePtr
Definition: XCoreFrameLowering.cpp:34
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::ARMFunctionInfo::getFramePtrSpillOffset
unsigned getFramePtrSpillOffset() const
Definition: ARMMachineFunctionInfo.h:175
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
ARMBaseInfo.h
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:78
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
DebugLoc.h
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
ThumbRegisterInfo.h
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::BitVector
Definition: BitVector.h:74
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:495
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::ARMFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: ARMFrameLowering.cpp:200
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:577
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
ARMBaseRegisterInfo.h
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::BitVector::any
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:162
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::LivePhysRegs::available
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
Definition: LivePhysRegs.cpp:139
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:826
MCRegisterInfo.h
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:757
llvm::isCalleeSavedRegister
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
Definition: ARMBaseRegisterInfo.h:92
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
ARMBaseInstrInfo.h
llvm::tryFoldSPUpdateIntoPushPop
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
Definition: ARMBaseInstrInfo.cpp:2523
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
R6
#define R6(n)
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARMFunctionInfo::setFramePtrSpillOffset
void setFramePtrSpillOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:176
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:347
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:755
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:577
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
Compiler.h
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMFunctionInfo::setGPRCalleeSavedArea2Offset
void setGPRCalleeSavedArea2Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:186
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:174
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::ARMFunctionInfo::setGPRCalleeSavedArea1Offset
void setGPRCalleeSavedArea1Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:185
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:569
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:100
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:436
ARMRegSet
std::bitset< ARM::NUM_TARGET_REGS > ARMRegSet
Definition: Thumb1FrameLowering.cpp:798
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1312
MachineFrameInfo.h
llvm::Thumb1InstrInfo
Definition: Thumb1InstrInfo.h:22
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaOffset
void setDPRCalleeSavedAreaOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:187
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
llvm::Thumb1FrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: Thumb1FrameLowering.cpp:53
isCSRestore
static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs)
Definition: Thumb1FrameLowering.cpp:457
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:384
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:285
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
SmallVector.h
llvm::ARMFrameLowering::STI
const ARMSubtarget & STI
Definition: ARMFrameLowering.h:23
llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: Thumb1FrameLowering.cpp:115
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::ARMFunctionInfo::hasStackFrame
bool hasStackFrame() const
Definition: ARMMachineFunctionInfo.h:166
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:292
llvm::ThumbRegisterInfo
Definition: ThumbRegisterInfo.h:25
llvm::emitThumbRegPlusImmediate
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Definition: ThumbRegisterInfo.cpp:185
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::ARMFunctionInfo::getArgRegsSaveSize
unsigned getArgRegsSaveSize() const
Definition: ARMMachineFunctionInfo.h:160
MachineOperand.h
llvm::ARMBaseRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:410
llvm::isARMLowRegister
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
llvm::MachineFrameInfo::setOffsetAdjustment
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
Definition: MachineFrameInfo.h:565
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:526
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:541
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::Thumb1FrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: Thumb1FrameLowering.cpp:811
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1284
findNextOrderedReg
static const unsigned * findNextOrderedReg(const unsigned *CurrentReg, const ARMRegSet &EnabledRegs, const unsigned *OrderEnd)
Definition: Thumb1FrameLowering.cpp:803
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:155
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
LivePhysRegs.h