LLVM  16.0.0git
Thumb1FrameLowering.cpp
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1 //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb1 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb1FrameLowering.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMSubtarget.h"
18 #include "Thumb1InstrInfo.h"
19 #include "ThumbRegisterInfo.h"
20 #include "Utils/ARMBaseInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/IR/DebugLoc.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCDwarf.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/Support/Compiler.h"
43 #include <bitset>
44 #include <cassert>
45 #include <iterator>
46 #include <vector>
47 
48 using namespace llvm;
49 
51  : ARMFrameLowering(sti) {}
52 
54  const MachineFrameInfo &MFI = MF.getFrameInfo();
55  unsigned CFSize = MFI.getMaxCallFrameSize();
56  // It's not always a good idea to include the call frame as part of the
57  // stack frame. ARM (especially Thumb) has small immediate offset to
58  // address the stack frame. So a large call frame can cause poor codegen
59  // and may even makes it impossible to scavenge a register.
60  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
61  return false;
62 
63  return !MFI.hasVarSizedObjects();
64 }
65 
66 static void
69  const TargetInstrInfo &TII, const DebugLoc &dl,
70  const ThumbRegisterInfo &MRI, int NumBytes,
71  unsigned ScratchReg, unsigned MIFlags) {
72  // If it would take more than three instructions to adjust the stack pointer
73  // using tADDspi/tSUBspi, load an immediate instead.
74  if (std::abs(NumBytes) > 508 * 3) {
75  // We use a different codepath here from the normal
76  // emitThumbRegPlusImmediate so we don't have to deal with register
77  // scavenging. (Scavenging could try to use the emergency spill slot
78  // before we've actually finished setting up the stack.)
79  if (ScratchReg == ARM::NoRegister)
80  report_fatal_error("Failed to emit Thumb1 stack adjustment");
81  MachineFunction &MF = *MBB.getParent();
83  if (ST.genExecuteOnly()) {
84  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
85  .addImm(NumBytes).setMIFlags(MIFlags);
86  } else {
87  MRI.emitLoadConstPool(MBB, MBBI, dl, ScratchReg, 0, NumBytes, ARMCC::AL,
88  0, MIFlags);
89  }
90  BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
91  .addReg(ARM::SP)
92  .addReg(ScratchReg, RegState::Kill)
94  .setMIFlags(MIFlags);
95  return;
96  }
97  // FIXME: This is assuming the heuristics in emitThumbRegPlusImmediate
98  // won't change.
99  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
100  MRI, MIFlags);
101 
102 }
103 
106  const TargetInstrInfo &TII, const DebugLoc &dl,
107  const ThumbRegisterInfo &MRI, int NumBytes,
108  unsigned MIFlags = MachineInstr::NoFlags) {
109  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
110  MRI, MIFlags);
111 }
112 
113 
117  const Thumb1InstrInfo &TII =
118  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
119  const ThumbRegisterInfo *RegInfo =
120  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
121  if (!hasReservedCallFrame(MF)) {
122  // If we have alloca, convert as follows:
123  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
124  // ADJCALLSTACKUP -> add, sp, sp, amount
125  MachineInstr &Old = *I;
126  DebugLoc dl = Old.getDebugLoc();
127  unsigned Amount = TII.getFrameSize(Old);
128  if (Amount != 0) {
129  // We need to keep the stack aligned properly. To do this, we round the
130  // amount of space needed for the outgoing arguments up to the next
131  // alignment boundary.
132  Amount = alignTo(Amount, getStackAlign());
133 
134  // Replace the pseudo instruction with a new instruction...
135  unsigned Opc = Old.getOpcode();
136  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
137  emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
138  } else {
139  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
140  emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
141  }
142  }
143  }
144  return MBB.erase(I);
145 }
146 
148  MachineBasicBlock &MBB) const {
150  MachineFrameInfo &MFI = MF.getFrameInfo();
152  MachineModuleInfo &MMI = MF.getMMI();
153  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
154  const ThumbRegisterInfo *RegInfo =
155  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
156  const Thumb1InstrInfo &TII =
157  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
158 
159  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
160  unsigned NumBytes = MFI.getStackSize();
161  assert(NumBytes >= ArgRegsSaveSize &&
162  "ArgRegsSaveSize is included in NumBytes");
163  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
164 
165  // Debug location must be unknown since the first debug location is used
166  // to determine the end of the prologue.
167  DebugLoc dl;
168 
169  Register FramePtr = RegInfo->getFrameRegister(MF);
170  Register BasePtr = RegInfo->getBaseRegister();
171  int CFAOffset = 0;
172 
173  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
174  NumBytes = (NumBytes + 3) & ~3;
175  MFI.setStackSize(NumBytes);
176 
177  // Determine the sizes of each callee-save spill areas and record which frame
178  // belongs to which callee-save spill areas.
179  unsigned FRSize = 0, GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
180  int FramePtrSpillFI = 0;
181 
182  if (ArgRegsSaveSize) {
183  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
184  ARM::NoRegister, MachineInstr::FrameSetup);
185  CFAOffset += ArgRegsSaveSize;
186  unsigned CFIIndex =
187  MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
188  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
189  .addCFIIndex(CFIIndex)
191  }
192 
193  if (!AFI->hasStackFrame()) {
194  if (NumBytes - ArgRegsSaveSize != 0) {
195  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
196  -(NumBytes - ArgRegsSaveSize),
197  ARM::NoRegister, MachineInstr::FrameSetup);
198  CFAOffset += NumBytes - ArgRegsSaveSize;
199  unsigned CFIIndex = MF.addFrameInst(
200  MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
201  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
202  .addCFIIndex(CFIIndex)
204  }
205  return;
206  }
207 
208  bool HasFrameRecordArea = hasFP(MF) && ARM::hGPRRegClass.contains(FramePtr);
209 
210  for (const CalleeSavedInfo &I : CSI) {
211  Register Reg = I.getReg();
212  int FI = I.getFrameIdx();
213  if (Reg == FramePtr)
214  FramePtrSpillFI = FI;
215  switch (Reg) {
216  case ARM::R11:
217  if (HasFrameRecordArea) {
218  FRSize += 4;
219  break;
220  }
221  [[fallthrough]];
222  case ARM::R8:
223  case ARM::R9:
224  case ARM::R10:
225  if (STI.splitFramePushPop(MF)) {
226  GPRCS2Size += 4;
227  break;
228  }
229  [[fallthrough]];
230  case ARM::LR:
231  if (HasFrameRecordArea) {
232  FRSize += 4;
233  break;
234  }
235  [[fallthrough]];
236  case ARM::R4:
237  case ARM::R5:
238  case ARM::R6:
239  case ARM::R7:
240  GPRCS1Size += 4;
241  break;
242  default:
243  DPRCSSize += 8;
244  }
245  }
246 
247  MachineBasicBlock::iterator FRPush, GPRCS1Push, GPRCS2Push;
248  if (HasFrameRecordArea) {
249  // Skip Frame Record setup:
250  // push {lr}
251  // mov lr, r11
252  // push {lr}
253  std::advance(MBBI, 2);
254  FRPush = MBBI++;
255  }
256 
257  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
258  GPRCS1Push = MBBI;
259  ++MBBI;
260  }
261 
262  // Find last push instruction for GPRCS2 - spilling of high registers
263  // (r8-r11) could consist of multiple tPUSH and tMOVr instructions.
264  while (true) {
266  // Skip a run of tMOVr instructions
267  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr &&
268  MBBI->getFlag(MachineInstr::FrameSetup))
269  MBBI++;
270  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH &&
271  MBBI->getFlag(MachineInstr::FrameSetup)) {
272  GPRCS2Push = MBBI;
273  MBBI++;
274  } else {
275  // We have reached an instruction which is not a push, so the previous
276  // run of tMOVr instructions (which may have been empty) was not part of
277  // the prologue. Reset MBBI back to the last PUSH of the prologue.
278  MBBI = OldMBBI;
279  break;
280  }
281  }
282 
283  // Determine starting offsets of spill areas.
284  unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize -
285  (FRSize + GPRCS1Size + GPRCS2Size + DPRCSSize);
286  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
287  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
288  bool HasFP = hasFP(MF);
289  if (HasFP)
290  AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
291  NumBytes);
292  if (HasFrameRecordArea)
293  AFI->setFrameRecordSavedAreaSize(FRSize);
294  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
295  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
296  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
297  NumBytes = DPRCSOffset;
298 
299  int FramePtrOffsetInBlock = 0;
300  unsigned adjustedGPRCS1Size = GPRCS1Size;
301  if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
302  tryFoldSPUpdateIntoPushPop(STI, MF, &*(GPRCS1Push), NumBytes)) {
303  FramePtrOffsetInBlock = NumBytes;
304  adjustedGPRCS1Size += NumBytes;
305  NumBytes = 0;
306  }
307  CFAOffset += adjustedGPRCS1Size;
308 
309  // Adjust FP so it point to the stack slot that contains the previous FP.
310  if (HasFP) {
311  MachineBasicBlock::iterator AfterPush =
312  HasFrameRecordArea ? std::next(FRPush) : std::next(GPRCS1Push);
313  if (HasFrameRecordArea) {
314  // We have just finished pushing the previous FP into the stack,
315  // so simply capture the SP value as the new Frame Pointer.
316  BuildMI(MBB, AfterPush, dl, TII.get(ARM::tMOVr), FramePtr)
317  .addReg(ARM::SP)
319  .add(predOps(ARMCC::AL));
320  } else {
321  FramePtrOffsetInBlock +=
322  MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
323  BuildMI(MBB, AfterPush, dl, TII.get(ARM::tADDrSPi), FramePtr)
324  .addReg(ARM::SP)
325  .addImm(FramePtrOffsetInBlock / 4)
327  .add(predOps(ARMCC::AL));
328  }
329 
330  if(FramePtrOffsetInBlock) {
331  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
332  nullptr, MRI->getDwarfRegNum(FramePtr, true), (CFAOffset - FramePtrOffsetInBlock)));
333  BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
334  .addCFIIndex(CFIIndex)
336  } else {
337  unsigned CFIIndex =
339  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
340  BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
341  .addCFIIndex(CFIIndex)
343  }
344  if (NumBytes > 508)
345  // If offset is > 508 then sp cannot be adjusted in a single instruction,
346  // try restoring from fp instead.
347  AFI->setShouldRestoreSPFromFP(true);
348  }
349 
350  // Emit call frame information for the callee-saved low registers.
351  if (GPRCS1Size > 0) {
352  MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
353  if (adjustedGPRCS1Size) {
354  unsigned CFIIndex =
355  MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
356  BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
357  .addCFIIndex(CFIIndex)
359  }
360  for (const CalleeSavedInfo &I : CSI) {
361  Register Reg = I.getReg();
362  int FI = I.getFrameIdx();
363  switch (Reg) {
364  case ARM::R8:
365  case ARM::R9:
366  case ARM::R10:
367  case ARM::R11:
368  case ARM::R12:
369  if (STI.splitFramePushPop(MF))
370  break;
371  [[fallthrough]];
372  case ARM::R0:
373  case ARM::R1:
374  case ARM::R2:
375  case ARM::R3:
376  case ARM::R4:
377  case ARM::R5:
378  case ARM::R6:
379  case ARM::R7:
380  case ARM::LR:
381  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
382  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
383  BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
384  .addCFIIndex(CFIIndex)
386  break;
387  }
388  }
389  }
390 
391  // Emit call frame information for the callee-saved high registers.
392  if (GPRCS2Size > 0) {
393  MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
394  for (auto &I : CSI) {
395  Register Reg = I.getReg();
396  int FI = I.getFrameIdx();
397  switch (Reg) {
398  case ARM::R8:
399  case ARM::R9:
400  case ARM::R10:
401  case ARM::R11:
402  case ARM::R12: {
403  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
404  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
405  BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
406  .addCFIIndex(CFIIndex)
408  break;
409  }
410  default:
411  break;
412  }
413  }
414  }
415 
416  if (NumBytes) {
417  // Insert it after all the callee-save spills.
418  //
419  // For a large stack frame, we might need a scratch register to store
420  // the size of the frame. We know all callee-save registers are free
421  // at this point in the prologue, so pick one.
422  unsigned ScratchRegister = ARM::NoRegister;
423  for (auto &I : CSI) {
424  Register Reg = I.getReg();
425  if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
426  ScratchRegister = Reg;
427  break;
428  }
429  }
430  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
431  ScratchRegister, MachineInstr::FrameSetup);
432  if (!HasFP) {
433  CFAOffset += NumBytes;
434  unsigned CFIIndex = MF.addFrameInst(
435  MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
436  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
437  .addCFIIndex(CFIIndex)
439  }
440  }
441 
442  if (STI.isTargetELF() && HasFP)
444  AFI->getFramePtrSpillOffset());
445 
446  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
447  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
448  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
449 
450  if (RegInfo->hasStackRealignment(MF)) {
451  const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
452  // Emit the following sequence, using R4 as a temporary, since we cannot use
453  // SP as a source or destination register for the shifts:
454  // mov r4, sp
455  // lsrs r4, r4, #NrBitsToZero
456  // lsls r4, r4, #NrBitsToZero
457  // mov sp, r4
458  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
459  .addReg(ARM::SP, RegState::Kill)
460  .add(predOps(ARMCC::AL));
461 
462  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
463  .addDef(ARM::CPSR)
465  .addImm(NrBitsToZero)
466  .add(predOps(ARMCC::AL));
467 
468  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
469  .addDef(ARM::CPSR)
471  .addImm(NrBitsToZero)
472  .add(predOps(ARMCC::AL));
473 
474  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
476  .add(predOps(ARMCC::AL));
477 
478  AFI->setShouldRestoreSPFromFP(true);
479  }
480 
481  // If we need a base pointer, set it up here. It's whatever the value
482  // of the stack pointer is at this point. Any variable size objects
483  // will be allocated after this, so we can still use the base pointer
484  // to reference locals.
485  if (RegInfo->hasBasePointer(MF))
486  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
487  .addReg(ARM::SP)
488  .add(predOps(ARMCC::AL));
489 
490  // If the frame has variable sized objects then the epilogue must restore
491  // the sp from fp. We can assume there's an FP here since hasFP already
492  // checks for hasVarSizedObjects.
493  if (MFI.hasVarSizedObjects())
494  AFI->setShouldRestoreSPFromFP(true);
495 
496  // In some cases, virtual registers have been introduced, e.g. by uses of
497  // emitThumbRegPlusImmInReg.
499 }
500 
502  MachineBasicBlock &MBB) const {
504  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
505  MachineFrameInfo &MFI = MF.getFrameInfo();
507  const ThumbRegisterInfo *RegInfo =
508  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
509  const Thumb1InstrInfo &TII =
510  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
511 
512  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
513  int NumBytes = (int)MFI.getStackSize();
514  assert((unsigned)NumBytes >= ArgRegsSaveSize &&
515  "ArgRegsSaveSize is included in NumBytes");
516  Register FramePtr = RegInfo->getFrameRegister(MF);
517 
518  if (!AFI->hasStackFrame()) {
519  if (NumBytes - ArgRegsSaveSize != 0)
520  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
521  NumBytes - ArgRegsSaveSize, ARM::NoRegister,
523  } else {
524  // Unwind MBBI to point to first LDR / VLDRD.
525  if (MBBI != MBB.begin()) {
526  do
527  --MBBI;
528  while (MBBI != MBB.begin() && MBBI->getFlag(MachineInstr::FrameDestroy));
529  if (!MBBI->getFlag(MachineInstr::FrameDestroy))
530  ++MBBI;
531  }
532 
533  // Move SP to start of FP callee save spill area.
534  NumBytes -= (AFI->getFrameRecordSavedAreaSize() +
538  ArgRegsSaveSize);
539 
540  if (AFI->shouldRestoreSPFromFP()) {
541  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
542  // Reset SP based on frame pointer only if the stack frame extends beyond
543  // frame pointer stack slot, the target is ELF and the function has FP, or
544  // the target uses var sized objects.
545  if (NumBytes) {
546  assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
547  "No scratch register to restore SP from FP!");
549  TII, *RegInfo, MachineInstr::FrameDestroy);
550  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
551  .addReg(ARM::R4)
554  } else
555  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
556  .addReg(FramePtr)
559  } else {
560  // For a large stack frame, we might need a scratch register to store
561  // the size of the frame. We know all callee-save registers are free
562  // at this point in the epilogue, so pick one.
563  unsigned ScratchRegister = ARM::NoRegister;
564  bool HasFP = hasFP(MF);
565  for (auto &I : MFI.getCalleeSavedInfo()) {
566  Register Reg = I.getReg();
567  if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
568  ScratchRegister = Reg;
569  break;
570  }
571  }
572  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
573  &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
574  MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
575  if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
576  emitPrologueEpilogueSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes,
577  ScratchRegister, MachineInstr::FrameDestroy);
578  } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
579  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes,
580  ScratchRegister, MachineInstr::FrameDestroy);
581  }
582  }
583 
584  if (needPopSpecialFixUp(MF)) {
585  bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
586  (void)Done;
587  assert(Done && "Emission of the special fixup failed!?");
588  }
589 }
590 
592  if (!needPopSpecialFixUp(*MBB.getParent()))
593  return true;
594 
595  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
596  return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
597 }
598 
599 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
600  ARMFunctionInfo *AFI =
601  const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
602  if (AFI->getArgRegsSaveSize())
603  return true;
604 
605  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
606  for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
607  if (CSI.getReg() == ARM::LR)
608  return true;
609 
610  return false;
611 }
612 
613 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
614  const BitVector &PopFriendly,
615  const LivePhysRegs &UsedRegs, unsigned &PopReg,
616  unsigned &TmpReg, MachineRegisterInfo &MRI) {
617  PopReg = TmpReg = 0;
618  for (auto Reg : GPRsNoLRSP.set_bits()) {
619  if (UsedRegs.available(MRI, Reg)) {
620  // Remember the first pop-friendly register and exit.
621  if (PopFriendly.test(Reg)) {
622  PopReg = Reg;
623  TmpReg = 0;
624  break;
625  }
626  // Otherwise, remember that the register will be available to
627  // save a pop-friendly register.
628  TmpReg = Reg;
629  }
630  }
631 }
632 
633 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
634  bool DoIt) const {
635  MachineFunction &MF = *MBB.getParent();
637  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
638  const TargetInstrInfo &TII = *STI.getInstrInfo();
639  const ThumbRegisterInfo *RegInfo =
640  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
641 
642  // If MBBI is a return instruction, or is a tPOP followed by a return
643  // instruction in the successor BB, we may be able to directly restore
644  // LR in the PC.
645  // This is only possible with v5T ops (v4T can't change the Thumb bit via
646  // a POP PC instruction), and only if we do not need to emit any SP update.
647  // Otherwise, we need a temporary register to pop the value
648  // and copy that value into LR.
649  auto MBBI = MBB.getFirstTerminator();
650  bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
651  if (CanRestoreDirectly) {
652  if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
653  CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
654  MBBI->getOpcode() == ARM::tPOP_RET);
655  else {
656  auto MBBI_prev = MBBI;
657  MBBI_prev--;
658  assert(MBBI_prev->getOpcode() == ARM::tPOP);
659  assert(MBB.succ_size() == 1);
660  if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
661  MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
662  else
663  CanRestoreDirectly = false;
664  }
665  }
666 
667  if (CanRestoreDirectly) {
668  if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
669  return true;
670  MachineInstrBuilder MIB =
671  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
674  // Copy implicit ops and popped registers, if any.
675  for (auto MO: MBBI->operands())
676  if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
677  MIB.add(MO);
678  MIB.addReg(ARM::PC, RegState::Define);
679  // Erase the old instruction (tBX_RET or tPOP).
680  MBB.erase(MBBI);
681  return true;
682  }
683 
684  // Look for a temporary register to use.
685  // First, compute the liveness information.
687  LivePhysRegs UsedRegs(TRI);
688  UsedRegs.addLiveOuts(MBB);
689  // The semantic of pristines changed recently and now,
690  // the callee-saved registers that are touched in the function
691  // are not part of the pristines set anymore.
692  // Add those callee-saved now.
693  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
694  for (unsigned i = 0; CSRegs[i]; ++i)
695  UsedRegs.addReg(CSRegs[i]);
696 
697  DebugLoc dl = DebugLoc();
698  if (MBBI != MBB.end()) {
699  dl = MBBI->getDebugLoc();
700  auto InstUpToMBBI = MBB.end();
701  while (InstUpToMBBI != MBBI)
702  // The pre-decrement is on purpose here.
703  // We want to have the liveness right before MBBI.
704  UsedRegs.stepBackward(*--InstUpToMBBI);
705  }
706 
707  // Look for a register that can be directly use in the POP.
708  unsigned PopReg = 0;
709  // And some temporary register, just in case.
710  unsigned TemporaryReg = 0;
711  BitVector PopFriendly =
712  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
713  // R7 may be used as a frame pointer, hence marked as not generally
714  // allocatable, however there's no reason to not use it as a temporary for
715  // restoring LR.
716  if (STI.getFramePointerReg() == ARM::R7)
717  PopFriendly.set(ARM::R7);
718 
719  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
720  // Rebuild the GPRs from the high registers because they are removed
721  // form the GPR reg class for thumb1.
722  BitVector GPRsNoLRSP =
723  TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
724  GPRsNoLRSP |= PopFriendly;
725  GPRsNoLRSP.reset(ARM::LR);
726  GPRsNoLRSP.reset(ARM::SP);
727  GPRsNoLRSP.reset(ARM::PC);
728  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg,
729  MF.getRegInfo());
730 
731  // If we couldn't find a pop-friendly register, try restoring LR before
732  // popping the other callee-saved registers, so we could use one of them as a
733  // temporary.
734  bool UseLDRSP = false;
735  if (!PopReg && MBBI != MBB.begin()) {
736  auto PrevMBBI = MBBI;
737  PrevMBBI--;
738  if (PrevMBBI->getOpcode() == ARM::tPOP) {
739  UsedRegs.stepBackward(*PrevMBBI);
740  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg,
741  TemporaryReg, MF.getRegInfo());
742  if (PopReg) {
743  MBBI = PrevMBBI;
744  UseLDRSP = true;
745  }
746  }
747  }
748 
749  if (!DoIt && !PopReg && !TemporaryReg)
750  return false;
751 
752  assert((PopReg || TemporaryReg) && "Cannot get LR");
753 
754  if (UseLDRSP) {
755  assert(PopReg && "Do not know how to get LR");
756  // Load the LR via LDR tmp, [SP, #off]
757  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
758  .addReg(PopReg, RegState::Define)
759  .addReg(ARM::SP)
760  .addImm(MBBI->getNumExplicitOperands() - 2)
763  // Move from the temporary register to the LR.
764  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
765  .addReg(ARM::LR, RegState::Define)
766  .addReg(PopReg, RegState::Kill)
769  // Advance past the pop instruction.
770  MBBI++;
771  // Increment the SP.
772  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
773  ArgRegsSaveSize + 4, ARM::NoRegister,
775  return true;
776  }
777 
778  if (TemporaryReg) {
779  assert(!PopReg && "Unnecessary MOV is about to be inserted");
780  PopReg = PopFriendly.find_first();
781  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
782  .addReg(TemporaryReg, RegState::Define)
783  .addReg(PopReg, RegState::Kill)
786  }
787 
788  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
789  // We couldn't use the direct restoration above, so
790  // perform the opposite conversion: tPOP_RET to tPOP.
791  MachineInstrBuilder MIB =
792  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
795  bool Popped = false;
796  for (auto MO: MBBI->operands())
797  if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
798  MO.getReg() != ARM::PC) {
799  MIB.add(MO);
800  if (!MO.isImplicit())
801  Popped = true;
802  }
803  // Is there anything left to pop?
804  if (!Popped)
805  MBB.erase(MIB.getInstr());
806  // Erase the old instruction.
807  MBB.erase(MBBI);
808  MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
811  }
812 
813  assert(PopReg && "Do not know how to get LR");
814  BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
816  .addReg(PopReg, RegState::Define)
818 
819  emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize,
820  ARM::NoRegister, MachineInstr::FrameDestroy);
821 
822  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
823  .addReg(ARM::LR, RegState::Define)
824  .addReg(PopReg, RegState::Kill)
827 
828  if (TemporaryReg)
829  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
830  .addReg(PopReg, RegState::Define)
831  .addReg(TemporaryReg, RegState::Kill)
834 
835  return true;
836 }
837 
839  ARM::R7, ARM::LR};
840 static const SmallVector<Register> OrderedHighRegs = {ARM::R8, ARM::R9,
841  ARM::R10, ARM::R11};
843  ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
844  ARM::R5, ARM::R6, ARM::R7, ARM::LR};
845 
846 static void splitLowAndHighRegs(const std::set<Register> &Regs,
847  std::set<Register> &LowRegs,
848  std::set<Register> &HighRegs) {
849  for (Register Reg : Regs) {
850  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
851  LowRegs.insert(Reg);
852  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
853  HighRegs.insert(Reg);
854  } else {
855  llvm_unreachable("callee-saved register of unexpected class");
856  }
857  }
858 }
859 
860 template <typename It>
861 It getNextOrderedReg(It OrderedStartIt, It OrderedEndIt,
862  const std::set<Register> &RegSet) {
863  return std::find_if(OrderedStartIt, OrderedEndIt,
864  [&](Register Reg) { return RegSet.count(Reg); });
865 }
866 
869  const TargetInstrInfo &TII,
870  const std::set<Register> &RegsToSave,
871  const std::set<Register> &CopyRegs) {
872  MachineFunction &MF = *MBB.getParent();
873  const MachineRegisterInfo &MRI = MF.getRegInfo();
874  DebugLoc DL;
875 
876  std::set<Register> LowRegs, HighRegs;
877  splitLowAndHighRegs(RegsToSave, LowRegs, HighRegs);
878 
879  // Push low regs first
880  if (!LowRegs.empty()) {
881  MachineInstrBuilder MIB =
882  BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
883  for (unsigned Reg : OrderedLowRegs) {
884  if (LowRegs.count(Reg)) {
885  bool isKill = !MRI.isLiveIn(Reg);
886  if (isKill && !MRI.isReserved(Reg))
887  MBB.addLiveIn(Reg);
888 
889  MIB.addReg(Reg, getKillRegState(isKill));
890  }
891  }
893  }
894 
895  // Now push the high registers
896  // There are no store instructions that can access high registers directly,
897  // so we have to move them to low registers, and push them.
898  // This might take multiple pushes, as it is possible for there to
899  // be fewer low registers available than high registers which need saving.
900 
901  // Find the first register to save.
902  // Registers must be processed in reverse order so that in case we need to use
903  // multiple PUSH instructions, the order of the registers on the stack still
904  // matches the unwind info. They need to be swicthed back to ascending order
905  // before adding to the PUSH instruction.
906  auto HiRegToSave = getNextOrderedReg(OrderedHighRegs.rbegin(),
907  OrderedHighRegs.rend(),
908  HighRegs);
909 
910  while (HiRegToSave != OrderedHighRegs.rend()) {
911  // Find the first low register to use.
912  auto CopyRegIt = getNextOrderedReg(OrderedCopyRegs.rbegin(),
913  OrderedCopyRegs.rend(),
914  CopyRegs);
915 
916  // Create the PUSH, but don't insert it yet (the MOVs need to come first).
917  MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH))
920 
921  SmallVector<unsigned, 4> RegsToPush;
922  while (HiRegToSave != OrderedHighRegs.rend() &&
923  CopyRegIt != OrderedCopyRegs.rend()) {
924  if (HighRegs.count(*HiRegToSave)) {
925  bool isKill = !MRI.isLiveIn(*HiRegToSave);
926  if (isKill && !MRI.isReserved(*HiRegToSave))
927  MBB.addLiveIn(*HiRegToSave);
928 
929  // Emit a MOV from the high reg to the low reg.
930  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
931  .addReg(*CopyRegIt, RegState::Define)
932  .addReg(*HiRegToSave, getKillRegState(isKill))
935 
936  // Record the register that must be added to the PUSH.
937  RegsToPush.push_back(*CopyRegIt);
938 
939  CopyRegIt = getNextOrderedReg(std::next(CopyRegIt),
940  OrderedCopyRegs.rend(),
941  CopyRegs);
942  HiRegToSave = getNextOrderedReg(std::next(HiRegToSave),
943  OrderedHighRegs.rend(),
944  HighRegs);
945  }
946  }
947 
948  // Add the low registers to the PUSH, in ascending order.
949  for (unsigned Reg : llvm::reverse(RegsToPush))
950  PushMIB.addReg(Reg, RegState::Kill);
951 
952  // Insert the PUSH instruction after the MOVs.
953  MBB.insert(MI, PushMIB);
954  }
955 }
956 
959  const TargetInstrInfo &TII,
960  const std::set<Register> &RegsToRestore,
961  const std::set<Register> &AvailableCopyRegs,
962  bool IsVarArg, bool HasV5Ops) {
963  if (RegsToRestore.empty())
964  return;
965 
966  MachineFunction &MF = *MBB.getParent();
968  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
969 
970  std::set<Register> LowRegs, HighRegs;
971  splitLowAndHighRegs(RegsToRestore, LowRegs, HighRegs);
972 
973  // Pop the high registers first
974  // There are no store instructions that can access high registers directly,
975  // so we have to pop into low registers and them move to the high registers.
976  // This might take multiple pops, as it is possible for there to
977  // be fewer low registers available than high registers which need restoring.
978 
979  // Find the first register to restore.
980  auto HiRegToRestore = getNextOrderedReg(OrderedHighRegs.begin(),
981  OrderedHighRegs.end(),
982  HighRegs);
983 
984  std::set<Register> CopyRegs = AvailableCopyRegs;
985  Register LowScratchReg;
986  if (!HighRegs.empty() && CopyRegs.empty()) {
987  // No copy regs are available to pop high regs. Let's make use of a return
988  // register and the scratch register (IP/R12) to copy things around.
989  LowScratchReg = ARM::R0;
990  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
991  .addReg(ARM::R12, RegState::Define)
992  .addReg(LowScratchReg, RegState::Kill)
995  CopyRegs.insert(LowScratchReg);
996  }
997 
998  while (HiRegToRestore != OrderedHighRegs.end()) {
999  assert(!CopyRegs.empty());
1000  // Find the first low register to use.
1001  auto CopyReg = getNextOrderedReg(OrderedCopyRegs.begin(),
1002  OrderedCopyRegs.end(),
1003  CopyRegs);
1004 
1005  // Create the POP instruction.
1006  MachineInstrBuilder PopMIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPOP))
1007  .add(predOps(ARMCC::AL))
1009 
1010  while (HiRegToRestore != OrderedHighRegs.end() &&
1011  CopyReg != OrderedCopyRegs.end()) {
1012  // Add the low register to the POP.
1013  PopMIB.addReg(*CopyReg, RegState::Define);
1014 
1015  // Create the MOV from low to high register.
1016  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
1017  .addReg(*HiRegToRestore, RegState::Define)
1018  .addReg(*CopyReg, RegState::Kill)
1019  .add(predOps(ARMCC::AL))
1021 
1022  CopyReg = getNextOrderedReg(std::next(CopyReg),
1023  OrderedCopyRegs.end(),
1024  CopyRegs);
1025  HiRegToRestore = getNextOrderedReg(std::next(HiRegToRestore),
1026  OrderedHighRegs.end(),
1027  HighRegs);
1028  }
1029  }
1030 
1031  // Restore low register used as scratch if necessary
1032  if (LowScratchReg.isValid()) {
1033  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
1034  .addReg(LowScratchReg, RegState::Define)
1035  .addReg(ARM::R12, RegState::Kill)
1036  .add(predOps(ARMCC::AL))
1038  }
1039 
1040  // Now pop the low registers
1041  if (!LowRegs.empty()) {
1042  MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP))
1043  .add(predOps(ARMCC::AL))
1045 
1046  bool NeedsPop = false;
1047  for (Register Reg : OrderedLowRegs) {
1048  if (!LowRegs.count(Reg))
1049  continue;
1050 
1051  if (Reg == ARM::LR) {
1052  if (!MBB.succ_empty() ||
1053  MI->getOpcode() == ARM::TCRETURNdi ||
1054  MI->getOpcode() == ARM::TCRETURNri)
1055  // LR may only be popped into PC, as part of return sequence.
1056  // If this isn't the return sequence, we'll need emitPopSpecialFixUp
1057  // to restore LR the hard way.
1058  // FIXME: if we don't pass any stack arguments it would be actually
1059  // advantageous *and* correct to do the conversion to an ordinary call
1060  // instruction here.
1061  continue;
1062  // Special epilogue for vararg functions. See emitEpilogue
1063  if (IsVarArg)
1064  continue;
1065  // ARMv4T requires BX, see emitEpilogue
1066  if (!HasV5Ops)
1067  continue;
1068 
1069  // CMSE entry functions must return via BXNS, see emitEpilogue.
1070  if (AFI->isCmseNSEntryFunction())
1071  continue;
1072 
1073  // Pop LR into PC.
1074  Reg = ARM::PC;
1075  (*MIB).setDesc(TII.get(ARM::tPOP_RET));
1076  if (MI != MBB.end())
1077  MIB.copyImplicitOps(*MI);
1078  MI = MBB.erase(MI);
1079  }
1080  MIB.addReg(Reg, getDefRegState(true));
1081  NeedsPop = true;
1082  }
1083 
1084  // It's illegal to emit pop instruction without operands.
1085  if (NeedsPop)
1086  MBB.insert(MI, &*MIB);
1087  else
1088  MF.deleteMachineInstr(MIB);
1089  }
1090 }
1091 
1094  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
1095  if (CSI.empty())
1096  return false;
1097 
1098  const TargetInstrInfo &TII = *STI.getInstrInfo();
1099  MachineFunction &MF = *MBB.getParent();
1100  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1101  MF.getSubtarget().getRegisterInfo());
1102  Register FPReg = RegInfo->getFrameRegister(MF);
1103 
1104  // In case FP is a high reg, we need a separate push sequence to generate
1105  // a correct Frame Record
1106  bool NeedsFrameRecordPush = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg);
1107 
1108  std::set<Register> FrameRecord;
1109  std::set<Register> SpilledGPRs;
1110  for (const CalleeSavedInfo &I : CSI) {
1111  Register Reg = I.getReg();
1112  if (NeedsFrameRecordPush && (Reg == FPReg || Reg == ARM::LR))
1113  FrameRecord.insert(Reg);
1114  else
1115  SpilledGPRs.insert(Reg);
1116  }
1117 
1118  pushRegsToStack(MBB, MI, TII, FrameRecord, {ARM::LR});
1119 
1120  // Determine intermediate registers which can be used for pushing high regs:
1121  // - Spilled low regs
1122  // - Unused argument registers
1123  std::set<Register> CopyRegs;
1124  for (Register Reg : SpilledGPRs)
1125  if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
1126  !MF.getRegInfo().isLiveIn(Reg) && !(hasFP(MF) && Reg == FPReg))
1127  CopyRegs.insert(Reg);
1128  for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
1129  if (!MF.getRegInfo().isLiveIn(ArgReg))
1130  CopyRegs.insert(ArgReg);
1131 
1132  pushRegsToStack(MBB, MI, TII, SpilledGPRs, CopyRegs);
1133 
1134  return true;
1135 }
1136 
1140  if (CSI.empty())
1141  return false;
1142 
1143  MachineFunction &MF = *MBB.getParent();
1145  const TargetInstrInfo &TII = *STI.getInstrInfo();
1146  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1147  MF.getSubtarget().getRegisterInfo());
1148  bool IsVarArg = AFI->getArgRegsSaveSize() > 0;
1149  Register FPReg = RegInfo->getFrameRegister(MF);
1150 
1151  // In case FP is a high reg, we need a separate pop sequence to generate
1152  // a correct Frame Record
1153  bool NeedsFrameRecordPop = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg);
1154 
1155  std::set<Register> FrameRecord;
1156  std::set<Register> SpilledGPRs;
1157  for (CalleeSavedInfo &I : CSI) {
1158  Register Reg = I.getReg();
1159  if (NeedsFrameRecordPop && (Reg == FPReg || Reg == ARM::LR))
1160  FrameRecord.insert(Reg);
1161  else
1162  SpilledGPRs.insert(Reg);
1163 
1164  if (Reg == ARM::LR)
1165  I.setRestored(false);
1166  }
1167 
1168  // Determine intermidiate registers which can be used for popping high regs:
1169  // - Spilled low regs
1170  // - Unused return registers
1171  std::set<Register> CopyRegs;
1172  std::set<Register> UnusedReturnRegs;
1173  for (Register Reg : SpilledGPRs)
1174  if ((ARM::tGPRRegClass.contains(Reg)) && !(hasFP(MF) && Reg == FPReg))
1175  CopyRegs.insert(Reg);
1177  if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
1178  UnusedReturnRegs.insert(ARM::R0);
1179  UnusedReturnRegs.insert(ARM::R1);
1180  UnusedReturnRegs.insert(ARM::R2);
1181  UnusedReturnRegs.insert(ARM::R3);
1182  for (auto Op : Terminator->implicit_operands()) {
1183  if (Op.isReg())
1184  UnusedReturnRegs.erase(Op.getReg());
1185  }
1186  }
1187  CopyRegs.insert(UnusedReturnRegs.begin(), UnusedReturnRegs.end());
1188 
1189  // First pop regular spilled regs.
1190  popRegsFromStack(MBB, MI, TII, SpilledGPRs, CopyRegs, IsVarArg,
1191  STI.hasV5TOps());
1192 
1193  // LR may only be popped into pc, as part of a return sequence.
1194  // Check that no other pop instructions are inserted after that.
1195  assert((!SpilledGPRs.count(ARM::LR) || FrameRecord.empty()) &&
1196  "Can't insert pop after return sequence");
1197 
1198  // Now pop Frame Record regs.
1199  // Only unused return registers can be used as copy regs at this point.
1200  popRegsFromStack(MBB, MI, TII, FrameRecord, UnusedReturnRegs, IsVarArg,
1201  STI.hasV5TOps());
1202 
1203  return true;
1204 }
llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: Thumb1FrameLowering.cpp:1137
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:385
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::ARMFunctionInfo::getFrameRecordSavedAreaSize
unsigned getFrameRecordSavedAreaSize() const
Definition: ARMMachineFunctionInfo.h:207
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:321
llvm::ARMFunctionInfo::setGPRCalleeSavedArea2Size
void setGPRCalleeSavedArea2Size(unsigned s)
Definition: ARMMachineFunctionInfo.h:216
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::ARMFunctionInfo::shouldRestoreSPFromFP
bool shouldRestoreSPFromFP() const
Definition: ARMMachineFunctionInfo.h:186
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::ARMFunctionInfo::setGPRCalleeSavedArea1Size
void setGPRCalleeSavedArea1Size(unsigned s)
Definition: ARMMachineFunctionInfo.h:215
llvm::Thumb1FrameLowering::Thumb1FrameLowering
Thumb1FrameLowering(const ARMSubtarget &sti)
Definition: Thumb1FrameLowering.cpp:50
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:256
llvm::ARMFunctionInfo::getGPRCalleeSavedArea1Size
unsigned getGPRCalleeSavedArea1Size() const
Definition: ARMMachineFunctionInfo.h:208
ARMMachineFunctionInfo.h
emitPrologueEpilogueSPUpdate
static void emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned ScratchReg, unsigned MIFlags)
Definition: Thumb1FrameLowering.cpp:67
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:133
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MachineFrameInfo::getOffsetAdjustment
int getOffsetAdjustment() const
Return the correction for frame offsets.
Definition: MachineFrameInfo.h:594
llvm::ARMFunctionInfo::getGPRCalleeSavedArea2Size
unsigned getGPRCalleeSavedArea2Size() const
Definition: ARMMachineFunctionInfo.h:209
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::Thumb1FrameLowering::canUseAsEpilogue
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: Thumb1FrameLowering.cpp:591
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:588
TargetInstrInfo.h
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:262
Thumb1InstrInfo.h
Thumb1FrameLowering.h
STLExtras.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:654
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:547
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::ARMBaseRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: ARMBaseRegisterInfo.h:209
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1324
llvm::ARMFunctionInfo::getDPRCalleeSavedAreaSize
unsigned getDPRCalleeSavedAreaSize() const
Definition: ARMMachineFunctionInfo.h:211
OrderedHighRegs
static const SmallVector< Register > OrderedHighRegs
Definition: Thumb1FrameLowering.cpp:840
llvm::ARMFunctionInfo::isCmseNSEntryFunction
bool isCmseNSEntryFunction() const
Definition: ARMMachineFunctionInfo.h:171
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
findTemporariesForLR
static void findTemporariesForLR(const BitVector &GPRsNoLRSP, const BitVector &PopFriendly, const LivePhysRegs &UsedRegs, unsigned &PopReg, unsigned &TmpReg, MachineRegisterInfo &MRI)
Definition: Thumb1FrameLowering.cpp:613
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:441
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:540
R2
#define R2(n)
llvm::Thumb1FrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: Thumb1FrameLowering.cpp:147
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:670
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::ARMFunctionInfo::setShouldRestoreSPFromFP
void setShouldRestoreSPFromFP(bool s)
Definition: ARMMachineFunctionInfo.h:187
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:28
pushRegsToStack
static void pushRegsToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const TargetInstrInfo &TII, const std::set< Register > &RegsToSave, const std::set< Register > &CopyRegs)
Definition: Thumb1FrameLowering.cpp:867
llvm::Thumb1FrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: Thumb1FrameLowering.cpp:501
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:758
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::ARMFunctionInfo::setFrameRecordSavedAreaSize
void setFrameRecordSavedAreaSize(unsigned s)
Definition: ARMMachineFunctionInfo.h:214
llvm::ARMBaseRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:485
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:930
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaSize
void setDPRCalleeSavedAreaSize(unsigned s)
Definition: ARMMachineFunctionInfo.h:218
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:209
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
MCContext.h
llvm::MachineFunction::deleteMachineInstr
void deleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
Definition: MachineFunction.cpp:418
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:751
emitCallSPUpdate
static void emitCallSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags)
Definition: Thumb1FrameLowering.cpp:104
FramePtr
static const unsigned FramePtr
Definition: XCoreFrameLowering.cpp:34
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::ARMFunctionInfo::getFramePtrSpillOffset
unsigned getFramePtrSpillOffset() const
Definition: ARMMachineFunctionInfo.h:192
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
ARMBaseInfo.h
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:74
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585
DebugLoc.h
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
ThumbRegisterInfo.h
llvm::BitVector
Definition: BitVector.h:75
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:540
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::ARMFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: ARMFrameLowering.cpp:202
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:611
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:660
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
ARMBaseRegisterInfo.h
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:770
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::BitVector::any
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:163
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::LivePhysRegs::available
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
Definition: LivePhysRegs.cpp:141
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:430
MCRegisterInfo.h
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:372
splitLowAndHighRegs
static void splitLowAndHighRegs(const std::set< Register > &Regs, std::set< Register > &LowRegs, std::set< Register > &HighRegs)
Definition: Thumb1FrameLowering.cpp:846
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:373
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:676
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:265
ARMBaseInstrInfo.h
llvm::tryFoldSPUpdateIntoPushPop
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
Definition: ARMBaseInstrInfo.cpp:2520
popRegsFromStack
static void popRegsFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MI, const TargetInstrInfo &TII, const std::set< Register > &RegsToRestore, const std::set< Register > &AvailableCopyRegs, bool IsVarArg, bool HasV5Ops)
Definition: Thumb1FrameLowering.cpp:957
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:533
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
OrderedLowRegs
static const SmallVector< Register > OrderedLowRegs
Definition: Thumb1FrameLowering.cpp:838
R6
#define R6(n)
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ARMFunctionInfo::setFramePtrSpillOffset
void setFramePtrSpillOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:193
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:388
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:240
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:274
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
Compiler.h
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMFunctionInfo::setGPRCalleeSavedArea2Offset
void setGPRCalleeSavedArea2Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:203
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:201
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::ARMFunctionInfo::setGPRCalleeSavedArea1Offset
void setGPRCalleeSavedArea1Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:202
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:601
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFunction::addFrameInst
unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:408
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1761
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:127
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:438
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1337
MachineFrameInfo.h
llvm::Thumb1InstrInfo
Definition: Thumb1InstrInfo.h:22
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaOffset
void setDPRCalleeSavedAreaOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:204
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:288
llvm::Thumb1FrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: Thumb1FrameLowering.cpp:53
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:385
OrderedCopyRegs
static const SmallVector< Register > OrderedCopyRegs
Definition: Thumb1FrameLowering.cpp:842
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
SmallVector.h
llvm::ARMFrameLowering::STI
const ARMSubtarget & STI
Definition: ARMFrameLowering.h:23
llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: Thumb1FrameLowering.cpp:115
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:309
MachineInstrBuilder.h
llvm::ARMFunctionInfo::hasStackFrame
bool hasStackFrame() const
Definition: ARMMachineFunctionInfo.h:183
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::Register::isValid
bool isValid() const
Definition: Register.h:126
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:293
llvm::ThumbRegisterInfo
Definition: ThumbRegisterInfo.h:25
llvm::emitThumbRegPlusImmediate
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Definition: ThumbRegisterInfo.cpp:185
llvm::ARMFunctionInfo::getArgRegsSaveSize
unsigned getArgRegsSaveSize() const
Definition: ARMMachineFunctionInfo.h:177
llvm::reverse
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:485
MachineOperand.h
llvm::ARMBaseRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:416
llvm::isARMLowRegister
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
llvm::MachineFrameInfo::setOffsetAdjustment
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
Definition: MachineFrameInfo.h:597
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:571
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:541
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::Thumb1FrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: Thumb1FrameLowering.cpp:1092
MachineFunction.h
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1297
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:157
getNextOrderedReg
It getNextOrderedReg(It OrderedStartIt, It OrderedEndIt, const std::set< Register > &RegSet)
Definition: Thumb1FrameLowering.cpp:861
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:311
LivePhysRegs.h