LLVM 17.0.0git
Namespaces | Macros | Enumerations | Functions | Variables
RISCVInstrInfo.cpp File Reference
#include "RISCVInstrInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "RISCVGenCompressInstEmitter.inc"
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenSearchableTables.inc"
Include dependency graph for RISCVInstrInfo.cpp:

Go to the source code of this file.

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::RISCVVPseudosTable
 

Macros

#define GEN_CHECK_COMPRESS_INSTR
 
#define GET_INSTRINFO_CTOR_DTOR
 
#define GET_INSTRINFO_NAMED_OPS
 
#define GET_RISCVVPseudosTable_IMPL
 
#define CASE_OPERAND_UIMM(NUM)
 
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)    RISCV::PseudoV##OP##_##TYPE##_##LMUL
 
#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)
 
#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)
 
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
 
#define CASE_VFMA_OPCODE_LMULS(OP, TYPE)
 
#define CASE_VFMA_SPLATS(OP)
 
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
 
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)    RISCV::PseudoV##OP##_##LMUL##_TIED
 
#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
 
#define CASE_WIDEOP_OPCODE_LMULS(OP)
 
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
 
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
 
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)
 

Enumerations

enum  MachineOutlinerConstructionID { MachineOutlinerDefault }
 

Functions

static bool forwardCopyWillClobberTuple (unsigned DstReg, unsigned SrcReg, unsigned NumRegs)
 
static bool isConvertibleToVMV_V_V (const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVII::VLMUL LMul)
 
static RISCVCC::CondCode getCondFromBranchOpc (unsigned Opc)
 
static void parseCondBranch (MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
 
unsigned getPredicatedOpcode (unsigned Opcode)
 
static MachineInstr * canFoldAsPredicatedOp (Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
 Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.
 
static bool isFADD (unsigned Opc)
 
static bool isFSUB (unsigned Opc)
 
static bool isFMUL (unsigned Opc)
 
static bool canCombineFPFusedMultiply (const MachineInstr &Root, const MachineOperand &MO, bool DoRegPressureReduce)
 
static bool getFPFusedMultiplyPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce)
 
static bool getFPPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce)
 
static unsigned getFPFusedMultiplyOpcode (unsigned RootOpc, MachineCombinerPattern Pattern)
 
static unsigned getAddendOperandIdx (MachineCombinerPattern Pattern)
 
static void combineFPFusedMultiply (MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs)
 
static bool isRVVWholeLoadStore (unsigned Opcode)
 

Variables

static cl::opt< bool > PreferWholeRegisterMove ("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))
 

Macro Definition Documentation

◆ CASE_OPERAND_UIMM

#define CASE_OPERAND_UIMM (   NUM)
Value:
case RISCVOp::OPERAND_UIMM##NUM: \
Ok = isUInt<NUM>(Imm); \
break;

◆ CASE_VFMA_CHANGE_OPCODE_COMMON

#define CASE_VFMA_CHANGE_OPCODE_COMMON (   OLDOP,
  NEWOP,
  TYPE,
  LMUL 
)
Value:
case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
break;
_
#define _
Definition: HexagonMCCodeEmitter.cpp:47

Definition at line 2202 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS

#define CASE_VFMA_CHANGE_OPCODE_LMULS (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
CASE_VFMA_CHANGE_OPCODE_COMMON
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
Definition: RISCVInstrInfo.cpp:2202

Definition at line 2221 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_M1

#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1 (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
llvm::M1
unsigned M1(unsigned Val)
Definition: VE.h:468

Definition at line 2207 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2 (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)

Definition at line 2213 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)

Definition at line 2217 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_SPLATS

#define CASE_VFMA_CHANGE_OPCODE_SPLATS (   OLDOP,
  NEWOP 
)
Value:
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VF16) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VF32) \
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VF64)
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
Definition: RISCVInstrInfo.cpp:2217

Definition at line 2225 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_COMMON

#define CASE_VFMA_OPCODE_COMMON (   OP,
  TYPE,
  LMUL 
)     RISCV::PseudoV##OP##_##TYPE##_##LMUL

Definition at line 2058 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS

#define CASE_VFMA_OPCODE_LMULS (   OP,
  TYPE 
)
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8): \
case CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
CASE_VFMA_OPCODE_COMMON
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)
Definition: RISCVInstrInfo.cpp:2058
CASE_VFMA_OPCODE_LMULS_MF4
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
Definition: RISCVInstrInfo.cpp:2071
OP
#define OP(n)
Definition: regex2.h:73

Definition at line 2075 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_M1

#define CASE_VFMA_OPCODE_LMULS_M1 (   OP,
  TYPE 
)
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)

Definition at line 2061 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF2

#define CASE_VFMA_OPCODE_LMULS_MF2 (   OP,
  TYPE 
)
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2): \
case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)
CASE_VFMA_OPCODE_LMULS_M1
#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)
Definition: RISCVInstrInfo.cpp:2061

Definition at line 2067 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF4

#define CASE_VFMA_OPCODE_LMULS_MF4 (   OP,
  TYPE 
)
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4): \
case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)
CASE_VFMA_OPCODE_LMULS_MF2
#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)
Definition: RISCVInstrInfo.cpp:2067

Definition at line 2071 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_SPLATS

#define CASE_VFMA_SPLATS (   OP)
Value:
CASE_VFMA_OPCODE_LMULS_MF4(OP, VF16): \
case CASE_VFMA_OPCODE_LMULS_MF2(OP, VF32): \
case CASE_VFMA_OPCODE_LMULS_M1(OP, VF64)

Definition at line 2079 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_WIDEOP_CHANGE_OPCODE_COMMON (   OP,
  LMUL 
)
Value:
case RISCV::PseudoV##OP##_##LMUL##_TIED: \
NewOpc = RISCV::PseudoV##OP##_##LMUL; \
break;

Definition at line 2359 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS (   OP)
Value:
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
CASE_WIDEOP_CHANGE_OPCODE_COMMON
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
Definition: RISCVInstrInfo.cpp:2359

Definition at line 2371 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4 (   OP)
Value:
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)

Definition at line 2364 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_COMMON

#define CASE_WIDEOP_OPCODE_COMMON (   OP,
  LMUL 
)     RISCV::PseudoV##OP##_##LMUL##_TIED

Definition at line 2344 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_LMULS

#define CASE_WIDEOP_OPCODE_LMULS (   OP)
Value:
CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \
case CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
CASE_WIDEOP_OPCODE_COMMON
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)
Definition: RISCVInstrInfo.cpp:2344
CASE_WIDEOP_OPCODE_LMULS_MF4
#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
Definition: RISCVInstrInfo.cpp:2347

Definition at line 2354 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_LMULS_MF4

#define CASE_WIDEOP_OPCODE_LMULS_MF4 (   OP)
Value:
CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \
case CASE_WIDEOP_OPCODE_COMMON(OP, MF2): \
case CASE_WIDEOP_OPCODE_COMMON(OP, M1): \
case CASE_WIDEOP_OPCODE_COMMON(OP, M2): \
case CASE_WIDEOP_OPCODE_COMMON(OP, M4)

Definition at line 2347 of file RISCVInstrInfo.cpp.

◆ GEN_CHECK_COMPRESS_INSTR

#define GEN_CHECK_COMPRESS_INSTR

Definition at line 36 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 39 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 40 of file RISCVInstrInfo.cpp.

◆ GET_RISCVVPseudosTable_IMPL

#define GET_RISCVVPseudosTable_IMPL

Definition at line 51 of file RISCVInstrInfo.cpp.

Enumeration Type Documentation

◆ MachineOutlinerConstructionID

enum MachineOutlinerConstructionID
Enumerator
MachineOutlinerDefault 

Definition at line 1859 of file RISCVInstrInfo.cpp.

Function Documentation

◆ canCombineFPFusedMultiply()

static bool canCombineFPFusedMultiply ( const MachineInstr &  Root,
const MachineOperand &  MO,
bool  DoRegPressureReduce 
)
static

Definition at line 1431 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCV::hasEqualFRM(), isFMUL(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MI, and MRI.

Referenced by getFPFusedMultiplyPatterns().

◆ canFoldAsPredicatedOp()

static MachineInstr * canFoldAsPredicatedOp ( Register  Reg,
const MachineRegisterInfo &  MRI,
const TargetInstrInfo *  TII 
)
static

Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.

Definition at line 1068 of file RISCVInstrInfo.cpp.

References getPredicatedOpcode(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isCPI(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isJTI(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), MI, and MRI.

Referenced by llvm::RISCVInstrInfo::optimizeSelect().

◆ combineFPFusedMultiply()

static void combineFPFusedMultiply ( MachineInstr &  Root,
MachineInstr &  Prev,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs 
)
static

Definition at line 1535 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), getAddendOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), getFPFusedMultiplyOpcode(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::DILocation::getMergedLocation(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

Referenced by llvm::RISCVInstrInfo::genAlternativeCodeSequence().

◆ forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple ( unsigned  DstReg,
unsigned  SrcReg,
unsigned  NumRegs 
)
static

Definition at line 120 of file RISCVInstrInfo.cpp.

◆ getAddendOperandIdx()

static unsigned getAddendOperandIdx ( MachineCombinerPattern  Pattern)
static

Definition at line 1522 of file RISCVInstrInfo.cpp.

References llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

◆ getCondFromBranchOpc()

static RISCVCC::CondCode getCondFromBranchOpc ( unsigned  Opc)
static

Definition at line 732 of file RISCVInstrInfo.cpp.

References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_INVALID, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, and llvm::RISCVCC::COND_NE.

◆ getFPFusedMultiplyOpcode()

static unsigned getFPFusedMultiplyOpcode ( unsigned  RootOpc,
MachineCombinerPattern  Pattern 
)
static

Definition at line 1499 of file RISCVInstrInfo.cpp.

References llvm::FMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

◆ getFPFusedMultiplyPatterns()

static bool getFPFusedMultiplyPatterns ( MachineInstr &  Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns,
bool  DoRegPressureReduce 
)
static

Definition at line 1459 of file RISCVInstrInfo.cpp.

References canCombineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isFADD(), isFSUB(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by getFPPatterns().

◆ getFPPatterns()

static bool getFPPatterns ( MachineInstr &  Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns,
bool  DoRegPressureReduce 
)
static

Definition at line 1482 of file RISCVInstrInfo.cpp.

References getFPFusedMultiplyPatterns().

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

◆ getPredicatedOpcode()

unsigned getPredicatedOpcode ( unsigned  Opcode)

Definition at line 1051 of file RISCVInstrInfo.cpp.

Referenced by canFoldAsPredicatedOp(), and llvm::RISCVInstrInfo::optimizeSelect().

◆ isConvertibleToVMV_V_V()

static bool isConvertibleToVMV_V_V ( const RISCVSubtarget &  STI,
const MachineBasicBlock &  MBB,
MachineBasicBlock::const_iterator  MBBI,
MachineBasicBlock::const_iterator &  DefMBBI,
RISCVII::VLMUL  LMul 
)
static

Definition at line 125 of file RISCVInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::RISCVVType::getSEW(), llvm::RISCVVType::getVLMUL(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVLOp(), llvm::RISCVII::isRVVWideningReduction(), llvm::RISCVVType::isTailAgnostic(), MBB, MBBI, PreferWholeRegisterMove, TRI, and TSFlags.

Referenced by llvm::RISCVInstrInfo::copyPhysReg().

◆ isFADD()

static bool isFADD ( unsigned  Opc)
static

Definition at line 1299 of file RISCVInstrInfo.cpp.

Referenced by getFPFusedMultiplyPatterns(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

◆ isFMUL()

static bool isFMUL ( unsigned  Opc)
static

Definition at line 1321 of file RISCVInstrInfo.cpp.

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

◆ isFSUB()

static bool isFSUB ( unsigned  Opc)
static

Definition at line 1310 of file RISCVInstrInfo.cpp.

Referenced by getFPFusedMultiplyPatterns().

◆ isRVVWholeLoadStore()

static bool isRVVWholeLoadStore ( unsigned  Opcode)
static

Definition at line 2778 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCV::isRVVSpill().

◆ parseCondBranch()

static void parseCondBranch ( MachineInstr &  LastInst,
MachineBasicBlock *&  Target,
SmallVectorImpl< MachineOperand > &  Cond 
)
static

Definition at line 754 of file RISCVInstrInfo.cpp.

References assert(), CC, Cond, llvm::MachineOperand::CreateImm(), getCondFromBranchOpc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MCInstrDesc::isConditionalBranch().

Variable Documentation

◆ PreferWholeRegisterMove

cl::opt< bool > PreferWholeRegisterMove("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers.")) ( "riscv-prefer-whole-register-move"  ,
cl::init(false)  ,
cl::Hidden  ,
cl::desc("Prefer whole register move for vector registers.")   
)
static

Referenced by isConvertibleToVMV_V_V().

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