doxygen/SystemZAsmPrinter_8cpp_source.html

//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

//

// Streams SystemZ assembly language and associated data, in the form of

// MCInsts and MCExprs respectively.

//

//===----------------------------------------------------------------------===//


#include "SystemZAsmPrinter.h"

#include "MCTargetDesc/SystemZInstPrinter.h"

#include "MCTargetDesc/SystemZMCExpr.h"

#include "SystemZConstantPoolValue.h"

#include "SystemZMCInstLower.h"

#include "TargetInfo/SystemZTargetInfo.h"

#include "llvm/ADT/StringExtras.h"

#include "llvm/BinaryFormat/ELF.h"

#include "llvm/CodeGen/MachineModuleInfoImpls.h"

#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"

#include "llvm/IR/Mangler.h"

#include "llvm/MC/MCExpr.h"

#include "llvm/MC/MCInstBuilder.h"

#include "llvm/MC/MCSectionELF.h"

#include "llvm/MC/MCStreamer.h"

#include "llvm/MC/TargetRegistry.h"

#include "llvm/Support/ConvertEBCDIC.h"


using namespace llvm;


// Return an RI instruction like MI with opcode Opcode, but with the

// GR64 register operands turned into GR32s.

static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {

  if (MI->isCompare())

    return MCInstBuilder(Opcode)

      .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))

      .addImm(MI->getOperand(1).getImm());

  else

    return MCInstBuilder(Opcode)

      .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))

      .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))

      .addImm(MI->getOperand(2).getImm());

}


// Return an RI instruction like MI with opcode Opcode, but with the

// GR64 register operands turned into GRH32s.

static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {

  if (MI->isCompare())

    return MCInstBuilder(Opcode)

      .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))

      .addImm(MI->getOperand(1).getImm());

  else

    return MCInstBuilder(Opcode)

      .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))

      .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))

      .addImm(MI->getOperand(2).getImm());

}


// Return an RI instruction like MI with opcode Opcode, but with the

// R2 register turned into a GR64.

static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {

  return MCInstBuilder(Opcode)

    .addReg(MI->getOperand(0).getReg())

    .addReg(MI->getOperand(1).getReg())

    .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))

    .addImm(MI->getOperand(3).getImm())

    .addImm(MI->getOperand(4).getImm())

    .addImm(MI->getOperand(5).getImm());

}


static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) {

  StringRef Name = "__tls_get_offset";

  return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),

                                 MCSymbolRefExpr::VK_PLT,

                                 Context);

}


static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {

  StringRef Name = "_GLOBAL_OFFSET_TABLE_";

  return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),

                                 MCSymbolRefExpr::VK_None,

                                 Context);

}


// MI is an instruction that accepts an optional alignment hint,

// and which was already lowered to LoweredMI.  If the alignment

// of the original memory operand is known, update LoweredMI to

// an instruction with the corresponding hint set.

static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,

                               unsigned Opcode) {

  if (MI->memoperands_empty())

    return;


  Align Alignment = Align(16);

  for (MachineInstr::mmo_iterator MMOI = MI->memoperands_begin(),

         EE = MI->memoperands_end(); MMOI != EE; ++MMOI)

    if ((*MMOI)->getAlign() < Alignment)

      Alignment = (*MMOI)->getAlign();


  unsigned AlignmentHint = 0;

  if (Alignment >= Align(16))

    AlignmentHint = 4;

  else if (Alignment >= Align(8))

    AlignmentHint = 3;

  if (AlignmentHint == 0)

    return;


  LoweredMI.setOpcode(Opcode);

  LoweredMI.addOperand(MCOperand::createImm(AlignmentHint));

}


// MI loads the high part of a vector from memory.  Return an instruction

// that uses replicating vector load Opcode to do the same thing.

static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {

  return MCInstBuilder(Opcode)

    .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))

    .addReg(MI->getOperand(1).getReg())

    .addImm(MI->getOperand(2).getImm())

    .addReg(MI->getOperand(3).getReg());

}


// MI stores the high part of a vector to memory.  Return an instruction

// that uses elemental vector store Opcode to do the same thing.

static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {

  return MCInstBuilder(Opcode)

    .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))

    .addReg(MI->getOperand(1).getReg())

    .addImm(MI->getOperand(2).getImm())

    .addReg(MI->getOperand(3).getReg())

    .addImm(0);

}


// The XPLINK ABI requires that a no-op encoding the call type is emitted after

// each call to a subroutine. This information can be used by the called

// function to determine its entry point, e.g. for generating a backtrace. The

// call type is encoded as a register number in the bcr instruction. See

// enumeration CallType for the possible values.

void SystemZAsmPrinter::emitCallInformation(CallType CT) {

  EmitToStreamer(*OutStreamer,

                 MCInstBuilder(SystemZ::BCRAsm)

                     .addImm(0)

                     .addReg(SystemZMC::GR64Regs[static_cast<unsigned>(CT)]));

}


uint32_t SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MCSymbol *Sym,

                                                            unsigned SlotKind) {

  auto Key = std::make_pair(Sym, SlotKind);

  auto It = Displacements.find(Key);


  if (It != Displacements.end())

    return (*It).second;


  // Determine length of descriptor.

  uint32_t Length;

  switch (SlotKind) {

  case SystemZII::MO_ADA_DIRECT_FUNC_DESC:

    Length = 2 * PointerSize;

    break;

  default:

    Length = PointerSize;

    break;

  }


  uint32_t Displacement = NextDisplacement;

  Displacements[std::make_pair(Sym, SlotKind)] = NextDisplacement;

  NextDisplacement += Length;


  return Displacement;

}


uint32_t

SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MachineOperand MO) {

  MCSymbol *Sym;

  if (MO.getType() == MachineOperand::MO_GlobalAddress) {

    const GlobalValue *GV = MO.getGlobal();

    Sym = MO.getParent()->getMF()->getTarget().getSymbol(GV);

    assert(Sym && "No symbol");

  } else if (MO.getType() == MachineOperand::MO_ExternalSymbol) {

    const char *SymName = MO.getSymbolName();

    Sym = MO.getParent()->getMF()->getContext().getOrCreateSymbol(SymName);

    assert(Sym && "No symbol");

  } else

    llvm_unreachable("Unexpected operand type");


  unsigned ADAslotType = MO.getTargetFlags();

  return insert(Sym, ADAslotType);

}


void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {

  SystemZ_MC::verifyInstructionPredicates(MI->getOpcode(),

                                          getSubtargetInfo().getFeatureBits());


  SystemZMCInstLower Lower(MF->getContext(), *this);

  MCInst LoweredMI;

  switch (MI->getOpcode()) {

  case SystemZ::Return:

    LoweredMI = MCInstBuilder(SystemZ::BR)

      .addReg(SystemZ::R14D);

    break;


  case SystemZ::Return_XPLINK:

    LoweredMI = MCInstBuilder(SystemZ::B)

      .addReg(SystemZ::R7D)

      .addImm(2)

      .addReg(0);

    break;


  case SystemZ::CondReturn:

    LoweredMI = MCInstBuilder(SystemZ::BCR)

      .addImm(MI->getOperand(0).getImm())

      .addImm(MI->getOperand(1).getImm())

      .addReg(SystemZ::R14D);

    break;


  case SystemZ::CondReturn_XPLINK:

    LoweredMI = MCInstBuilder(SystemZ::BC)

      .addImm(MI->getOperand(0).getImm())

      .addImm(MI->getOperand(1).getImm())

      .addReg(SystemZ::R7D)

      .addImm(2)

      .addReg(0);

    break;


  case SystemZ::CRBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CGRBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CGRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CIBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CGIBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CGIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CLRBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CLRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CLGRBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CLGRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CLIBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CLIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CLGIBReturn:

    LoweredMI = MCInstBuilder(SystemZ::CLGIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(SystemZ::R14D)

      .addImm(0);

    break;


  case SystemZ::CallBRASL_XPLINK64:

    EmitToStreamer(*OutStreamer,

                   MCInstBuilder(SystemZ::BRASL)

                       .addReg(SystemZ::R7D)

                       .addExpr(Lower.getExpr(MI->getOperand(0),

                                              MCSymbolRefExpr::VK_PLT)));

    emitCallInformation(CallType::BRASL7);

    return;


  case SystemZ::CallBASR_XPLINK64:

    EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)

                                     .addReg(SystemZ::R7D)

                                     .addReg(MI->getOperand(0).getReg()));

    emitCallInformation(CallType::BASR76);

    return;


  case SystemZ::CallBASR_STACKEXT:

    EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)

                                     .addReg(SystemZ::R3D)

                                     .addReg(MI->getOperand(0).getReg()));

    emitCallInformation(CallType::BASR33);

    return;


  case SystemZ::ADA_ENTRY_VALUE:

  case SystemZ::ADA_ENTRY: {

    const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();

    const SystemZInstrInfo *TII = Subtarget.getInstrInfo();

    uint32_t Disp = ADATable.insert(MI->getOperand(1));

    Register TargetReg = MI->getOperand(0).getReg();


    Register ADAReg = MI->getOperand(2).getReg();

    Disp += MI->getOperand(3).getImm();

    bool LoadAddr = MI->getOpcode() == SystemZ::ADA_ENTRY;


    unsigned Op0 = LoadAddr ? SystemZ::LA : SystemZ::LG;

    unsigned Op = TII->getOpcodeForOffset(Op0, Disp);


    Register IndexReg = 0;

    if (!Op) {

      if (TargetReg != ADAReg) {

        IndexReg = TargetReg;

        // Use TargetReg to store displacement.

        EmitToStreamer(

            *OutStreamer,

            MCInstBuilder(SystemZ::LLILF).addReg(TargetReg).addImm(Disp));

      } else

        EmitToStreamer(

            *OutStreamer,

            MCInstBuilder(SystemZ::ALGFI).addReg(TargetReg).addImm(Disp));

      Disp = 0;

      Op = Op0;

    }

    EmitToStreamer(*OutStreamer, MCInstBuilder(Op)

                                     .addReg(TargetReg)

                                     .addReg(IndexReg)

                                     .addImm(Disp)

                                     .addReg(ADAReg));


    return;

  }

  case SystemZ::CallBRASL:

    LoweredMI = MCInstBuilder(SystemZ::BRASL)

      .addReg(SystemZ::R14D)

      .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));

    break;


  case SystemZ::CallBASR:

    LoweredMI = MCInstBuilder(SystemZ::BASR)

      .addReg(SystemZ::R14D)

      .addReg(MI->getOperand(0).getReg());

    break;


  case SystemZ::CallJG:

    LoweredMI = MCInstBuilder(SystemZ::JG)

      .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));

    break;


  case SystemZ::CallBRCL:

    LoweredMI = MCInstBuilder(SystemZ::BRCL)

      .addImm(MI->getOperand(0).getImm())

      .addImm(MI->getOperand(1).getImm())

      .addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT));

    break;


  case SystemZ::CallBR:

    LoweredMI = MCInstBuilder(SystemZ::BR)

      .addReg(MI->getOperand(0).getReg());

    break;


  case SystemZ::CallBCR:

    LoweredMI = MCInstBuilder(SystemZ::BCR)

      .addImm(MI->getOperand(0).getImm())

      .addImm(MI->getOperand(1).getImm())

      .addReg(MI->getOperand(2).getReg());

    break;


  case SystemZ::CRBCall:

    LoweredMI = MCInstBuilder(SystemZ::CRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::CGRBCall:

    LoweredMI = MCInstBuilder(SystemZ::CGRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::CIBCall:

    LoweredMI = MCInstBuilder(SystemZ::CIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::CGIBCall:

    LoweredMI = MCInstBuilder(SystemZ::CGIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::CLRBCall:

    LoweredMI = MCInstBuilder(SystemZ::CLRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::CLGRBCall:

    LoweredMI = MCInstBuilder(SystemZ::CLGRB)

      .addReg(MI->getOperand(0).getReg())

      .addReg(MI->getOperand(1).getReg())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::CLIBCall:

    LoweredMI = MCInstBuilder(SystemZ::CLIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::CLGIBCall:

    LoweredMI = MCInstBuilder(SystemZ::CLGIB)

      .addReg(MI->getOperand(0).getReg())

      .addImm(MI->getOperand(1).getImm())

      .addImm(MI->getOperand(2).getImm())

      .addReg(MI->getOperand(3).getReg())

      .addImm(0);

    break;


  case SystemZ::TLS_GDCALL:

    LoweredMI = MCInstBuilder(SystemZ::BRASL)

      .addReg(SystemZ::R14D)

      .addExpr(getTLSGetOffset(MF->getContext()))

      .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSGD));

    break;


  case SystemZ::TLS_LDCALL:

    LoweredMI = MCInstBuilder(SystemZ::BRASL)

      .addReg(SystemZ::R14D)

      .addExpr(getTLSGetOffset(MF->getContext()))

      .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSLDM));

    break;


  case SystemZ::GOT:

    LoweredMI = MCInstBuilder(SystemZ::LARL)

      .addReg(MI->getOperand(0).getReg())

      .addExpr(getGlobalOffsetTable(MF->getContext()));

    break;


  case SystemZ::IILF64:

    LoweredMI = MCInstBuilder(SystemZ::IILF)

      .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))

      .addImm(MI->getOperand(2).getImm());

    break;


  case SystemZ::IIHF64:

    LoweredMI = MCInstBuilder(SystemZ::IIHF)

      .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))

      .addImm(MI->getOperand(2).getImm());

    break;


  case SystemZ::RISBHH:

  case SystemZ::RISBHL:

    LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG);

    break;


  case SystemZ::RISBLH:

  case SystemZ::RISBLL:

    LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG);

    break;


  case SystemZ::VLVGP32:

    LoweredMI = MCInstBuilder(SystemZ::VLVGP)

      .addReg(MI->getOperand(0).getReg())

      .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))

      .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));

    break;


  case SystemZ::VLR32:

  case SystemZ::VLR64:

    LoweredMI = MCInstBuilder(SystemZ::VLR)

      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))

      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));

    break;


  case SystemZ::VL:

    Lower.lower(MI, LoweredMI);

    lowerAlignmentHint(MI, LoweredMI, SystemZ::VLAlign);

    break;


  case SystemZ::VST:

    Lower.lower(MI, LoweredMI);

    lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTAlign);

    break;


  case SystemZ::VLM:

    Lower.lower(MI, LoweredMI);

    lowerAlignmentHint(MI, LoweredMI, SystemZ::VLMAlign);

    break;


  case SystemZ::VSTM:

    Lower.lower(MI, LoweredMI);

    lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTMAlign);

    break;


  case SystemZ::VL32:

    LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF);

    break;


  case SystemZ::VL64:

    LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPG);

    break;


  case SystemZ::VST32:

    LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEF);

    break;


  case SystemZ::VST64:

    LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEG);

    break;


  case SystemZ::LFER:

    LoweredMI = MCInstBuilder(SystemZ::VLGVF)

      .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))

      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))

      .addReg(0).addImm(0);

    break;


  case SystemZ::LEFR:

    LoweredMI = MCInstBuilder(SystemZ::VLVGF)

      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))

      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))

      .addReg(MI->getOperand(1).getReg())

      .addReg(0).addImm(0);

    break;


#define LOWER_LOW(NAME)                                                 \

  case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break


  LOWER_LOW(IILL);

  LOWER_LOW(IILH);

  LOWER_LOW(TMLL);

  LOWER_LOW(TMLH);

  LOWER_LOW(NILL);

  LOWER_LOW(NILH);

  LOWER_LOW(NILF);

  LOWER_LOW(OILL);

  LOWER_LOW(OILH);

  LOWER_LOW(OILF);

  LOWER_LOW(XILF);


#undef LOWER_LOW


#define LOWER_HIGH(NAME) \

  case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break


  LOWER_HIGH(IIHL);

  LOWER_HIGH(IIHH);

  LOWER_HIGH(TMHL);

  LOWER_HIGH(TMHH);

  LOWER_HIGH(NIHL);

  LOWER_HIGH(NIHH);

  LOWER_HIGH(NIHF);

  LOWER_HIGH(OIHL);

  LOWER_HIGH(OIHH);

  LOWER_HIGH(OIHF);

  LOWER_HIGH(XIHF);


#undef LOWER_HIGH


  case SystemZ::Serialize:

    if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())

      LoweredMI = MCInstBuilder(SystemZ::BCRAsm)

        .addImm(14).addReg(SystemZ::R0D);

    else

      LoweredMI = MCInstBuilder(SystemZ::BCRAsm)

        .addImm(15).addReg(SystemZ::R0D);

    break;


  // We want to emit "j .+2" for traps, jumping to the relative immediate field

  // of the jump instruction, which is an illegal instruction. We cannot emit a

  // "." symbol, so create and emit a temp label before the instruction and use

  // that instead.

  case SystemZ::Trap: {

    MCSymbol *DotSym = OutContext.createTempSymbol();

    OutStreamer->emitLabel(DotSym);


    const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);

    const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);

    LoweredMI = MCInstBuilder(SystemZ::J)

      .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));

    }

    break;


  // Conditional traps will create a branch on condition instruction that jumps

  // to the relative immediate field of the jump instruction. (eg. "jo .+2")

  case SystemZ::CondTrap: {

    MCSymbol *DotSym = OutContext.createTempSymbol();

    OutStreamer->emitLabel(DotSym);


    const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);

    const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);

    LoweredMI = MCInstBuilder(SystemZ::BRC)

      .addImm(MI->getOperand(0).getImm())

      .addImm(MI->getOperand(1).getImm())

      .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));

    }

    break;


  case TargetOpcode::FENTRY_CALL:

    LowerFENTRY_CALL(*MI, Lower);

    return;


  case TargetOpcode::STACKMAP:

    LowerSTACKMAP(*MI);

    return;


  case TargetOpcode::PATCHPOINT:

    LowerPATCHPOINT(*MI, Lower);

    return;


  case SystemZ::EXRL_Pseudo: {

    unsigned TargetInsOpc = MI->getOperand(0).getImm();

    Register LenMinus1Reg = MI->getOperand(1).getReg();

    Register DestReg = MI->getOperand(2).getReg();

    int64_t DestDisp = MI->getOperand(3).getImm();

    Register SrcReg = MI->getOperand(4).getReg();

    int64_t SrcDisp = MI->getOperand(5).getImm();


    SystemZTargetStreamer *TS = getTargetStreamer();

    MCSymbol *DotSym = nullptr;

    MCInst ET = MCInstBuilder(TargetInsOpc).addReg(DestReg)

      .addImm(DestDisp).addImm(1).addReg(SrcReg).addImm(SrcDisp);

    SystemZTargetStreamer::MCInstSTIPair ET_STI(ET, &MF->getSubtarget());

    SystemZTargetStreamer::EXRLT2SymMap::iterator I =

        TS->EXRLTargets2Sym.find(ET_STI);

    if (I != TS->EXRLTargets2Sym.end())

      DotSym = I->second;

    else

      TS->EXRLTargets2Sym[ET_STI] = DotSym = OutContext.createTempSymbol();

    const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext);

    EmitToStreamer(

        *OutStreamer,

        MCInstBuilder(SystemZ::EXRL).addReg(LenMinus1Reg).addExpr(Dot));

    return;

  }


  default:

    Lower.lower(MI, LoweredMI);

    break;

  }

  EmitToStreamer(*OutStreamer, LoweredMI);

}


// Emit the largest nop instruction smaller than or equal to NumBytes

// bytes.  Return the size of nop emitted.

static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer,

                        unsigned NumBytes, const MCSubtargetInfo &STI) {

  if (NumBytes < 2) {

    llvm_unreachable("Zero nops?");

    return 0;

  }

  else if (NumBytes < 4) {

    OutStreamer.emitInstruction(

        MCInstBuilder(SystemZ::BCRAsm).addImm(0).addReg(SystemZ::R0D), STI);

    return 2;

  }

  else if (NumBytes < 6) {

    OutStreamer.emitInstruction(

        MCInstBuilder(SystemZ::BCAsm).addImm(0).addReg(0).addImm(0).addReg(0),

        STI);

    return 4;

  }

  else {

    MCSymbol *DotSym = OutContext.createTempSymbol();

    const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext);

    OutStreamer.emitLabel(DotSym);

    OutStreamer.emitInstruction(

        MCInstBuilder(SystemZ::BRCLAsm).addImm(0).addExpr(Dot), STI);

    return 6;

  }

}


void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,

                                         SystemZMCInstLower &Lower) {

  MCContext &Ctx = MF->getContext();

  if (MF->getFunction().hasFnAttribute("mrecord-mcount")) {

    MCSymbol *DotSym = OutContext.createTempSymbol();

    OutStreamer->pushSection();

    OutStreamer->switchSection(

        Ctx.getELFSection("__mcount_loc", ELF::SHT_PROGBITS, ELF::SHF_ALLOC));

    OutStreamer->emitSymbolValue(DotSym, 8);

    OutStreamer->popSection();

    OutStreamer->emitLabel(DotSym);

  }


  if (MF->getFunction().hasFnAttribute("mnop-mcount")) {

    EmitNop(Ctx, *OutStreamer, 6, getSubtargetInfo());

    return;

  }


  MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");

  const MCSymbolRefExpr *Op =

      MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_PLT, Ctx);

  OutStreamer->emitInstruction(

      MCInstBuilder(SystemZ::BRASL).addReg(SystemZ::R0D).addExpr(Op),

      getSubtargetInfo());

}


void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {

  auto *TII = MF->getSubtarget<SystemZSubtarget>().getInstrInfo();


  unsigned NumNOPBytes = MI.getOperand(1).getImm();


  auto &Ctx = OutStreamer->getContext();

  MCSymbol *MILabel = Ctx.createTempSymbol();

  OutStreamer->emitLabel(MILabel);


  SM.recordStackMap(*MILabel, MI);

  assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");


  // Scan ahead to trim the shadow.

  unsigned ShadowBytes = 0;

  const MachineBasicBlock &MBB = *MI.getParent();

  MachineBasicBlock::const_iterator MII(MI);

  ++MII;

  while (ShadowBytes < NumNOPBytes) {

    if (MII == MBB.end() ||

        MII->getOpcode() == TargetOpcode::PATCHPOINT ||

        MII->getOpcode() == TargetOpcode::STACKMAP)

      break;

    ShadowBytes += TII->getInstSizeInBytes(*MII);

    if (MII->isCall())

      break;

    ++MII;

  }


  // Emit nops.

  while (ShadowBytes < NumNOPBytes)

    ShadowBytes += EmitNop(OutContext, *OutStreamer, NumNOPBytes - ShadowBytes,

                           getSubtargetInfo());

}


// Lower a patchpoint of the form:

// [<def>], <id>, <numBytes>, <target>, <numArgs>

void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,

                                        SystemZMCInstLower &Lower) {

  auto &Ctx = OutStreamer->getContext();

  MCSymbol *MILabel = Ctx.createTempSymbol();

  OutStreamer->emitLabel(MILabel);


  SM.recordPatchPoint(*MILabel, MI);

  PatchPointOpers Opers(&MI);


  unsigned EncodedBytes = 0;

  const MachineOperand &CalleeMO = Opers.getCallTarget();


  if (CalleeMO.isImm()) {

    uint64_t CallTarget = CalleeMO.getImm();

    if (CallTarget) {

      unsigned ScratchIdx = -1;

      unsigned ScratchReg = 0;

      do {

        ScratchIdx = Opers.getNextScratchIdx(ScratchIdx + 1);

        ScratchReg = MI.getOperand(ScratchIdx).getReg();

      } while (ScratchReg == SystemZ::R0D);


      // Materialize the call target address

      EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::LLILF)

                                      .addReg(ScratchReg)

                                      .addImm(CallTarget & 0xFFFFFFFF));

      EncodedBytes += 6;

      if (CallTarget >> 32) {

        EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::IIHF)

                                        .addReg(ScratchReg)

                                        .addImm(CallTarget >> 32));

        EncodedBytes += 6;

      }


      EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)

                                     .addReg(SystemZ::R14D)

                                     .addReg(ScratchReg));

      EncodedBytes += 2;

    }

  } else if (CalleeMO.isGlobal()) {

    const MCExpr *Expr = Lower.getExpr(CalleeMO, MCSymbolRefExpr::VK_PLT);

    EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BRASL)

                                   .addReg(SystemZ::R14D)

                                   .addExpr(Expr));

    EncodedBytes += 6;

  }


  // Emit padding.

  unsigned NumBytes = Opers.getNumPatchBytes();

  assert(NumBytes >= EncodedBytes &&

         "Patchpoint can't request size less than the length of a call.");

  assert((NumBytes - EncodedBytes) % 2 == 0 &&

         "Invalid number of NOP bytes requested!");

  while (EncodedBytes < NumBytes)

    EncodedBytes += EmitNop(OutContext, *OutStreamer, NumBytes - EncodedBytes,

                            getSubtargetInfo());

}


// The *alignment* of 128-bit vector types is different between the software

// and hardware vector ABIs. If the there is an externally visible use of a

// vector type in the module it should be annotated with an attribute.

void SystemZAsmPrinter::emitAttributes(Module &M) {

  if (M.getModuleFlag("s390x-visible-vector-ABI")) {

    bool HasVectorFeature =

      TM.getMCSubtargetInfo()->hasFeature(SystemZ::FeatureVector);

    OutStreamer->emitGNUAttribute(8, HasVectorFeature ? 2 : 1);

  }

}


// Convert a SystemZ-specific constant pool modifier into the associated

// MCSymbolRefExpr variant kind.

static MCSymbolRefExpr::VariantKind

getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier) {

  switch (Modifier) {

  case SystemZCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;

  case SystemZCP::TLSLDM: return MCSymbolRefExpr::VK_TLSLDM;

  case SystemZCP::DTPOFF: return MCSymbolRefExpr::VK_DTPOFF;

  case SystemZCP::NTPOFF: return MCSymbolRefExpr::VK_NTPOFF;

  }

  llvm_unreachable("Invalid SystemCPModifier!");

}


void SystemZAsmPrinter::emitMachineConstantPoolValue(

    MachineConstantPoolValue *MCPV) {

  auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);


  const MCExpr *Expr =

    MCSymbolRefExpr::create(getSymbol(ZCPV->getGlobalValue()),

                            getModifierVariantKind(ZCPV->getModifier()),

                            OutContext);

  uint64_t Size = getDataLayout().getTypeAllocSize(ZCPV->getType());


  OutStreamer->emitValue(Expr, Size);

}


static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo,

                                  raw_ostream &OS) {

  const char *RegName = SystemZInstPrinter::getRegisterName(RegNo);

  if (MAI->getAssemblerDialect() == AD_HLASM) {

    // Skip register prefix so that only register number is left

    assert(isalpha(RegName[0]) && isdigit(RegName[1]));

    OS << (RegName + 1);

  } else

    OS << '%' << RegName;

}


static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI,

                         raw_ostream &OS) {

  if (MCOp.isReg()) {

    if (!MCOp.getReg())

      OS << '0';

    else

      printFormattedRegName(MAI, MCOp.getReg(), OS);

  } else if (MCOp.isImm())

    OS << MCOp.getImm();

  else if (MCOp.isExpr())

    MCOp.getExpr()->print(OS, MAI);

  else

    llvm_unreachable("Invalid operand");

}


static void printAddress(const MCAsmInfo *MAI, unsigned Base,

                         const MCOperand &DispMO, unsigned Index,

                         raw_ostream &OS) {

  printOperand(DispMO, MAI, OS);

  if (Base || Index) {

    OS << '(';

    if (Index) {

      printFormattedRegName(MAI, Index, OS);

      if (Base)

        OS << ',';

    }

    if (Base)

      printFormattedRegName(MAI, Base, OS);

    OS << ')';

  }

}


bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,

                                        const char *ExtraCode,

                                        raw_ostream &OS) {

  const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();

  const MachineOperand &MO = MI->getOperand(OpNo);

  MCOperand MCOp;

  if (ExtraCode) {

    if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() &&

        SystemZ::GR128BitRegClass.contains(MO.getReg()))

      MCOp =

          MCOperand::createReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64));

    else

      return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);

  } else {

    SystemZMCInstLower Lower(MF->getContext(), *this);

    MCOp = Lower.lowerOperand(MO);

  }

  printOperand(MCOp, MAI, OS);

  return false;

}


bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,

                                              unsigned OpNo,

                                              const char *ExtraCode,

                                              raw_ostream &OS) {

  printAddress(MAI, MI->getOperand(OpNo).getReg(),

               MCOperand::createImm(MI->getOperand(OpNo + 1).getImm()),

               MI->getOperand(OpNo + 2).getReg(), OS);

  return false;

}


void SystemZAsmPrinter::emitEndOfAsmFile(Module &M) {

  auto TT = OutContext.getTargetTriple();

  if (TT.isOSzOS()) {

    emitADASection();

  }

  emitAttributes(M);

}


void SystemZAsmPrinter::emitADASection() {

  OutStreamer->pushSection();


  const unsigned PointerSize = getDataLayout().getPointerSize();

  OutStreamer->switchSection(getObjFileLowering().getADASection());


  unsigned EmittedBytes = 0;

  for (auto &Entry : ADATable.getTable()) {

    const MCSymbol *Sym;

    unsigned SlotKind;

    std::tie(Sym, SlotKind) = Entry.first;

    unsigned Offset = Entry.second;

    assert(Offset == EmittedBytes && "Offset not as expected");

    (void)EmittedBytes;

#define EMIT_COMMENT(Str)                                                      \

  OutStreamer->AddComment(Twine("Offset ")                                     \

                              .concat(utostr(Offset))                          \

                              .concat(" " Str " ")                             \

                              .concat(Sym->getName()));

    switch (SlotKind) {

    case SystemZII::MO_ADA_DIRECT_FUNC_DESC:

      // Language Environment DLL logic requires function descriptors, for

      // imported functions, that are placed in the ADA to be 8 byte aligned.

      EMIT_COMMENT("function descriptor of");

      OutStreamer->emitValue(

          SystemZMCExpr::create(SystemZMCExpr::VK_SystemZ_RCon,

                                MCSymbolRefExpr::create(Sym, OutContext),

                                OutContext),

          PointerSize);

      OutStreamer->emitValue(

          SystemZMCExpr::create(SystemZMCExpr::VK_SystemZ_VCon,

                                MCSymbolRefExpr::create(Sym, OutContext),

                                OutContext),

          PointerSize);

      EmittedBytes += PointerSize * 2;

      break;

    case SystemZII::MO_ADA_DATA_SYMBOL_ADDR:

      EMIT_COMMENT("pointer to data symbol");

      OutStreamer->emitValue(

          SystemZMCExpr::create(SystemZMCExpr::VK_SystemZ_None,

                                MCSymbolRefExpr::create(Sym, OutContext),

                                OutContext),

          PointerSize);

      EmittedBytes += PointerSize;

      break;

    case SystemZII::MO_ADA_INDIRECT_FUNC_DESC: {

      MCSymbol *Alias = OutContext.createTempSymbol(

          Twine(Sym->getName()).concat("@indirect"));

      OutStreamer->emitAssignment(Alias,

                                  MCSymbolRefExpr::create(Sym, OutContext));

      OutStreamer->emitSymbolAttribute(Alias, MCSA_IndirectSymbol);


      EMIT_COMMENT("pointer to function descriptor");

      OutStreamer->emitValue(

          SystemZMCExpr::create(SystemZMCExpr::VK_SystemZ_VCon,

                                MCSymbolRefExpr::create(Alias, OutContext),

                                OutContext),

          PointerSize);

      EmittedBytes += PointerSize;

      break;

    }

    default:

      llvm_unreachable("Unexpected slot kind");

    }

#undef EMIT_COMMENT

  }

  OutStreamer->popSection();

}


void SystemZAsmPrinter::emitFunctionBodyEnd() {

  if (TM.getTargetTriple().isOSzOS()) {

    // Emit symbol for the end of function if the z/OS target streamer

    // is used. This is needed to calculate the size of the function.

    MCSymbol *FnEndSym = createTempSymbol("func_end");

    OutStreamer->emitLabel(FnEndSym);


    OutStreamer->pushSection();

    OutStreamer->switchSection(getObjFileLowering().getPPA1Section());

    emitPPA1(FnEndSym);

    OutStreamer->popSection();


    CurrentFnPPA1Sym = nullptr;

    CurrentFnEPMarkerSym = nullptr;

  }

}


static void emitPPA1Flags(std::unique_ptr<MCStreamer> &OutStreamer, bool VarArg,

                          bool StackProtector, bool FPRMask, bool VRMask,

                          bool HasName) {

  enum class PPA1Flag1 : uint8_t {

    DSA64Bit = (0x80 >> 0),

    VarArg = (0x80 >> 7),

    LLVM_MARK_AS_BITMASK_ENUM(DSA64Bit)

  };

  enum class PPA1Flag2 : uint8_t {

    ExternalProcedure = (0x80 >> 0),

    STACKPROTECTOR = (0x80 >> 3),

    LLVM_MARK_AS_BITMASK_ENUM(ExternalProcedure)

  };

  enum class PPA1Flag3 : uint8_t {

    FPRMask = (0x80 >> 2),

    LLVM_MARK_AS_BITMASK_ENUM(FPRMask)

  };

  enum class PPA1Flag4 : uint8_t {

    EPMOffsetPresent = (0x80 >> 0),

    VRMask = (0x80 >> 2),

    ProcedureNamePresent = (0x80 >> 7),

    LLVM_MARK_AS_BITMASK_ENUM(EPMOffsetPresent)

  };


  // Declare optional section flags that can be modified.

  auto Flags1 = PPA1Flag1(0);

  auto Flags2 = PPA1Flag2::ExternalProcedure;

  auto Flags3 = PPA1Flag3(0);

  auto Flags4 = PPA1Flag4::EPMOffsetPresent;


  Flags1 |= PPA1Flag1::DSA64Bit;


  if (VarArg)

    Flags1 |= PPA1Flag1::VarArg;


  if (StackProtector)

    Flags2 |= PPA1Flag2::STACKPROTECTOR;


  // SavedGPRMask, SavedFPRMask, and SavedVRMask are precomputed in.

  if (FPRMask)

    Flags3 |= PPA1Flag3::FPRMask; // Add emit FPR mask flag.


  if (VRMask)

    Flags4 |= PPA1Flag4::VRMask; // Add emit VR mask flag.


  if (HasName)

    Flags4 |= PPA1Flag4::ProcedureNamePresent; // Add optional name block.


  OutStreamer->AddComment("PPA1 Flags 1");

  if ((Flags1 & PPA1Flag1::DSA64Bit) == PPA1Flag1::DSA64Bit)

    OutStreamer->AddComment("  Bit 0: 1 = 64-bit DSA");

  else

    OutStreamer->AddComment("  Bit 0: 0 = 32-bit DSA");

  if ((Flags1 & PPA1Flag1::VarArg) == PPA1Flag1::VarArg)

    OutStreamer->AddComment("  Bit 7: 1 = Vararg function");

  OutStreamer->emitInt8(static_cast<uint8_t>(Flags1)); // Flags 1.


  OutStreamer->AddComment("PPA1 Flags 2");

  if ((Flags2 & PPA1Flag2::ExternalProcedure) == PPA1Flag2::ExternalProcedure)

    OutStreamer->AddComment("  Bit 0: 1 = External procedure");

  if ((Flags2 & PPA1Flag2::STACKPROTECTOR) == PPA1Flag2::STACKPROTECTOR)

    OutStreamer->AddComment("  Bit 3: 1 = STACKPROTECT is enabled");

  else

    OutStreamer->AddComment("  Bit 3: 0 = STACKPROTECT is not enabled");

  OutStreamer->emitInt8(static_cast<uint8_t>(Flags2)); // Flags 2.


  OutStreamer->AddComment("PPA1 Flags 3");

  if ((Flags3 & PPA1Flag3::FPRMask) == PPA1Flag3::FPRMask)

    OutStreamer->AddComment("  Bit 2: 1 = FP Reg Mask is in optional area");

  OutStreamer->emitInt8(

      static_cast<uint8_t>(Flags3)); // Flags 3 (optional sections).


  OutStreamer->AddComment("PPA1 Flags 4");

  if ((Flags4 & PPA1Flag4::VRMask) == PPA1Flag4::VRMask)

    OutStreamer->AddComment("  Bit 2: 1 = Vector Reg Mask is in optional area");

  if ((Flags4 & PPA1Flag4::ProcedureNamePresent) ==

      PPA1Flag4::ProcedureNamePresent)

    OutStreamer->AddComment("  Bit 7: 1 = Name Length and Name");

  OutStreamer->emitInt8(static_cast<uint8_t>(

      Flags4)); // Flags 4 (optional sections, always emit these).

}


static void emitPPA1Name(std::unique_ptr<MCStreamer> &OutStreamer,

                         StringRef OutName) {

  size_t NameSize = OutName.size();

  uint16_t OutSize;

  if (NameSize < UINT16_MAX) {

    OutSize = static_cast<uint16_t>(NameSize);

  } else {

    OutName = OutName.substr(0, UINT16_MAX);

    OutSize = UINT16_MAX;

  }

  // Emit padding to ensure that the next optional field word-aligned.

  uint8_t ExtraZeros = 4 - ((2 + OutSize) % 4);


  SmallString<512> OutnameConv;

  ConverterEBCDIC::convertToEBCDIC(OutName, OutnameConv);

  OutName = OutnameConv.str();


  OutStreamer->AddComment("Length of Name");

  OutStreamer->emitInt16(OutSize);

  OutStreamer->AddComment("Name of Function");

  OutStreamer->emitBytes(OutName);

  OutStreamer->emitZeros(ExtraZeros);

}


void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {

  const TargetRegisterInfo *TRI = MF->getRegInfo().getTargetRegisterInfo();

  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();

  const auto TargetHasVector = Subtarget.hasVector();


  const SystemZMachineFunctionInfo *ZFI =

      MF->getInfo<SystemZMachineFunctionInfo>();

  const auto *ZFL = static_cast<const SystemZXPLINKFrameLowering *>(

      Subtarget.getFrameLowering());

  const MachineFrameInfo &MFFrame = MF->getFrameInfo();


  // Get saved GPR/FPR/VPR masks.

  const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();

  uint16_t SavedGPRMask = 0;

  uint16_t SavedFPRMask = 0;

  uint8_t SavedVRMask = 0;

  int64_t OffsetFPR = 0;

  int64_t OffsetVR = 0;

  const int64_t TopOfStack =

      MFFrame.getOffsetAdjustment() + MFFrame.getStackSize();


  // Loop over the spilled registers. The CalleeSavedInfo can't be used because

  // it does not contain all spilled registers.

  for (unsigned I = ZFI->getSpillGPRRegs().LowGPR,

                E = ZFI->getSpillGPRRegs().HighGPR;

       I && E && I <= E; ++I) {

    unsigned V = TRI->getEncodingValue((Register)I);

    assert(V < 16 && "GPR index out of range");

    SavedGPRMask |= 1 << (15 - V);

  }


  for (auto &CS : CSI) {

    unsigned Reg = CS.getReg();

    unsigned I = TRI->getEncodingValue(Reg);


    if (SystemZ::FP64BitRegClass.contains(Reg)) {

      assert(I < 16 && "FPR index out of range");

      SavedFPRMask |= 1 << (15 - I);

      int64_t Temp = MFFrame.getObjectOffset(CS.getFrameIdx());

      if (Temp < OffsetFPR)

        OffsetFPR = Temp;

    } else if (SystemZ::VR128BitRegClass.contains(Reg)) {

      assert(I >= 16 && I <= 23 && "VPR index out of range");

      unsigned BitNum = I - 16;

      SavedVRMask |= 1 << (7 - BitNum);

      int64_t Temp = MFFrame.getObjectOffset(CS.getFrameIdx());

      if (Temp < OffsetVR)

        OffsetVR = Temp;

    }

  }


  // Adjust the offset.

  OffsetFPR += (OffsetFPR < 0) ? TopOfStack : 0;

  OffsetVR += (OffsetVR < 0) ? TopOfStack : 0;


  // Get alloca register.

  uint8_t FrameReg = TRI->getEncodingValue(TRI->getFrameRegister(*MF));

  uint8_t AllocaReg = ZFL->hasFP(*MF) ? FrameReg : 0;

  assert(AllocaReg < 16 && "Can't have alloca register larger than 15");

  (void)AllocaReg;


  // Build FPR save area offset.

  uint32_t FrameAndFPROffset = 0;

  if (SavedFPRMask) {

    uint64_t FPRSaveAreaOffset = OffsetFPR;

    assert(FPRSaveAreaOffset < 0x10000000 && "Offset out of range");


    FrameAndFPROffset = FPRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.

    FrameAndFPROffset |= FrameReg << 28;                // Put into top 4 bits.

  }


  // Build VR save area offset.

  uint32_t FrameAndVROffset = 0;

  if (TargetHasVector && SavedVRMask) {

    uint64_t VRSaveAreaOffset = OffsetVR;

    assert(VRSaveAreaOffset < 0x10000000 && "Offset out of range");


    FrameAndVROffset = VRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.

    FrameAndVROffset |= FrameReg << 28;               // Put into top 4 bits.

  }


  // Emit PPA1 section.

  OutStreamer->AddComment("PPA1");

  OutStreamer->emitLabel(CurrentFnPPA1Sym);

  OutStreamer->AddComment("Version");

  OutStreamer->emitInt8(0x02); // Version.

  OutStreamer->AddComment("LE Signature X'CE'");

  OutStreamer->emitInt8(0xCE); // CEL signature.

  OutStreamer->AddComment("Saved GPR Mask");

  OutStreamer->emitInt16(SavedGPRMask);


  bool HasName =

      MF->getFunction().hasName() && MF->getFunction().getName().size() > 0;


  emitPPA1Flags(OutStreamer, MF->getFunction().isVarArg(),

                MFFrame.hasStackProtectorIndex(), SavedFPRMask != 0,

                TargetHasVector && SavedVRMask != 0, HasName);


  OutStreamer->AddComment("Length/4 of Parms");

  OutStreamer->emitInt16(

      static_cast<uint16_t>(ZFI->getSizeOfFnParams() / 4)); // Parms/4.

  OutStreamer->AddComment("Length of Code");

  OutStreamer->emitAbsoluteSymbolDiff(FnEndSym, CurrentFnEPMarkerSym, 4);


  // Emit saved FPR mask and offset to FPR save area (0x20 of flags 3).

  if (SavedFPRMask) {

    OutStreamer->AddComment("FPR mask");

    OutStreamer->emitInt16(SavedFPRMask);

    OutStreamer->AddComment("AR mask");

    OutStreamer->emitInt16(0); // AR Mask, unused currently.

    OutStreamer->AddComment("FPR Save Area Locator");

    OutStreamer->AddComment(Twine("  Bit 0-3: Register R")

                                .concat(utostr(FrameAndFPROffset >> 28))

                                .str());

    OutStreamer->AddComment(Twine("  Bit 4-31: Offset ")

                                .concat(utostr(FrameAndFPROffset & 0x0FFFFFFF))

                                .str());

    OutStreamer->emitInt32(FrameAndFPROffset); // Offset to FPR save area with

                                               // register to add value to

                                               // (alloca reg).

  }


  // Emit saved VR mask to VR save area.

  if (TargetHasVector && SavedVRMask) {

    OutStreamer->AddComment("VR mask");

    OutStreamer->emitInt8(SavedVRMask);

    OutStreamer->emitInt8(0);  // Reserved.

    OutStreamer->emitInt16(0); // Also reserved.

    OutStreamer->AddComment("VR Save Area Locator");

    OutStreamer->AddComment(Twine("  Bit 0-3: Register R")

                                .concat(utostr(FrameAndVROffset >> 28))

                                .str());

    OutStreamer->AddComment(Twine("  Bit 4-31: Offset ")

                                .concat(utostr(FrameAndVROffset & 0x0FFFFFFF))

                                .str());

    OutStreamer->emitInt32(FrameAndVROffset);

  }


  // Emit name length and name optional section (0x01 of flags 4)

  if (HasName)

    emitPPA1Name(OutStreamer, MF->getFunction().getName());


  // Emit offset to entry point optional section (0x80 of flags 4).

  OutStreamer->emitAbsoluteSymbolDiff(CurrentFnEPMarkerSym, CurrentFnPPA1Sym,

                                      4);

}


void SystemZAsmPrinter::emitFunctionEntryLabel() {

  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();


  if (Subtarget.getTargetTriple().isOSzOS()) {

    MCContext &OutContext = OutStreamer->getContext();


    // Save information for later use.

    std::string N(MF->getFunction().hasName()

                      ? Twine(MF->getFunction().getName()).concat("_").str()

                      : "");


    CurrentFnEPMarkerSym =

        OutContext.createTempSymbol(Twine("EPM_").concat(N).str(), true);

    CurrentFnPPA1Sym =

        OutContext.createTempSymbol(Twine("PPA1_").concat(N).str(), true);


    // EntryPoint Marker

    const MachineFrameInfo &MFFrame = MF->getFrameInfo();

    bool IsUsingAlloca = MFFrame.hasVarSizedObjects();

    uint32_t DSASize = MFFrame.getStackSize();

    bool IsLeaf = DSASize == 0 && MFFrame.getCalleeSavedInfo().empty();


    // Set Flags

    uint8_t Flags = 0;

    if (IsLeaf)

      Flags |= 0x08;

    if (IsUsingAlloca)

      Flags |= 0x04;


    // Combine into top 27 bits of DSASize and bottom 5 bits of Flags.

    uint32_t DSAAndFlags = DSASize & 0xFFFFFFE0; // (x/32) << 5

    DSAAndFlags |= Flags;


    // Emit entry point marker section.

    OutStreamer->AddComment("XPLINK Routine Layout Entry");

    OutStreamer->emitLabel(CurrentFnEPMarkerSym);

    OutStreamer->AddComment("Eyecatcher 0x00C300C500C500");

    OutStreamer->emitIntValueInHex(0x00C300C500C500, 7); // Eyecatcher.

    OutStreamer->AddComment("Mark Type C'1'");

    OutStreamer->emitInt8(0xF1); // Mark Type.

    OutStreamer->AddComment("Offset to PPA1");

    OutStreamer->emitAbsoluteSymbolDiff(CurrentFnPPA1Sym, CurrentFnEPMarkerSym,

                                        4);

    if (OutStreamer->isVerboseAsm()) {

      OutStreamer->AddComment("DSA Size 0x" + Twine::utohexstr(DSASize));

      OutStreamer->AddComment("Entry Flags");

      if (Flags & 0x08)

        OutStreamer->AddComment("  Bit 1: 1 = Leaf function");

      else

        OutStreamer->AddComment("  Bit 1: 0 = Non-leaf function");

      if (Flags & 0x04)

        OutStreamer->AddComment("  Bit 2: 1 = Uses alloca");

      else

        OutStreamer->AddComment("  Bit 2: 0 = Does not use alloca");

    }

    OutStreamer->emitInt32(DSAAndFlags);

  }


  AsmPrinter::emitFunctionEntryLabel();

}


// Force static initialization.

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmPrinter() {

  RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget());

}

MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105

MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74

getModifierVariantKind
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
Definition: ARMAsmPrinter.cpp:839

ELF.h

E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135

ConvertEBCDIC.h
This file provides utility functions for converting between EBCDIC-1047 and UTF-8.

Name
std::string Name
Definition: ELFObjHandler.cpp:77

Size
uint64_t Size
Definition: ELFObjHandler.cpp:81

Sym
Symbol * Sym
Definition: ELF_riscv.cpp:468

X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125

MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110

RegName
#define RegName(no)

MCExpr.h

MCInstBuilder.h

MCSectionELF.h

MCStreamer.h

I
#define I(x, y, z)
Definition: MD5.cpp:58

MachineModuleInfoImpls.h

TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1627

Mangler.h

Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66

assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

OS
raw_pwrite_stream & OS
Definition: SampleProfWriter.cpp:53

printOperand
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
Definition: SelectionDAGDumper.cpp:987

StringExtras.h
This file contains some functions that are useful when dealing with strings.

emitPPA1Name
static void emitPPA1Name(std::unique_ptr< MCStreamer > &OutStreamer, StringRef OutName)
Definition: SystemZAsmPrinter.cpp:1128

LOWER_LOW
#define LOWER_LOW(NAME)

lowerAlignmentHint
static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:92

EMIT_COMMENT
#define EMIT_COMMENT(Str)

getGlobalOffsetTable
static const MCSymbolRefExpr * getGlobalOffsetTable(MCContext &Context)
Definition: SystemZAsmPrinter.cpp:81

LOWER_HIGH
#define LOWER_HIGH(NAME)

printFormattedRegName
static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo, raw_ostream &OS)
Definition: SystemZAsmPrinter.cpp:878

lowerRILow
static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:36

lowerRIHigh
static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:50

LLVMInitializeSystemZAsmPrinter
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmPrinter()
Definition: SystemZAsmPrinter.cpp:1361

emitPPA1Flags
static void emitPPA1Flags(std::unique_ptr< MCStreamer > &OutStreamer, bool VarArg, bool StackProtector, bool FPRMask, bool VRMask, bool HasName)
Definition: SystemZAsmPrinter.cpp:1046

printAddress
static void printAddress(const MCAsmInfo *MAI, unsigned Base, const MCOperand &DispMO, unsigned Index, raw_ostream &OS)
Definition: SystemZAsmPrinter.cpp:904

getTLSGetOffset
static const MCSymbolRefExpr * getTLSGetOffset(MCContext &Context)
Definition: SystemZAsmPrinter.cpp:74

lowerSubvectorStore
static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:127

EmitNop
static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer, unsigned NumBytes, const MCSubtargetInfo &STI)
Definition: SystemZAsmPrinter.cpp:694

lowerSubvectorLoad
static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:117

lowerRIEfLow
static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:64

SystemZAsmPrinter.h

SystemZConstantPoolValue.h

SystemZInstPrinter.h

SystemZMCExpr.h

SystemZMCInstLower.h

SystemZTargetInfo.h

TargetLoweringObjectFileImpl.h

TargetRegistry.h

contains
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:470

T

llvm::AsmPrinter::getObjFileLowering
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:381

llvm::AsmPrinter::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:671

llvm::AsmPrinter::EmitToStreamer
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:401

llvm::AsmPrinter::TM
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:88

llvm::AsmPrinter::MAI
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:91

llvm::AsmPrinter::MF
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:103

llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:95

llvm::AsmPrinter::createTempSymbol
MCSymbol * createTempSymbol(const Twine &Name) const
Definition: AsmPrinter.cpp:3647

llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:100

llvm::AsmPrinter::SM
StackMaps SM
Definition: AsmPrinter.h:211

llvm::AsmPrinter::getDataLayout
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:385

llvm::AsmPrinter::emitFunctionEntryLabel
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: AsmPrinter.cpp:1050

llvm::AsmPrinter::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:396

llvm::AsmPrinter::PrintAsmOperand
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: AsmPrinterInlineAsm.cpp:468

llvm::DWARFExpression::Operation
This class represents an Operation in the Expression.
Definition: DWARFExpression.h:32

llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:504

llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:748

llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:189

llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:645

llvm::GlobalValue
Definition: GlobalValue.h:44

llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56

llvm::MCAsmInfo::getAssemblerDialect
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:686

llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:528

llvm::MCConstantExpr
Definition: MCExpr.h:144

llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194

llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76

llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:322

llvm::MCContext::getELFSection
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:565

llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201

llvm::MCContext::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCContext.h:434

llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35

llvm::MCExpr::print
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41

llvm::MCInstBuilder
Definition: MCInstBuilder.h:21

llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31

llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37

llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:55

llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184

llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210

llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197

llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36

llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134

llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80

llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141

llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62

llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69

llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61

llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114

llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65

llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:139

llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212

llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1104

llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:424

llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76

llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119

llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192

llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194

llvm::MCSymbolRefExpr::VK_DTPOFF
@ VK_DTPOFF
Definition: MCExpr.h:213

llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195

llvm::MCSymbolRefExpr::VK_TLSLDM
@ VK_TLSLDM
Definition: MCExpr.h:211

llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:209

llvm::MCSymbolRefExpr::VK_PLT
@ VK_PLT
Definition: MCExpr.h:208

llvm::MCSymbolRefExpr::VK_NTPOFF
@ VK_NTPOFF
Definition: MCExpr.h:206

llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:389

llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41

llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95

llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:320

llvm::MachineConstantPoolValue
Abstract base class for all machine specific constantpool value subclasses.
Definition: MachineConstantPool.h:35

llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106

llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355

llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585

llvm::MachineFrameInfo::getOffsetAdjustment
int getOffsetAdjustment() const
Return the correction for frame offsets.
Definition: MachineFrameInfo.h:594

llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787

llvm::MachineFrameInfo::hasStackProtectorIndex
bool hasStackProtectorIndex() const
Definition: MachineFrameInfo.h:360

llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526

llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:708

llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:724

llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:660

llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:718

llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:674

llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:704

llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:806

llvm::MachineInstrBundleIterator< const MachineInstr >

llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:68

llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:704

llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48

llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:582

llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:556

llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:329

llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:331

llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:243

llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:226

llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:347

llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:224

llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:637

llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:369

llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61

llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60

llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:157

llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65

llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76

llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19

llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26

llvm::SmallString::str
StringRef str() const
Explicit conversion to StringRef.
Definition: SmallString.h:261

llvm::StackMaps::recordPatchPoint
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:554

llvm::StackMaps::recordStackMap
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:544

llvm::StackProtector
Definition: StackProtector.h:34

llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50

llvm::StringRef::substr
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:575

llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137

llvm::SystemZAsmPrinter::emitMachineConstantPoolValue
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
Definition: SystemZAsmPrinter.cpp:865

llvm::SystemZAsmPrinter::emitFunctionBodyEnd
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Definition: SystemZAsmPrinter.cpp:1029

llvm::SystemZAsmPrinter::emitInstruction
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
Definition: SystemZAsmPrinter.cpp:192

llvm::SystemZAsmPrinter::PrintAsmMemoryOperand
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
Definition: SystemZAsmPrinter.cpp:942

llvm::SystemZAsmPrinter::emitFunctionEntryLabel
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: SystemZAsmPrinter.cpp:1299

llvm::SystemZAsmPrinter::PrintAsmOperand
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: SystemZAsmPrinter.cpp:921

llvm::SystemZAsmPrinter::emitEndOfAsmFile
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
Definition: SystemZAsmPrinter.cpp:952

llvm::SystemZConstantPoolValue
A SystemZ-specific constant pool value.
Definition: SystemZConstantPoolValue.h:32

llvm::SystemZInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg)

llvm::SystemZInstrInfo
Definition: SystemZInstrInfo.h:185

llvm::SystemZMCExpr::create
static const SystemZMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: SystemZMCExpr.cpp:15

llvm::SystemZMCExpr::VK_SystemZ_None
@ VK_SystemZ_None
Definition: SystemZMCExpr.h:23

llvm::SystemZMCExpr::VK_SystemZ_VCon
@ VK_SystemZ_VCon
Definition: SystemZMCExpr.h:25

llvm::SystemZMCExpr::VK_SystemZ_RCon
@ VK_SystemZ_RCon
Definition: SystemZMCExpr.h:24

llvm::SystemZMCInstLower
Definition: SystemZMCInstLower.h:23

llvm::SystemZMachineFunctionInfo
Definition: SystemZMachineFunctionInfo.h:27

llvm::SystemZMachineFunctionInfo::getSpillGPRRegs
SystemZ::GPRRegs getSpillGPRRegs() const
Definition: SystemZMachineFunctionInfo.h:63

llvm::SystemZMachineFunctionInfo::getSizeOfFnParams
unsigned getSizeOfFnParams() const
Definition: SystemZMachineFunctionInfo.h:57

llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33

llvm::SystemZSubtarget::getInstrInfo
const SystemZInstrInfo * getInstrInfo() const override
Definition: SystemZSubtarget.h:76

llvm::SystemZSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition: SystemZSubtarget.h:68

llvm::SystemZTargetStreamer
Definition: SystemZTargetStreamer.h:18

llvm::SystemZTargetStreamer::MCInstSTIPair
std::pair< MCInst, const MCSubtargetInfo * > MCInstSTIPair
Definition: SystemZTargetStreamer.h:22

llvm::SystemZTargetStreamer::EXRLTargets2Sym
EXRLT2SymMap EXRLTargets2Sym
Definition: SystemZTargetStreamer.h:47

llvm::SystemZXPLINKFrameLowering
Definition: SystemZFrameLowering.h:101

llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:127

llvm::TargetMachine::getMCSubtargetInfo
const MCSubtargetInfo * getMCSubtargetInfo() const
Definition: TargetMachine.h:217

llvm::TargetMachine::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: TargetMachine.cpp:225

llvm::TargetMachine::getMCRegisterInfo
const MCRegisterInfo * getMCRegisterInfo() const
Definition: TargetMachine.h:215

llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236

llvm::Triple::isOSzOS
bool isOSzOS() const
Definition: Triple.h:515

llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81

llvm::Twine::str
std::string str() const
Return the twine contents as a std::string.
Definition: Twine.cpp:17

llvm::Twine::concat
Twine concat(const Twine &Suffix) const
Definition: Twine.h:525

llvm::Twine::utohexstr
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:416

llvm::Value::hasName
bool hasName() const
Definition: Value.h:261

llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309

llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52

uint16_t

uint32_t

uint64_t

llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143

llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486

llvm::ARM::ProfileKind::M
@ M

llvm::ConverterEBCDIC::convertToEBCDIC
std::error_code convertToEBCDIC(StringRef Source, SmallVectorImpl< char > &Result)
Definition: ConvertEBCDIC.cpp:69

llvm::ELF::SHT_PROGBITS
@ SHT_PROGBITS
Definition: ELF.h:1000

llvm::ELF::SHF_ALLOC
@ SHF_ALLOC
Definition: ELF.h:1089

llvm::M68k::MemAddrModeKind::V
@ V

llvm::SystemZCP::SystemZCPModifier
SystemZCPModifier
Definition: SystemZConstantPoolValue.h:20

llvm::SystemZCP::TLSGD
@ TLSGD
Definition: SystemZConstantPoolValue.h:21

llvm::SystemZCP::NTPOFF
@ NTPOFF
Definition: SystemZConstantPoolValue.h:24

llvm::SystemZCP::DTPOFF
@ DTPOFF
Definition: SystemZConstantPoolValue.h:23

llvm::SystemZCP::TLSLDM
@ TLSLDM
Definition: SystemZConstantPoolValue.h:22

llvm::SystemZII::MO_ADA_DATA_SYMBOL_ADDR
@ MO_ADA_DATA_SYMBOL_ADDR
Definition: SystemZInstrInfo.h:83

llvm::SystemZII::MO_ADA_DIRECT_FUNC_DESC
@ MO_ADA_DIRECT_FUNC_DESC
Definition: SystemZInstrInfo.h:85

llvm::SystemZII::MO_ADA_INDIRECT_FUNC_DESC
@ MO_ADA_INDIRECT_FUNC_DESC
Definition: SystemZInstrInfo.h:84

llvm::SystemZMC::getRegAsGR32
unsigned getRegAsGR32(unsigned Reg)
Definition: SystemZMCTargetDesc.h:65

llvm::SystemZMC::GR64Regs
const unsigned GR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:49

llvm::SystemZMC::getRegAsGRH32
unsigned getRegAsGRH32(unsigned Reg)
Definition: SystemZMCTargetDesc.h:70

llvm::SystemZMC::getRegAsVR128
unsigned getRegAsVR128(unsigned Reg)
Definition: SystemZMCTargetDesc.h:75

llvm::SystemZMC::getRegAsGR64
unsigned getRegAsGR64(unsigned Reg)
Definition: SystemZMCTargetDesc.h:60

llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462

llvm::XCOFF::NameSize
constexpr size_t NameSize
Definition: XCOFF.h:29

llvm::dwarf::Index
Index
Definition: Dwarf.h:558

llvm::jitlink::aarch64::PointerSize
constexpr uint64_t PointerSize
aarch64 pointer size.
Definition: aarch64.h:606

llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58

llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18

llvm::getTheSystemZTarget
Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14

llvm::Offset
@ Offset
Definition: DWP.cpp:440

llvm::Length
@ Length
Definition: DWP.cpp:440

llvm::AD_HLASM
@ AD_HLASM
Definition: SystemZMCAsmInfo.h:18

llvm::HexPrintStyle::Lower
@ Lower

llvm::concat
detail::concat_range< ValueT, RangeTs... > concat(RangeTs &&... Ranges)
Concatenated range across two or more ranges.
Definition: STLExtras.h:1186

llvm::ModRefInfo::LLVM_MARK_AS_BITMASK_ENUM
@ LLVM_MARK_AS_BITMASK_ENUM

llvm::MCSA_IndirectSymbol
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
Definition: MCDirectives.h:35

N
#define N

llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39

llvm::RegisterAsmPrinter
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Definition: TargetRegistry.h:1417

llvm::SystemZ::GPRRegs::LowGPR
unsigned LowGPR
Definition: SystemZMachineFunctionInfo.h:20

llvm::SystemZ::GPRRegs::HighGPR
unsigned HighGPR
Definition: SystemZMachineFunctionInfo.h:21