LLVM  15.0.0git
X86AsmParser.cpp
Go to the documentation of this file.
1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "MCTargetDesc/X86MCExpr.h"
14 #include "X86AsmParserCommon.h"
15 #include "X86Operand.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallString.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSection.h"
31 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/MC/TargetRegistry.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/SourceMgr.h"
39 #include <algorithm>
40 #include <memory>
41 
42 using namespace llvm;
43 
45  "x86-experimental-lvi-inline-asm-hardening",
46  cl::desc("Harden inline assembly code that may be vulnerable to Load Value"
47  " Injection (LVI). This feature is experimental."), cl::Hidden);
48 
49 static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
50  if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
51  ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
52  return true;
53  }
54  return false;
55 }
56 
57 namespace {
58 
59 static const char OpPrecedence[] = {
60  0, // IC_OR
61  1, // IC_XOR
62  2, // IC_AND
63  4, // IC_LSHIFT
64  4, // IC_RSHIFT
65  5, // IC_PLUS
66  5, // IC_MINUS
67  6, // IC_MULTIPLY
68  6, // IC_DIVIDE
69  6, // IC_MOD
70  7, // IC_NOT
71  8, // IC_NEG
72  9, // IC_RPAREN
73  10, // IC_LPAREN
74  0, // IC_IMM
75  0, // IC_REGISTER
76  3, // IC_EQ
77  3, // IC_NE
78  3, // IC_LT
79  3, // IC_LE
80  3, // IC_GT
81  3 // IC_GE
82 };
83 
84 class X86AsmParser : public MCTargetAsmParser {
85  ParseInstructionInfo *InstInfo;
86  bool Code16GCC;
87  unsigned ForcedDataPrefix = 0;
88 
89  enum VEXEncoding {
90  VEXEncoding_Default,
91  VEXEncoding_VEX,
92  VEXEncoding_VEX2,
93  VEXEncoding_VEX3,
94  VEXEncoding_EVEX,
95  };
96 
97  VEXEncoding ForcedVEXEncoding = VEXEncoding_Default;
98 
99  enum DispEncoding {
100  DispEncoding_Default,
101  DispEncoding_Disp8,
102  DispEncoding_Disp32,
103  };
104 
105  DispEncoding ForcedDispEncoding = DispEncoding_Default;
106 
107 private:
108  SMLoc consumeToken() {
109  MCAsmParser &Parser = getParser();
110  SMLoc Result = Parser.getTok().getLoc();
111  Parser.Lex();
112  return Result;
113  }
114 
115  X86TargetStreamer &getTargetStreamer() {
116  assert(getParser().getStreamer().getTargetStreamer() &&
117  "do not have a target streamer");
118  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
119  return static_cast<X86TargetStreamer &>(TS);
120  }
121 
122  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
123  uint64_t &ErrorInfo, FeatureBitset &MissingFeatures,
124  bool matchingInlineAsm, unsigned VariantID = 0) {
125  // In Code16GCC mode, match as 32-bit.
126  if (Code16GCC)
127  SwitchMode(X86::Is32Bit);
128  unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
129  MissingFeatures, matchingInlineAsm,
130  VariantID);
131  if (Code16GCC)
132  SwitchMode(X86::Is16Bit);
133  return rv;
134  }
135 
136  enum InfixCalculatorTok {
137  IC_OR = 0,
138  IC_XOR,
139  IC_AND,
140  IC_LSHIFT,
141  IC_RSHIFT,
142  IC_PLUS,
143  IC_MINUS,
144  IC_MULTIPLY,
145  IC_DIVIDE,
146  IC_MOD,
147  IC_NOT,
148  IC_NEG,
149  IC_RPAREN,
150  IC_LPAREN,
151  IC_IMM,
152  IC_REGISTER,
153  IC_EQ,
154  IC_NE,
155  IC_LT,
156  IC_LE,
157  IC_GT,
158  IC_GE
159  };
160 
161  enum IntelOperatorKind {
162  IOK_INVALID = 0,
163  IOK_LENGTH,
164  IOK_SIZE,
165  IOK_TYPE,
166  };
167 
168  enum MasmOperatorKind {
169  MOK_INVALID = 0,
170  MOK_LENGTHOF,
171  MOK_SIZEOF,
172  MOK_TYPE,
173  };
174 
175  class InfixCalculator {
176  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
177  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
178  SmallVector<ICToken, 4> PostfixStack;
179 
180  bool isUnaryOperator(InfixCalculatorTok Op) const {
181  return Op == IC_NEG || Op == IC_NOT;
182  }
183 
184  public:
185  int64_t popOperand() {
186  assert (!PostfixStack.empty() && "Poped an empty stack!");
187  ICToken Op = PostfixStack.pop_back_val();
188  if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
189  return -1; // The invalid Scale value will be caught later by checkScale
190  return Op.second;
191  }
192  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
193  assert ((Op == IC_IMM || Op == IC_REGISTER) &&
194  "Unexpected operand!");
195  PostfixStack.push_back(std::make_pair(Op, Val));
196  }
197 
198  void popOperator() { InfixOperatorStack.pop_back(); }
199  void pushOperator(InfixCalculatorTok Op) {
200  // Push the new operator if the stack is empty.
201  if (InfixOperatorStack.empty()) {
202  InfixOperatorStack.push_back(Op);
203  return;
204  }
205 
206  // Push the new operator if it has a higher precedence than the operator
207  // on the top of the stack or the operator on the top of the stack is a
208  // left parentheses.
209  unsigned Idx = InfixOperatorStack.size() - 1;
210  InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
211  if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
212  InfixOperatorStack.push_back(Op);
213  return;
214  }
215 
216  // The operator on the top of the stack has higher precedence than the
217  // new operator.
218  unsigned ParenCount = 0;
219  while (true) {
220  // Nothing to process.
221  if (InfixOperatorStack.empty())
222  break;
223 
224  Idx = InfixOperatorStack.size() - 1;
225  StackOp = InfixOperatorStack[Idx];
226  if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
227  break;
228 
229  // If we have an even parentheses count and we see a left parentheses,
230  // then stop processing.
231  if (!ParenCount && StackOp == IC_LPAREN)
232  break;
233 
234  if (StackOp == IC_RPAREN) {
235  ++ParenCount;
236  InfixOperatorStack.pop_back();
237  } else if (StackOp == IC_LPAREN) {
238  --ParenCount;
239  InfixOperatorStack.pop_back();
240  } else {
241  InfixOperatorStack.pop_back();
242  PostfixStack.push_back(std::make_pair(StackOp, 0));
243  }
244  }
245  // Push the new operator.
246  InfixOperatorStack.push_back(Op);
247  }
248 
249  int64_t execute() {
250  // Push any remaining operators onto the postfix stack.
251  while (!InfixOperatorStack.empty()) {
252  InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
253  if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
254  PostfixStack.push_back(std::make_pair(StackOp, 0));
255  }
256 
257  if (PostfixStack.empty())
258  return 0;
259 
260  SmallVector<ICToken, 16> OperandStack;
261  for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
262  ICToken Op = PostfixStack[i];
263  if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
264  OperandStack.push_back(Op);
265  } else if (isUnaryOperator(Op.first)) {
266  assert (OperandStack.size() > 0 && "Too few operands.");
267  ICToken Operand = OperandStack.pop_back_val();
268  assert (Operand.first == IC_IMM &&
269  "Unary operation with a register!");
270  switch (Op.first) {
271  default:
272  report_fatal_error("Unexpected operator!");
273  break;
274  case IC_NEG:
275  OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
276  break;
277  case IC_NOT:
278  OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
279  break;
280  }
281  } else {
282  assert (OperandStack.size() > 1 && "Too few operands.");
283  int64_t Val;
284  ICToken Op2 = OperandStack.pop_back_val();
285  ICToken Op1 = OperandStack.pop_back_val();
286  switch (Op.first) {
287  default:
288  report_fatal_error("Unexpected operator!");
289  break;
290  case IC_PLUS:
291  Val = Op1.second + Op2.second;
292  OperandStack.push_back(std::make_pair(IC_IMM, Val));
293  break;
294  case IC_MINUS:
295  Val = Op1.second - Op2.second;
296  OperandStack.push_back(std::make_pair(IC_IMM, Val));
297  break;
298  case IC_MULTIPLY:
299  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
300  "Multiply operation with an immediate and a register!");
301  Val = Op1.second * Op2.second;
302  OperandStack.push_back(std::make_pair(IC_IMM, Val));
303  break;
304  case IC_DIVIDE:
305  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
306  "Divide operation with an immediate and a register!");
307  assert (Op2.second != 0 && "Division by zero!");
308  Val = Op1.second / Op2.second;
309  OperandStack.push_back(std::make_pair(IC_IMM, Val));
310  break;
311  case IC_MOD:
312  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
313  "Modulo operation with an immediate and a register!");
314  Val = Op1.second % Op2.second;
315  OperandStack.push_back(std::make_pair(IC_IMM, Val));
316  break;
317  case IC_OR:
318  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
319  "Or operation with an immediate and a register!");
320  Val = Op1.second | Op2.second;
321  OperandStack.push_back(std::make_pair(IC_IMM, Val));
322  break;
323  case IC_XOR:
324  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
325  "Xor operation with an immediate and a register!");
326  Val = Op1.second ^ Op2.second;
327  OperandStack.push_back(std::make_pair(IC_IMM, Val));
328  break;
329  case IC_AND:
330  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
331  "And operation with an immediate and a register!");
332  Val = Op1.second & Op2.second;
333  OperandStack.push_back(std::make_pair(IC_IMM, Val));
334  break;
335  case IC_LSHIFT:
336  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
337  "Left shift operation with an immediate and a register!");
338  Val = Op1.second << Op2.second;
339  OperandStack.push_back(std::make_pair(IC_IMM, Val));
340  break;
341  case IC_RSHIFT:
342  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
343  "Right shift operation with an immediate and a register!");
344  Val = Op1.second >> Op2.second;
345  OperandStack.push_back(std::make_pair(IC_IMM, Val));
346  break;
347  case IC_EQ:
348  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
349  "Equals operation with an immediate and a register!");
350  Val = (Op1.second == Op2.second) ? -1 : 0;
351  OperandStack.push_back(std::make_pair(IC_IMM, Val));
352  break;
353  case IC_NE:
354  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
355  "Not-equals operation with an immediate and a register!");
356  Val = (Op1.second != Op2.second) ? -1 : 0;
357  OperandStack.push_back(std::make_pair(IC_IMM, Val));
358  break;
359  case IC_LT:
360  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
361  "Less-than operation with an immediate and a register!");
362  Val = (Op1.second < Op2.second) ? -1 : 0;
363  OperandStack.push_back(std::make_pair(IC_IMM, Val));
364  break;
365  case IC_LE:
366  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
367  "Less-than-or-equal operation with an immediate and a "
368  "register!");
369  Val = (Op1.second <= Op2.second) ? -1 : 0;
370  OperandStack.push_back(std::make_pair(IC_IMM, Val));
371  break;
372  case IC_GT:
373  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
374  "Greater-than operation with an immediate and a register!");
375  Val = (Op1.second > Op2.second) ? -1 : 0;
376  OperandStack.push_back(std::make_pair(IC_IMM, Val));
377  break;
378  case IC_GE:
379  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
380  "Greater-than-or-equal operation with an immediate and a "
381  "register!");
382  Val = (Op1.second >= Op2.second) ? -1 : 0;
383  OperandStack.push_back(std::make_pair(IC_IMM, Val));
384  break;
385  }
386  }
387  }
388  assert (OperandStack.size() == 1 && "Expected a single result.");
389  return OperandStack.pop_back_val().second;
390  }
391  };
392 
393  enum IntelExprState {
394  IES_INIT,
395  IES_OR,
396  IES_XOR,
397  IES_AND,
398  IES_EQ,
399  IES_NE,
400  IES_LT,
401  IES_LE,
402  IES_GT,
403  IES_GE,
404  IES_LSHIFT,
405  IES_RSHIFT,
406  IES_PLUS,
407  IES_MINUS,
408  IES_OFFSET,
409  IES_CAST,
410  IES_NOT,
411  IES_MULTIPLY,
412  IES_DIVIDE,
413  IES_MOD,
414  IES_LBRAC,
415  IES_RBRAC,
416  IES_LPAREN,
417  IES_RPAREN,
418  IES_REGISTER,
419  IES_INTEGER,
420  IES_IDENTIFIER,
421  IES_ERROR
422  };
423 
424  class IntelExprStateMachine {
425  IntelExprState State, PrevState;
426  unsigned BaseReg, IndexReg, TmpReg, Scale;
427  int64_t Imm;
428  const MCExpr *Sym;
429  StringRef SymName;
430  InfixCalculator IC;
432  short BracCount;
433  bool MemExpr;
434  bool OffsetOperator;
435  bool AttachToOperandIdx;
436  bool IsPIC;
437  SMLoc OffsetOperatorLoc;
438  AsmTypeInfo CurType;
439 
440  bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
441  if (Sym) {
442  ErrMsg = "cannot use more than one symbol in memory operand";
443  return true;
444  }
445  Sym = Val;
446  SymName = ID;
447  return false;
448  }
449 
450  public:
451  IntelExprStateMachine()
452  : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
453  TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
454  MemExpr(false), OffsetOperator(false), AttachToOperandIdx(false),
455  IsPIC(false) {}
456 
457  void addImm(int64_t imm) { Imm += imm; }
458  short getBracCount() const { return BracCount; }
459  bool isMemExpr() const { return MemExpr; }
460  bool isOffsetOperator() const { return OffsetOperator; }
461  SMLoc getOffsetLoc() const { return OffsetOperatorLoc; }
462  unsigned getBaseReg() const { return BaseReg; }
463  unsigned getIndexReg() const { return IndexReg; }
464  unsigned getScale() const { return Scale; }
465  const MCExpr *getSym() const { return Sym; }
466  StringRef getSymName() const { return SymName; }
467  StringRef getType() const { return CurType.Name; }
468  unsigned getSize() const { return CurType.Size; }
469  unsigned getElementSize() const { return CurType.ElementSize; }
470  unsigned getLength() const { return CurType.Length; }
471  int64_t getImm() { return Imm + IC.execute(); }
472  bool isValidEndState() const {
473  return State == IES_RBRAC || State == IES_INTEGER;
474  }
475 
476  // Is the intel expression appended after an operand index.
477  // [OperandIdx][Intel Expression]
478  // This is neccessary for checking if it is an independent
479  // intel expression at back end when parse inline asm.
480  void setAppendAfterOperand() { AttachToOperandIdx = true; }
481 
482  bool isPIC() const { return IsPIC; }
483  void setPIC() { IsPIC = true; }
484 
485  bool hadError() const { return State == IES_ERROR; }
486  const InlineAsmIdentifierInfo &getIdentifierInfo() const { return Info; }
487 
488  bool regsUseUpError(StringRef &ErrMsg) {
489  // This case mostly happen in inline asm, e.g. Arr[BaseReg + IndexReg]
490  // can not intruduce additional register in inline asm in PIC model.
491  if (IsPIC && AttachToOperandIdx)
492  ErrMsg = "Don't use 2 or more regs for mem offset in PIC model!";
493  else
494  ErrMsg = "BaseReg/IndexReg already set!";
495  return true;
496  }
497 
498  void onOr() {
499  IntelExprState CurrState = State;
500  switch (State) {
501  default:
502  State = IES_ERROR;
503  break;
504  case IES_INTEGER:
505  case IES_RPAREN:
506  case IES_REGISTER:
507  State = IES_OR;
508  IC.pushOperator(IC_OR);
509  break;
510  }
511  PrevState = CurrState;
512  }
513  void onXor() {
514  IntelExprState CurrState = State;
515  switch (State) {
516  default:
517  State = IES_ERROR;
518  break;
519  case IES_INTEGER:
520  case IES_RPAREN:
521  case IES_REGISTER:
522  State = IES_XOR;
523  IC.pushOperator(IC_XOR);
524  break;
525  }
526  PrevState = CurrState;
527  }
528  void onAnd() {
529  IntelExprState CurrState = State;
530  switch (State) {
531  default:
532  State = IES_ERROR;
533  break;
534  case IES_INTEGER:
535  case IES_RPAREN:
536  case IES_REGISTER:
537  State = IES_AND;
538  IC.pushOperator(IC_AND);
539  break;
540  }
541  PrevState = CurrState;
542  }
543  void onEq() {
544  IntelExprState CurrState = State;
545  switch (State) {
546  default:
547  State = IES_ERROR;
548  break;
549  case IES_INTEGER:
550  case IES_RPAREN:
551  case IES_REGISTER:
552  State = IES_EQ;
553  IC.pushOperator(IC_EQ);
554  break;
555  }
556  PrevState = CurrState;
557  }
558  void onNE() {
559  IntelExprState CurrState = State;
560  switch (State) {
561  default:
562  State = IES_ERROR;
563  break;
564  case IES_INTEGER:
565  case IES_RPAREN:
566  case IES_REGISTER:
567  State = IES_NE;
568  IC.pushOperator(IC_NE);
569  break;
570  }
571  PrevState = CurrState;
572  }
573  void onLT() {
574  IntelExprState CurrState = State;
575  switch (State) {
576  default:
577  State = IES_ERROR;
578  break;
579  case IES_INTEGER:
580  case IES_RPAREN:
581  case IES_REGISTER:
582  State = IES_LT;
583  IC.pushOperator(IC_LT);
584  break;
585  }
586  PrevState = CurrState;
587  }
588  void onLE() {
589  IntelExprState CurrState = State;
590  switch (State) {
591  default:
592  State = IES_ERROR;
593  break;
594  case IES_INTEGER:
595  case IES_RPAREN:
596  case IES_REGISTER:
597  State = IES_LE;
598  IC.pushOperator(IC_LE);
599  break;
600  }
601  PrevState = CurrState;
602  }
603  void onGT() {
604  IntelExprState CurrState = State;
605  switch (State) {
606  default:
607  State = IES_ERROR;
608  break;
609  case IES_INTEGER:
610  case IES_RPAREN:
611  case IES_REGISTER:
612  State = IES_GT;
613  IC.pushOperator(IC_GT);
614  break;
615  }
616  PrevState = CurrState;
617  }
618  void onGE() {
619  IntelExprState CurrState = State;
620  switch (State) {
621  default:
622  State = IES_ERROR;
623  break;
624  case IES_INTEGER:
625  case IES_RPAREN:
626  case IES_REGISTER:
627  State = IES_GE;
628  IC.pushOperator(IC_GE);
629  break;
630  }
631  PrevState = CurrState;
632  }
633  void onLShift() {
634  IntelExprState CurrState = State;
635  switch (State) {
636  default:
637  State = IES_ERROR;
638  break;
639  case IES_INTEGER:
640  case IES_RPAREN:
641  case IES_REGISTER:
642  State = IES_LSHIFT;
643  IC.pushOperator(IC_LSHIFT);
644  break;
645  }
646  PrevState = CurrState;
647  }
648  void onRShift() {
649  IntelExprState CurrState = State;
650  switch (State) {
651  default:
652  State = IES_ERROR;
653  break;
654  case IES_INTEGER:
655  case IES_RPAREN:
656  case IES_REGISTER:
657  State = IES_RSHIFT;
658  IC.pushOperator(IC_RSHIFT);
659  break;
660  }
661  PrevState = CurrState;
662  }
663  bool onPlus(StringRef &ErrMsg) {
664  IntelExprState CurrState = State;
665  switch (State) {
666  default:
667  State = IES_ERROR;
668  break;
669  case IES_INTEGER:
670  case IES_RPAREN:
671  case IES_REGISTER:
672  case IES_OFFSET:
673  State = IES_PLUS;
674  IC.pushOperator(IC_PLUS);
675  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
676  // If we already have a BaseReg, then assume this is the IndexReg with
677  // no explicit scale.
678  if (!BaseReg) {
679  BaseReg = TmpReg;
680  } else {
681  if (IndexReg)
682  return regsUseUpError(ErrMsg);
683  IndexReg = TmpReg;
684  Scale = 0;
685  }
686  }
687  break;
688  }
689  PrevState = CurrState;
690  return false;
691  }
692  bool onMinus(StringRef &ErrMsg) {
693  IntelExprState CurrState = State;
694  switch (State) {
695  default:
696  State = IES_ERROR;
697  break;
698  case IES_OR:
699  case IES_XOR:
700  case IES_AND:
701  case IES_EQ:
702  case IES_NE:
703  case IES_LT:
704  case IES_LE:
705  case IES_GT:
706  case IES_GE:
707  case IES_LSHIFT:
708  case IES_RSHIFT:
709  case IES_PLUS:
710  case IES_NOT:
711  case IES_MULTIPLY:
712  case IES_DIVIDE:
713  case IES_MOD:
714  case IES_LPAREN:
715  case IES_RPAREN:
716  case IES_LBRAC:
717  case IES_RBRAC:
718  case IES_INTEGER:
719  case IES_REGISTER:
720  case IES_INIT:
721  case IES_OFFSET:
722  State = IES_MINUS;
723  // push minus operator if it is not a negate operator
724  if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
725  CurrState == IES_INTEGER || CurrState == IES_RBRAC ||
726  CurrState == IES_OFFSET)
727  IC.pushOperator(IC_MINUS);
728  else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
729  // We have negate operator for Scale: it's illegal
730  ErrMsg = "Scale can't be negative";
731  return true;
732  } else
733  IC.pushOperator(IC_NEG);
734  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
735  // If we already have a BaseReg, then assume this is the IndexReg with
736  // no explicit scale.
737  if (!BaseReg) {
738  BaseReg = TmpReg;
739  } else {
740  if (IndexReg)
741  return regsUseUpError(ErrMsg);
742  IndexReg = TmpReg;
743  Scale = 0;
744  }
745  }
746  break;
747  }
748  PrevState = CurrState;
749  return false;
750  }
751  void onNot() {
752  IntelExprState CurrState = State;
753  switch (State) {
754  default:
755  State = IES_ERROR;
756  break;
757  case IES_OR:
758  case IES_XOR:
759  case IES_AND:
760  case IES_EQ:
761  case IES_NE:
762  case IES_LT:
763  case IES_LE:
764  case IES_GT:
765  case IES_GE:
766  case IES_LSHIFT:
767  case IES_RSHIFT:
768  case IES_PLUS:
769  case IES_MINUS:
770  case IES_NOT:
771  case IES_MULTIPLY:
772  case IES_DIVIDE:
773  case IES_MOD:
774  case IES_LPAREN:
775  case IES_LBRAC:
776  case IES_INIT:
777  State = IES_NOT;
778  IC.pushOperator(IC_NOT);
779  break;
780  }
781  PrevState = CurrState;
782  }
783  bool onRegister(unsigned Reg, StringRef &ErrMsg) {
784  IntelExprState CurrState = State;
785  switch (State) {
786  default:
787  State = IES_ERROR;
788  break;
789  case IES_PLUS:
790  case IES_LPAREN:
791  case IES_LBRAC:
792  State = IES_REGISTER;
793  TmpReg = Reg;
794  IC.pushOperand(IC_REGISTER);
795  break;
796  case IES_MULTIPLY:
797  // Index Register - Scale * Register
798  if (PrevState == IES_INTEGER) {
799  if (IndexReg)
800  return regsUseUpError(ErrMsg);
801  State = IES_REGISTER;
802  IndexReg = Reg;
803  // Get the scale and replace the 'Scale * Register' with '0'.
804  Scale = IC.popOperand();
805  if (checkScale(Scale, ErrMsg))
806  return true;
807  IC.pushOperand(IC_IMM);
808  IC.popOperator();
809  } else {
810  State = IES_ERROR;
811  }
812  break;
813  }
814  PrevState = CurrState;
815  return false;
816  }
817  bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
818  const InlineAsmIdentifierInfo &IDInfo,
819  const AsmTypeInfo &Type, bool ParsingMSInlineAsm,
820  StringRef &ErrMsg) {
821  // InlineAsm: Treat an enum value as an integer
822  if (ParsingMSInlineAsm)
824  return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
825  // Treat a symbolic constant like an integer
826  if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
827  return onInteger(CE->getValue(), ErrMsg);
828  PrevState = State;
829  switch (State) {
830  default:
831  State = IES_ERROR;
832  break;
833  case IES_CAST:
834  case IES_PLUS:
835  case IES_MINUS:
836  case IES_NOT:
837  case IES_INIT:
838  case IES_LBRAC:
839  case IES_LPAREN:
840  if (setSymRef(SymRef, SymRefName, ErrMsg))
841  return true;
842  MemExpr = true;
843  State = IES_INTEGER;
844  IC.pushOperand(IC_IMM);
845  if (ParsingMSInlineAsm)
846  Info = IDInfo;
847  setTypeInfo(Type);
848  break;
849  }
850  return false;
851  }
852  bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
853  IntelExprState CurrState = State;
854  switch (State) {
855  default:
856  State = IES_ERROR;
857  break;
858  case IES_PLUS:
859  case IES_MINUS:
860  case IES_NOT:
861  case IES_OR:
862  case IES_XOR:
863  case IES_AND:
864  case IES_EQ:
865  case IES_NE:
866  case IES_LT:
867  case IES_LE:
868  case IES_GT:
869  case IES_GE:
870  case IES_LSHIFT:
871  case IES_RSHIFT:
872  case IES_DIVIDE:
873  case IES_MOD:
874  case IES_MULTIPLY:
875  case IES_LPAREN:
876  case IES_INIT:
877  case IES_LBRAC:
878  State = IES_INTEGER;
879  if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
880  // Index Register - Register * Scale
881  if (IndexReg)
882  return regsUseUpError(ErrMsg);
883  IndexReg = TmpReg;
884  Scale = TmpInt;
885  if (checkScale(Scale, ErrMsg))
886  return true;
887  // Get the scale and replace the 'Register * Scale' with '0'.
888  IC.popOperator();
889  } else {
890  IC.pushOperand(IC_IMM, TmpInt);
891  }
892  break;
893  }
894  PrevState = CurrState;
895  return false;
896  }
897  void onStar() {
898  PrevState = State;
899  switch (State) {
900  default:
901  State = IES_ERROR;
902  break;
903  case IES_INTEGER:
904  case IES_REGISTER:
905  case IES_RPAREN:
906  State = IES_MULTIPLY;
907  IC.pushOperator(IC_MULTIPLY);
908  break;
909  }
910  }
911  void onDivide() {
912  PrevState = State;
913  switch (State) {
914  default:
915  State = IES_ERROR;
916  break;
917  case IES_INTEGER:
918  case IES_RPAREN:
919  State = IES_DIVIDE;
920  IC.pushOperator(IC_DIVIDE);
921  break;
922  }
923  }
924  void onMod() {
925  PrevState = State;
926  switch (State) {
927  default:
928  State = IES_ERROR;
929  break;
930  case IES_INTEGER:
931  case IES_RPAREN:
932  State = IES_MOD;
933  IC.pushOperator(IC_MOD);
934  break;
935  }
936  }
937  bool onLBrac() {
938  if (BracCount)
939  return true;
940  PrevState = State;
941  switch (State) {
942  default:
943  State = IES_ERROR;
944  break;
945  case IES_RBRAC:
946  case IES_INTEGER:
947  case IES_RPAREN:
948  State = IES_PLUS;
949  IC.pushOperator(IC_PLUS);
950  CurType.Length = 1;
951  CurType.Size = CurType.ElementSize;
952  break;
953  case IES_INIT:
954  case IES_CAST:
955  assert(!BracCount && "BracCount should be zero on parsing's start");
956  State = IES_LBRAC;
957  break;
958  }
959  MemExpr = true;
960  BracCount++;
961  return false;
962  }
963  bool onRBrac(StringRef &ErrMsg) {
964  IntelExprState CurrState = State;
965  switch (State) {
966  default:
967  State = IES_ERROR;
968  break;
969  case IES_INTEGER:
970  case IES_OFFSET:
971  case IES_REGISTER:
972  case IES_RPAREN:
973  if (BracCount-- != 1) {
974  ErrMsg = "unexpected bracket encountered";
975  return true;
976  }
977  State = IES_RBRAC;
978  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
979  // If we already have a BaseReg, then assume this is the IndexReg with
980  // no explicit scale.
981  if (!BaseReg) {
982  BaseReg = TmpReg;
983  } else {
984  if (IndexReg)
985  return regsUseUpError(ErrMsg);
986  IndexReg = TmpReg;
987  Scale = 0;
988  }
989  }
990  break;
991  }
992  PrevState = CurrState;
993  return false;
994  }
995  void onLParen() {
996  IntelExprState CurrState = State;
997  switch (State) {
998  default:
999  State = IES_ERROR;
1000  break;
1001  case IES_PLUS:
1002  case IES_MINUS:
1003  case IES_NOT:
1004  case IES_OR:
1005  case IES_XOR:
1006  case IES_AND:
1007  case IES_EQ:
1008  case IES_NE:
1009  case IES_LT:
1010  case IES_LE:
1011  case IES_GT:
1012  case IES_GE:
1013  case IES_LSHIFT:
1014  case IES_RSHIFT:
1015  case IES_MULTIPLY:
1016  case IES_DIVIDE:
1017  case IES_MOD:
1018  case IES_LPAREN:
1019  case IES_INIT:
1020  case IES_LBRAC:
1021  State = IES_LPAREN;
1022  IC.pushOperator(IC_LPAREN);
1023  break;
1024  }
1025  PrevState = CurrState;
1026  }
1027  void onRParen() {
1028  PrevState = State;
1029  switch (State) {
1030  default:
1031  State = IES_ERROR;
1032  break;
1033  case IES_INTEGER:
1034  case IES_OFFSET:
1035  case IES_REGISTER:
1036  case IES_RBRAC:
1037  case IES_RPAREN:
1038  State = IES_RPAREN;
1039  IC.pushOperator(IC_RPAREN);
1040  break;
1041  }
1042  }
1043  bool onOffset(const MCExpr *Val, SMLoc OffsetLoc, StringRef ID,
1044  const InlineAsmIdentifierInfo &IDInfo,
1045  bool ParsingMSInlineAsm, StringRef &ErrMsg) {
1046  PrevState = State;
1047  switch (State) {
1048  default:
1049  ErrMsg = "unexpected offset operator expression";
1050  return true;
1051  case IES_PLUS:
1052  case IES_INIT:
1053  case IES_LBRAC:
1054  if (setSymRef(Val, ID, ErrMsg))
1055  return true;
1056  OffsetOperator = true;
1057  OffsetOperatorLoc = OffsetLoc;
1058  State = IES_OFFSET;
1059  // As we cannot yet resolve the actual value (offset), we retain
1060  // the requested semantics by pushing a '0' to the operands stack
1061  IC.pushOperand(IC_IMM);
1062  if (ParsingMSInlineAsm) {
1063  Info = IDInfo;
1064  }
1065  break;
1066  }
1067  return false;
1068  }
1069  void onCast(AsmTypeInfo Info) {
1070  PrevState = State;
1071  switch (State) {
1072  default:
1073  State = IES_ERROR;
1074  break;
1075  case IES_LPAREN:
1076  setTypeInfo(Info);
1077  State = IES_CAST;
1078  break;
1079  }
1080  }
1081  void setTypeInfo(AsmTypeInfo Type) { CurType = Type; }
1082  };
1083 
1084  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
1085  bool MatchingInlineAsm = false) {
1086  MCAsmParser &Parser = getParser();
1087  if (MatchingInlineAsm) {
1088  if (!getLexer().isAtStartOfStatement())
1089  Parser.eatToEndOfStatement();
1090  return false;
1091  }
1092  return Parser.Error(L, Msg, Range);
1093  }
1094 
1095  bool MatchRegisterByName(unsigned &RegNo, StringRef RegName, SMLoc StartLoc,
1096  SMLoc EndLoc);
1097  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
1098  bool RestoreOnFailure);
1099 
1100  std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
1101  std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
1102  bool IsSIReg(unsigned Reg);
1103  unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1104  void
1105  AddDefaultSrcDestOperands(OperandVector &Operands,
1106  std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1107  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
1108  bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
1109  OperandVector &FinalOperands);
1110  bool parseOperand(OperandVector &Operands, StringRef Name);
1111  bool parseATTOperand(OperandVector &Operands);
1112  bool parseIntelOperand(OperandVector &Operands, StringRef Name);
1113  bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
1115  bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
1116  unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
1117  unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
1118  unsigned IdentifyMasmOperator(StringRef Name);
1119  bool ParseMasmOperator(unsigned OpKind, int64_t &Val);
1120  bool ParseRoundingModeOp(SMLoc Start, OperandVector &Operands);
1121  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1122  bool &ParseError, SMLoc &End);
1123  bool ParseMasmNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1124  bool &ParseError, SMLoc &End);
1125  void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
1126  SMLoc End);
1127  bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
1128  bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
1130  bool IsUnevaluatedOperand, SMLoc &End,
1131  bool IsParsingOffsetOperator = false);
1132  void tryParseOperandIdx(AsmToken::TokenKind PrevTK,
1133  IntelExprStateMachine &SM);
1134 
1135  bool ParseMemOperand(unsigned SegReg, const MCExpr *Disp, SMLoc StartLoc,
1136  SMLoc EndLoc, OperandVector &Operands);
1137 
1138  X86::CondCode ParseConditionCode(StringRef CCode);
1139 
1140  bool ParseIntelMemoryOperandSize(unsigned &Size);
1141  bool CreateMemForMSInlineAsm(unsigned SegReg, const MCExpr *Disp,
1142  unsigned BaseReg, unsigned IndexReg,
1143  unsigned Scale, SMLoc Start, SMLoc End,
1144  unsigned Size, StringRef Identifier,
1147 
1148  bool parseDirectiveArch();
1149  bool parseDirectiveNops(SMLoc L);
1150  bool parseDirectiveEven(SMLoc L);
1151  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
1152 
1153  /// CodeView FPO data directives.
1154  bool parseDirectiveFPOProc(SMLoc L);
1155  bool parseDirectiveFPOSetFrame(SMLoc L);
1156  bool parseDirectiveFPOPushReg(SMLoc L);
1157  bool parseDirectiveFPOStackAlloc(SMLoc L);
1158  bool parseDirectiveFPOStackAlign(SMLoc L);
1159  bool parseDirectiveFPOEndPrologue(SMLoc L);
1160  bool parseDirectiveFPOEndProc(SMLoc L);
1161 
1162  /// SEH directives.
1163  bool parseSEHRegisterNumber(unsigned RegClassID, unsigned &RegNo);
1164  bool parseDirectiveSEHPushReg(SMLoc);
1165  bool parseDirectiveSEHSetFrame(SMLoc);
1166  bool parseDirectiveSEHSaveReg(SMLoc);
1167  bool parseDirectiveSEHSaveXMM(SMLoc);
1168  bool parseDirectiveSEHPushFrame(SMLoc);
1169 
1170  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1171 
1172  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
1173  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
1174 
1175  // Load Value Injection (LVI) Mitigations for machine code
1176  void emitWarningForSpecialLVIInstruction(SMLoc Loc);
1177  void applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out);
1178  void applyLVILoadHardeningMitigation(MCInst &Inst, MCStreamer &Out);
1179 
1180  /// Wrapper around MCStreamer::emitInstruction(). Possibly adds
1181  /// instrumentation around Inst.
1182  void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
1183 
1184  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1187  bool MatchingInlineAsm) override;
1188 
1189  void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
1190  MCStreamer &Out, bool MatchingInlineAsm);
1191 
1192  bool ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures,
1193  bool MatchingInlineAsm);
1194 
1195  bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
1198  bool MatchingInlineAsm);
1199 
1200  bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
1203  bool MatchingInlineAsm);
1204 
1205  bool OmitRegisterFromClobberLists(unsigned RegNo) override;
1206 
1207  /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
1208  /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
1209  /// return false if no parsing errors occurred, true otherwise.
1210  bool HandleAVX512Operand(OperandVector &Operands);
1211 
1212  bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
1213 
1214  bool is64BitMode() const {
1215  // FIXME: Can tablegen auto-generate this?
1216  return getSTI().getFeatureBits()[X86::Is64Bit];
1217  }
1218  bool is32BitMode() const {
1219  // FIXME: Can tablegen auto-generate this?
1220  return getSTI().getFeatureBits()[X86::Is32Bit];
1221  }
1222  bool is16BitMode() const {
1223  // FIXME: Can tablegen auto-generate this?
1224  return getSTI().getFeatureBits()[X86::Is16Bit];
1225  }
1226  void SwitchMode(unsigned mode) {
1227  MCSubtargetInfo &STI = copySTI();
1228  FeatureBitset AllModes({X86::Is64Bit, X86::Is32Bit, X86::Is16Bit});
1229  FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
1230  FeatureBitset FB = ComputeAvailableFeatures(
1231  STI.ToggleFeature(OldMode.flip(mode)));
1232  setAvailableFeatures(FB);
1233 
1234  assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
1235  }
1236 
1237  unsigned getPointerWidth() {
1238  if (is16BitMode()) return 16;
1239  if (is32BitMode()) return 32;
1240  if (is64BitMode()) return 64;
1241  llvm_unreachable("invalid mode");
1242  }
1243 
1244  bool isParsingIntelSyntax() {
1245  return getParser().getAssemblerDialect();
1246  }
1247 
1248  /// @name Auto-generated Matcher Functions
1249  /// {
1250 
1251 #define GET_ASSEMBLER_HEADER
1252 #include "X86GenAsmMatcher.inc"
1253 
1254  /// }
1255 
1256 public:
1257  enum X86MatchResultTy {
1258  Match_Unsupported = FIRST_TARGET_MATCH_RESULT_TY,
1259 #define GET_OPERAND_DIAGNOSTIC_TYPES
1260 #include "X86GenAsmMatcher.inc"
1261  };
1262 
1263  X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
1264  const MCInstrInfo &mii, const MCTargetOptions &Options)
1265  : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
1266  Code16GCC(false) {
1267 
1268  Parser.addAliasForDirective(".word", ".2byte");
1269 
1270  // Initialize the set of available features.
1271  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
1272  }
1273 
1274  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
1275  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1276  SMLoc &EndLoc) override;
1277 
1278  bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
1279 
1280  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1281  SMLoc NameLoc, OperandVector &Operands) override;
1282 
1283  bool ParseDirective(AsmToken DirectiveID) override;
1284 };
1285 } // end anonymous namespace
1286 
1287 /// @name Auto-generated Match Functions
1288 /// {
1289 
1290 static unsigned MatchRegisterName(StringRef Name);
1291 
1292 /// }
1293 
1294 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
1295  unsigned Scale, bool Is64BitMode,
1296  StringRef &ErrMsg) {
1297  // If we have both a base register and an index register make sure they are
1298  // both 64-bit or 32-bit registers.
1299  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1300 
1301  if (BaseReg != 0 &&
1302  !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
1303  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||
1304  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||
1305  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {
1306  ErrMsg = "invalid base+index expression";
1307  return true;
1308  }
1309 
1310  if (IndexReg != 0 &&
1311  !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1312  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1313  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1314  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1315  X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1316  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1317  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
1318  ErrMsg = "invalid base+index expression";
1319  return true;
1320  }
1321 
1322  if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1323  IndexReg == X86::EIP || IndexReg == X86::RIP ||
1324  IndexReg == X86::ESP || IndexReg == X86::RSP) {
1325  ErrMsg = "invalid base+index expression";
1326  return true;
1327  }
1328 
1329  // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1330  // and then only in non-64-bit modes.
1331  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1332  (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1333  BaseReg != X86::SI && BaseReg != X86::DI))) {
1334  ErrMsg = "invalid 16-bit base register";
1335  return true;
1336  }
1337 
1338  if (BaseReg == 0 &&
1339  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1340  ErrMsg = "16-bit memory operand may not include only index register";
1341  return true;
1342  }
1343 
1344  if (BaseReg != 0 && IndexReg != 0) {
1345  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1346  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1347  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1348  IndexReg == X86::EIZ)) {
1349  ErrMsg = "base register is 64-bit, but index register is not";
1350  return true;
1351  }
1352  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1353  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1354  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1355  IndexReg == X86::RIZ)) {
1356  ErrMsg = "base register is 32-bit, but index register is not";
1357  return true;
1358  }
1359  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
1360  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1361  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1362  ErrMsg = "base register is 16-bit, but index register is not";
1363  return true;
1364  }
1365  if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1366  (IndexReg != X86::SI && IndexReg != X86::DI)) {
1367  ErrMsg = "invalid 16-bit base/index register combination";
1368  return true;
1369  }
1370  }
1371  }
1372 
1373  // RIP/EIP-relative addressing is only supported in 64-bit mode.
1374  if (!Is64BitMode && BaseReg != 0 &&
1375  (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1376  ErrMsg = "IP-relative addressing requires 64-bit mode";
1377  return true;
1378  }
1379 
1380  return checkScale(Scale, ErrMsg);
1381 }
1382 
1383 bool X86AsmParser::MatchRegisterByName(unsigned &RegNo, StringRef RegName,
1384  SMLoc StartLoc, SMLoc EndLoc) {
1385  // If we encounter a %, ignore it. This code handles registers with and
1386  // without the prefix, unprefixed registers can occur in cfi directives.
1387  RegName.consume_front("%");
1388 
1389  RegNo = MatchRegisterName(RegName);
1390 
1391  // If the match failed, try the register name as lowercase.
1392  if (RegNo == 0)
1393  RegNo = MatchRegisterName(RegName.lower());
1394 
1395  // The "flags" and "mxcsr" registers cannot be referenced directly.
1396  // Treat it as an identifier instead.
1397  if (isParsingMSInlineAsm() && isParsingIntelSyntax() &&
1398  (RegNo == X86::EFLAGS || RegNo == X86::MXCSR))
1399  RegNo = 0;
1400 
1401  if (!is64BitMode()) {
1402  // FIXME: This should be done using Requires<Not64BitMode> and
1403  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1404  // checked.
1405  if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1406  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1408  X86II::isX86_64ExtendedReg(RegNo)) {
1409  return Error(StartLoc,
1410  "register %" + RegName + " is only available in 64-bit mode",
1411  SMRange(StartLoc, EndLoc));
1412  }
1413  }
1414 
1415  // If this is "db[0-15]", match it as an alias
1416  // for dr[0-15].
1417  if (RegNo == 0 && RegName.startswith("db")) {
1418  if (RegName.size() == 3) {
1419  switch (RegName[2]) {
1420  case '0':
1421  RegNo = X86::DR0;
1422  break;
1423  case '1':
1424  RegNo = X86::DR1;
1425  break;
1426  case '2':
1427  RegNo = X86::DR2;
1428  break;
1429  case '3':
1430  RegNo = X86::DR3;
1431  break;
1432  case '4':
1433  RegNo = X86::DR4;
1434  break;
1435  case '5':
1436  RegNo = X86::DR5;
1437  break;
1438  case '6':
1439  RegNo = X86::DR6;
1440  break;
1441  case '7':
1442  RegNo = X86::DR7;
1443  break;
1444  case '8':
1445  RegNo = X86::DR8;
1446  break;
1447  case '9':
1448  RegNo = X86::DR9;
1449  break;
1450  }
1451  } else if (RegName.size() == 4 && RegName[2] == '1') {
1452  switch (RegName[3]) {
1453  case '0':
1454  RegNo = X86::DR10;
1455  break;
1456  case '1':
1457  RegNo = X86::DR11;
1458  break;
1459  case '2':
1460  RegNo = X86::DR12;
1461  break;
1462  case '3':
1463  RegNo = X86::DR13;
1464  break;
1465  case '4':
1466  RegNo = X86::DR14;
1467  break;
1468  case '5':
1469  RegNo = X86::DR15;
1470  break;
1471  }
1472  }
1473  }
1474 
1475  if (RegNo == 0) {
1476  if (isParsingIntelSyntax())
1477  return true;
1478  return Error(StartLoc, "invalid register name", SMRange(StartLoc, EndLoc));
1479  }
1480  return false;
1481 }
1482 
1483 bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1484  SMLoc &EndLoc, bool RestoreOnFailure) {
1485  MCAsmParser &Parser = getParser();
1486  MCAsmLexer &Lexer = getLexer();
1487  RegNo = 0;
1488 
1489  SmallVector<AsmToken, 5> Tokens;
1490  auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() {
1491  if (RestoreOnFailure) {
1492  while (!Tokens.empty()) {
1493  Lexer.UnLex(Tokens.pop_back_val());
1494  }
1495  }
1496  };
1497 
1498  const AsmToken &PercentTok = Parser.getTok();
1499  StartLoc = PercentTok.getLoc();
1500 
1501  // If we encounter a %, ignore it. This code handles registers with and
1502  // without the prefix, unprefixed registers can occur in cfi directives.
1503  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent)) {
1504  Tokens.push_back(PercentTok);
1505  Parser.Lex(); // Eat percent token.
1506  }
1507 
1508  const AsmToken &Tok = Parser.getTok();
1509  EndLoc = Tok.getEndLoc();
1510 
1511  if (Tok.isNot(AsmToken::Identifier)) {
1512  OnFailure();
1513  if (isParsingIntelSyntax()) return true;
1514  return Error(StartLoc, "invalid register name",
1515  SMRange(StartLoc, EndLoc));
1516  }
1517 
1518  if (MatchRegisterByName(RegNo, Tok.getString(), StartLoc, EndLoc)) {
1519  OnFailure();
1520  return true;
1521  }
1522 
1523  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1524  if (RegNo == X86::ST0) {
1525  Tokens.push_back(Tok);
1526  Parser.Lex(); // Eat 'st'
1527 
1528  // Check to see if we have '(4)' after %st.
1529  if (Lexer.isNot(AsmToken::LParen))
1530  return false;
1531  // Lex the paren.
1532  Tokens.push_back(Parser.getTok());
1533  Parser.Lex();
1534 
1535  const AsmToken &IntTok = Parser.getTok();
1536  if (IntTok.isNot(AsmToken::Integer)) {
1537  OnFailure();
1538  return Error(IntTok.getLoc(), "expected stack index");
1539  }
1540  switch (IntTok.getIntVal()) {
1541  case 0: RegNo = X86::ST0; break;
1542  case 1: RegNo = X86::ST1; break;
1543  case 2: RegNo = X86::ST2; break;
1544  case 3: RegNo = X86::ST3; break;
1545  case 4: RegNo = X86::ST4; break;
1546  case 5: RegNo = X86::ST5; break;
1547  case 6: RegNo = X86::ST6; break;
1548  case 7: RegNo = X86::ST7; break;
1549  default:
1550  OnFailure();
1551  return Error(IntTok.getLoc(), "invalid stack index");
1552  }
1553 
1554  // Lex IntTok
1555  Tokens.push_back(IntTok);
1556  Parser.Lex();
1557  if (Lexer.isNot(AsmToken::RParen)) {
1558  OnFailure();
1559  return Error(Parser.getTok().getLoc(), "expected ')'");
1560  }
1561 
1562  EndLoc = Parser.getTok().getEndLoc();
1563  Parser.Lex(); // Eat ')'
1564  return false;
1565  }
1566 
1567  EndLoc = Parser.getTok().getEndLoc();
1568 
1569  if (RegNo == 0) {
1570  OnFailure();
1571  if (isParsingIntelSyntax()) return true;
1572  return Error(StartLoc, "invalid register name",
1573  SMRange(StartLoc, EndLoc));
1574  }
1575 
1576  Parser.Lex(); // Eat identifier token.
1577  return false;
1578 }
1579 
1580 bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1581  SMLoc &EndLoc) {
1582  return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1583 }
1584 
1585 OperandMatchResultTy X86AsmParser::tryParseRegister(unsigned &RegNo,
1586  SMLoc &StartLoc,
1587  SMLoc &EndLoc) {
1588  bool Result =
1589  ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1590  bool PendingErrors = getParser().hasPendingError();
1591  getParser().clearPendingErrors();
1592  if (PendingErrors)
1593  return MatchOperand_ParseFail;
1594  if (Result)
1595  return MatchOperand_NoMatch;
1596  return MatchOperand_Success;
1597 }
1598 
1599 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1600  bool Parse32 = is32BitMode() || Code16GCC;
1601  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1602  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1603  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1604  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1605  Loc, Loc, 0);
1606 }
1607 
1608 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1609  bool Parse32 = is32BitMode() || Code16GCC;
1610  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1611  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1612  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1613  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1614  Loc, Loc, 0);
1615 }
1616 
1617 bool X86AsmParser::IsSIReg(unsigned Reg) {
1618  switch (Reg) {
1619  default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1620  case X86::RSI:
1621  case X86::ESI:
1622  case X86::SI:
1623  return true;
1624  case X86::RDI:
1625  case X86::EDI:
1626  case X86::DI:
1627  return false;
1628  }
1629 }
1630 
1631 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1632  bool IsSIReg) {
1633  switch (RegClassID) {
1634  default: llvm_unreachable("Unexpected register class");
1635  case X86::GR64RegClassID:
1636  return IsSIReg ? X86::RSI : X86::RDI;
1637  case X86::GR32RegClassID:
1638  return IsSIReg ? X86::ESI : X86::EDI;
1639  case X86::GR16RegClassID:
1640  return IsSIReg ? X86::SI : X86::DI;
1641  }
1642 }
1643 
1644 void X86AsmParser::AddDefaultSrcDestOperands(
1645  OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1646  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1647  if (isParsingIntelSyntax()) {
1648  Operands.push_back(std::move(Dst));
1649  Operands.push_back(std::move(Src));
1650  }
1651  else {
1652  Operands.push_back(std::move(Src));
1653  Operands.push_back(std::move(Dst));
1654  }
1655 }
1656 
1657 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1658  OperandVector &FinalOperands) {
1659 
1660  if (OrigOperands.size() > 1) {
1661  // Check if sizes match, OrigOperands also contains the instruction name
1662  assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1663  "Operand size mismatch");
1664 
1666  // Verify types match
1667  int RegClassID = -1;
1668  for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1669  X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1670  X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1671 
1672  if (FinalOp.isReg() &&
1673  (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1674  // Return false and let a normal complaint about bogus operands happen
1675  return false;
1676 
1677  if (FinalOp.isMem()) {
1678 
1679  if (!OrigOp.isMem())
1680  // Return false and let a normal complaint about bogus operands happen
1681  return false;
1682 
1683  unsigned OrigReg = OrigOp.Mem.BaseReg;
1684  unsigned FinalReg = FinalOp.Mem.BaseReg;
1685 
1686  // If we've already encounterd a register class, make sure all register
1687  // bases are of the same register class
1688  if (RegClassID != -1 &&
1689  !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1690  return Error(OrigOp.getStartLoc(),
1691  "mismatching source and destination index registers");
1692  }
1693 
1694  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1695  RegClassID = X86::GR64RegClassID;
1696  else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1697  RegClassID = X86::GR32RegClassID;
1698  else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1699  RegClassID = X86::GR16RegClassID;
1700  else
1701  // Unexpected register class type
1702  // Return false and let a normal complaint about bogus operands happen
1703  return false;
1704 
1705  bool IsSI = IsSIReg(FinalReg);
1706  FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1707 
1708  if (FinalReg != OrigReg) {
1709  std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1710  Warnings.push_back(std::make_pair(
1711  OrigOp.getStartLoc(),
1712  "memory operand is only for determining the size, " + RegName +
1713  " will be used for the location"));
1714  }
1715 
1716  FinalOp.Mem.Size = OrigOp.Mem.Size;
1717  FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1718  FinalOp.Mem.BaseReg = FinalReg;
1719  }
1720  }
1721 
1722  // Produce warnings only if all the operands passed the adjustment - prevent
1723  // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1724  for (auto &WarningMsg : Warnings) {
1725  Warning(WarningMsg.first, WarningMsg.second);
1726  }
1727 
1728  // Remove old operands
1729  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1730  OrigOperands.pop_back();
1731  }
1732  // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1733  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1734  OrigOperands.push_back(std::move(FinalOperands[i]));
1735 
1736  return false;
1737 }
1738 
1739 bool X86AsmParser::parseOperand(OperandVector &Operands, StringRef Name) {
1740  if (isParsingIntelSyntax())
1741  return parseIntelOperand(Operands, Name);
1742 
1743  return parseATTOperand(Operands);
1744 }
1745 
1746 bool X86AsmParser::CreateMemForMSInlineAsm(
1747  unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1748  unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
1750  // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1751  // some other label reference.
1753  // Insert an explicit size if the user didn't have one.
1754  if (!Size) {
1755  Size = getPointerWidth();
1756  InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1757  /*Len=*/0, Size);
1758  }
1759  // Create an absolute memory reference in order to match against
1760  // instructions taking a PC relative operand.
1761  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
1762  End, Size, Identifier,
1763  Info.Label.Decl));
1764  return false;
1765  }
1766  // We either have a direct symbol reference, or an offset from a symbol. The
1767  // parser always puts the symbol on the LHS, so look there for size
1768  // calculation purposes.
1769  unsigned FrontendSize = 0;
1770  void *Decl = nullptr;
1771  bool IsGlobalLV = false;
1772  if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
1773  // Size is in terms of bits in this context.
1774  FrontendSize = Info.Var.Type * 8;
1775  Decl = Info.Var.Decl;
1776  IsGlobalLV = Info.Var.IsGlobalLV;
1777  }
1778  // It is widely common for MS InlineAsm to use a global variable and one/two
1779  // registers in a mmory expression, and though unaccessible via rip/eip.
1780  if (IsGlobalLV && (BaseReg || IndexReg)) {
1781  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
1782  End, Size, Identifier, Decl, 0,
1783  BaseReg && IndexReg));
1784  return false;
1785  }
1786  // Otherwise, we set the base register to a non-zero value
1787  // if we don't know the actual value at this time. This is necessary to
1788  // get the matching correct in some cases.
1789  BaseReg = BaseReg ? BaseReg : 1;
1790  Operands.push_back(X86Operand::CreateMem(
1791  getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
1792  Size,
1793  /*DefaultBaseReg=*/X86::RIP, Identifier, Decl, FrontendSize));
1794  return false;
1795 }
1796 
1797 // Some binary bitwise operators have a named synonymous
1798 // Query a candidate string for being such a named operator
1799 // and if so - invoke the appropriate handler
1800 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
1801  IntelExprStateMachine &SM,
1802  bool &ParseError, SMLoc &End) {
1803  // A named operator should be either lower or upper case, but not a mix...
1804  // except in MASM, which uses full case-insensitivity.
1805  if (Name.compare(Name.lower()) && Name.compare(Name.upper()) &&
1806  !getParser().isParsingMasm())
1807  return false;
1808  if (Name.equals_insensitive("not")) {
1809  SM.onNot();
1810  } else if (Name.equals_insensitive("or")) {
1811  SM.onOr();
1812  } else if (Name.equals_insensitive("shl")) {
1813  SM.onLShift();
1814  } else if (Name.equals_insensitive("shr")) {
1815  SM.onRShift();
1816  } else if (Name.equals_insensitive("xor")) {
1817  SM.onXor();
1818  } else if (Name.equals_insensitive("and")) {
1819  SM.onAnd();
1820  } else if (Name.equals_insensitive("mod")) {
1821  SM.onMod();
1822  } else if (Name.equals_insensitive("offset")) {
1823  SMLoc OffsetLoc = getTok().getLoc();
1824  const MCExpr *Val = nullptr;
1825  StringRef ID;
1827  ParseError = ParseIntelOffsetOperator(Val, ID, Info, End);
1828  if (ParseError)
1829  return true;
1830  StringRef ErrMsg;
1831  ParseError =
1832  SM.onOffset(Val, OffsetLoc, ID, Info, isParsingMSInlineAsm(), ErrMsg);
1833  if (ParseError)
1834  return Error(SMLoc::getFromPointer(Name.data()), ErrMsg);
1835  } else {
1836  return false;
1837  }
1838  if (!Name.equals_insensitive("offset"))
1839  End = consumeToken();
1840  return true;
1841 }
1842 bool X86AsmParser::ParseMasmNamedOperator(StringRef Name,
1843  IntelExprStateMachine &SM,
1844  bool &ParseError, SMLoc &End) {
1845  if (Name.equals_insensitive("eq")) {
1846  SM.onEq();
1847  } else if (Name.equals_insensitive("ne")) {
1848  SM.onNE();
1849  } else if (Name.equals_insensitive("lt")) {
1850  SM.onLT();
1851  } else if (Name.equals_insensitive("le")) {
1852  SM.onLE();
1853  } else if (Name.equals_insensitive("gt")) {
1854  SM.onGT();
1855  } else if (Name.equals_insensitive("ge")) {
1856  SM.onGE();
1857  } else {
1858  return false;
1859  }
1860  End = consumeToken();
1861  return true;
1862 }
1863 
1864 // Check if current intel expression append after an operand.
1865 // Like: [Operand][Intel Expression]
1866 void X86AsmParser::tryParseOperandIdx(AsmToken::TokenKind PrevTK,
1867  IntelExprStateMachine &SM) {
1868  if (PrevTK != AsmToken::RBrac)
1869  return;
1870 
1871  SM.setAppendAfterOperand();
1872 }
1873 
1874 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1875  MCAsmParser &Parser = getParser();
1876  StringRef ErrMsg;
1877 
1879 
1880  if (getContext().getObjectFileInfo()->isPositionIndependent())
1881  SM.setPIC();
1882 
1883  bool Done = false;
1884  while (!Done) {
1885  // Get a fresh reference on each loop iteration in case the previous
1886  // iteration moved the token storage during UnLex().
1887  const AsmToken &Tok = Parser.getTok();
1888 
1889  bool UpdateLocLex = true;
1890  AsmToken::TokenKind TK = getLexer().getKind();
1891 
1892  switch (TK) {
1893  default:
1894  if ((Done = SM.isValidEndState()))
1895  break;
1896  return Error(Tok.getLoc(), "unknown token in expression");
1897  case AsmToken::Error:
1898  return Error(getLexer().getErrLoc(), getLexer().getErr());
1899  break;
1901  Done = true;
1902  break;
1903  case AsmToken::Real:
1904  // DotOperator: [ebx].0
1905  UpdateLocLex = false;
1906  if (ParseIntelDotOperator(SM, End))
1907  return true;
1908  break;
1909  case AsmToken::Dot:
1910  if (!Parser.isParsingMasm()) {
1911  if ((Done = SM.isValidEndState()))
1912  break;
1913  return Error(Tok.getLoc(), "unknown token in expression");
1914  }
1915  // MASM allows spaces around the dot operator (e.g., "var . x")
1916  Lex();
1917  UpdateLocLex = false;
1918  if (ParseIntelDotOperator(SM, End))
1919  return true;
1920  break;
1921  case AsmToken::Dollar:
1922  if (!Parser.isParsingMasm()) {
1923  if ((Done = SM.isValidEndState()))
1924  break;
1925  return Error(Tok.getLoc(), "unknown token in expression");
1926  }
1928  case AsmToken::String: {
1929  if (Parser.isParsingMasm()) {
1930  // MASM parsers handle strings in expressions as constants.
1931  SMLoc ValueLoc = Tok.getLoc();
1932  int64_t Res;
1933  const MCExpr *Val;
1934  if (Parser.parsePrimaryExpr(Val, End, nullptr))
1935  return true;
1936  UpdateLocLex = false;
1937  if (!Val->evaluateAsAbsolute(Res, getStreamer().getAssemblerPtr()))
1938  return Error(ValueLoc, "expected absolute value");
1939  if (SM.onInteger(Res, ErrMsg))
1940  return Error(ValueLoc, ErrMsg);
1941  break;
1942  }
1944  }
1945  case AsmToken::At:
1946  case AsmToken::Identifier: {
1947  SMLoc IdentLoc = Tok.getLoc();
1948  StringRef Identifier = Tok.getString();
1949  UpdateLocLex = false;
1950  if (Parser.isParsingMasm()) {
1951  size_t DotOffset = Identifier.find_first_of('.');
1952  if (DotOffset != StringRef::npos) {
1953  consumeToken();
1954  StringRef LHS = Identifier.slice(0, DotOffset);
1955  StringRef Dot = Identifier.slice(DotOffset, DotOffset + 1);
1956  StringRef RHS = Identifier.slice(DotOffset + 1, StringRef::npos);
1957  if (!RHS.empty()) {
1958  getLexer().UnLex(AsmToken(AsmToken::Identifier, RHS));
1959  }
1960  getLexer().UnLex(AsmToken(AsmToken::Dot, Dot));
1961  if (!LHS.empty()) {
1962  getLexer().UnLex(AsmToken(AsmToken::Identifier, LHS));
1963  }
1964  break;
1965  }
1966  }
1967  // (MASM only) <TYPE> PTR operator
1968  if (Parser.isParsingMasm()) {
1969  const AsmToken &NextTok = getLexer().peekTok();
1970  if (NextTok.is(AsmToken::Identifier) &&
1971  NextTok.getIdentifier().equals_insensitive("ptr")) {
1972  AsmTypeInfo Info;
1973  if (Parser.lookUpType(Identifier, Info))
1974  return Error(Tok.getLoc(), "unknown type");
1975  SM.onCast(Info);
1976  // Eat type and PTR.
1977  consumeToken();
1978  End = consumeToken();
1979  break;
1980  }
1981  }
1982  // Register, or (MASM only) <register>.<field>
1983  unsigned Reg;
1984  if (Tok.is(AsmToken::Identifier)) {
1985  if (!ParseRegister(Reg, IdentLoc, End, /*RestoreOnFailure=*/true)) {
1986  if (SM.onRegister(Reg, ErrMsg))
1987  return Error(IdentLoc, ErrMsg);
1988  break;
1989  }
1990  if (Parser.isParsingMasm()) {
1991  const std::pair<StringRef, StringRef> IDField =
1992  Tok.getString().split('.');
1993  const StringRef ID = IDField.first, Field = IDField.second;
1994  SMLoc IDEndLoc = SMLoc::getFromPointer(ID.data() + ID.size());
1995  if (!Field.empty() &&
1996  !MatchRegisterByName(Reg, ID, IdentLoc, IDEndLoc)) {
1997  if (SM.onRegister(Reg, ErrMsg))
1998  return Error(IdentLoc, ErrMsg);
1999 
2001  SMLoc FieldStartLoc = SMLoc::getFromPointer(Field.data());
2002  if (Parser.lookUpField(Field, Info))
2003  return Error(FieldStartLoc, "unknown offset");
2004  else if (SM.onPlus(ErrMsg))
2005  return Error(getTok().getLoc(), ErrMsg);
2006  else if (SM.onInteger(Info.Offset, ErrMsg))
2007  return Error(IdentLoc, ErrMsg);
2008  SM.setTypeInfo(Info.Type);
2009 
2010  End = consumeToken();
2011  break;
2012  }
2013  }
2014  }
2015  // Operator synonymous ("not", "or" etc.)
2016  bool ParseError = false;
2017  if (ParseIntelNamedOperator(Identifier, SM, ParseError, End)) {
2018  if (ParseError)
2019  return true;
2020  break;
2021  }
2022  if (Parser.isParsingMasm() &&
2023  ParseMasmNamedOperator(Identifier, SM, ParseError, End)) {
2024  if (ParseError)
2025  return true;
2026  break;
2027  }
2028  // Symbol reference, when parsing assembly content
2030  AsmFieldInfo FieldInfo;
2031  const MCExpr *Val;
2032  if (isParsingMSInlineAsm() || Parser.isParsingMasm()) {
2033  // MS Dot Operator expression
2034  if (Identifier.count('.') &&
2035  (PrevTK == AsmToken::RBrac || PrevTK == AsmToken::RParen)) {
2036  if (ParseIntelDotOperator(SM, End))
2037  return true;
2038  break;
2039  }
2040  }
2041  if (isParsingMSInlineAsm()) {
2042  // MS InlineAsm operators (TYPE/LENGTH/SIZE)
2043  if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
2044  if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
2045  if (SM.onInteger(Val, ErrMsg))
2046  return Error(IdentLoc, ErrMsg);
2047  } else {
2048  return true;
2049  }
2050  break;
2051  }
2052  // MS InlineAsm identifier
2053  // Call parseIdentifier() to combine @ with the identifier behind it.
2054  if (TK == AsmToken::At && Parser.parseIdentifier(Identifier))
2055  return Error(IdentLoc, "expected identifier");
2056  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
2057  return true;
2058  else if (SM.onIdentifierExpr(Val, Identifier, Info, FieldInfo.Type,
2059  true, ErrMsg))
2060  return Error(IdentLoc, ErrMsg);
2061  break;
2062  }
2063  if (Parser.isParsingMasm()) {
2064  if (unsigned OpKind = IdentifyMasmOperator(Identifier)) {
2065  int64_t Val;
2066  if (ParseMasmOperator(OpKind, Val))
2067  return true;
2068  if (SM.onInteger(Val, ErrMsg))
2069  return Error(IdentLoc, ErrMsg);
2070  break;
2071  }
2072  if (!getParser().lookUpType(Identifier, FieldInfo.Type)) {
2073  // Field offset immediate; <TYPE>.<field specification>
2074  Lex(); // eat type
2075  bool EndDot = parseOptionalToken(AsmToken::Dot);
2076  while (EndDot || (getTok().is(AsmToken::Identifier) &&
2077  getTok().getString().startswith("."))) {
2078  getParser().parseIdentifier(Identifier);
2079  if (!EndDot)
2080  Identifier.consume_front(".");
2081  EndDot = Identifier.consume_back(".");
2082  if (getParser().lookUpField(FieldInfo.Type.Name, Identifier,
2083  FieldInfo)) {
2084  SMLoc IDEnd =
2085  SMLoc::getFromPointer(Identifier.data() + Identifier.size());
2086  return Error(IdentLoc, "Unable to lookup field reference!",
2087  SMRange(IdentLoc, IDEnd));
2088  }
2089  if (!EndDot)
2090  EndDot = parseOptionalToken(AsmToken::Dot);
2091  }
2092  if (SM.onInteger(FieldInfo.Offset, ErrMsg))
2093  return Error(IdentLoc, ErrMsg);
2094  break;
2095  }
2096  }
2097  if (getParser().parsePrimaryExpr(Val, End, &FieldInfo.Type)) {
2098  return Error(Tok.getLoc(), "Unexpected identifier!");
2099  } else if (SM.onIdentifierExpr(Val, Identifier, Info, FieldInfo.Type,
2100  false, ErrMsg)) {
2101  return Error(IdentLoc, ErrMsg);
2102  }
2103  break;
2104  }
2105  case AsmToken::Integer: {
2106  // Look for 'b' or 'f' following an Integer as a directional label
2107  SMLoc Loc = getTok().getLoc();
2108  int64_t IntVal = getTok().getIntVal();
2109  End = consumeToken();
2110  UpdateLocLex = false;
2111  if (getLexer().getKind() == AsmToken::Identifier) {
2112  StringRef IDVal = getTok().getString();
2113  if (IDVal == "f" || IDVal == "b") {
2114  MCSymbol *Sym =
2115  getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
2117  const MCExpr *Val =
2118  MCSymbolRefExpr::create(Sym, Variant, getContext());
2119  if (IDVal == "b" && Sym->isUndefined())
2120  return Error(Loc, "invalid reference to undefined symbol");
2121  StringRef Identifier = Sym->getName();
2123  AsmTypeInfo Type;
2124  if (SM.onIdentifierExpr(Val, Identifier, Info, Type,
2125  isParsingMSInlineAsm(), ErrMsg))
2126  return Error(Loc, ErrMsg);
2127  End = consumeToken();
2128  } else {
2129  if (SM.onInteger(IntVal, ErrMsg))
2130  return Error(Loc, ErrMsg);
2131  }
2132  } else {
2133  if (SM.onInteger(IntVal, ErrMsg))
2134  return Error(Loc, ErrMsg);
2135  }
2136  break;
2137  }
2138  case AsmToken::Plus:
2139  if (SM.onPlus(ErrMsg))
2140  return Error(getTok().getLoc(), ErrMsg);
2141  break;
2142  case AsmToken::Minus:
2143  if (SM.onMinus(ErrMsg))
2144  return Error(getTok().getLoc(), ErrMsg);
2145  break;
2146  case AsmToken::Tilde: SM.onNot(); break;
2147  case AsmToken::Star: SM.onStar(); break;
2148  case AsmToken::Slash: SM.onDivide(); break;
2149  case AsmToken::Percent: SM.onMod(); break;
2150  case AsmToken::Pipe: SM.onOr(); break;
2151  case AsmToken::Caret: SM.onXor(); break;
2152  case AsmToken::Amp: SM.onAnd(); break;
2153  case AsmToken::LessLess:
2154  SM.onLShift(); break;
2156  SM.onRShift(); break;
2157  case AsmToken::LBrac:
2158  if (SM.onLBrac())
2159  return Error(Tok.getLoc(), "unexpected bracket encountered");
2160  tryParseOperandIdx(PrevTK, SM);
2161  break;
2162  case AsmToken::RBrac:
2163  if (SM.onRBrac(ErrMsg)) {
2164  return Error(Tok.getLoc(), ErrMsg);
2165  }
2166  break;
2167  case AsmToken::LParen: SM.onLParen(); break;
2168  case AsmToken::RParen: SM.onRParen(); break;
2169  }
2170  if (SM.hadError())
2171  return Error(Tok.getLoc(), "unknown token in expression");
2172 
2173  if (!Done && UpdateLocLex)
2174  End = consumeToken();
2175 
2176  PrevTK = TK;
2177  }
2178  return false;
2179 }
2180 
2181 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
2182  SMLoc Start, SMLoc End) {
2183  SMLoc Loc = Start;
2184  unsigned ExprLen = End.getPointer() - Start.getPointer();
2185  // Skip everything before a symbol displacement (if we have one)
2186  if (SM.getSym() && !SM.isOffsetOperator()) {
2187  StringRef SymName = SM.getSymName();
2188  if (unsigned Len = SymName.data() - Start.getPointer())
2189  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
2190  Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
2191  ExprLen = End.getPointer() - (SymName.data() + SymName.size());
2192  // If we have only a symbol than there's no need for complex rewrite,
2193  // simply skip everything after it
2194  if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
2195  if (ExprLen)
2196  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
2197  return;
2198  }
2199  }
2200  // Build an Intel Expression rewrite
2201  StringRef BaseRegStr;
2202  StringRef IndexRegStr;
2203  StringRef OffsetNameStr;
2204  if (SM.getBaseReg())
2205  BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
2206  if (SM.getIndexReg())
2207  IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
2208  if (SM.isOffsetOperator())
2209  OffsetNameStr = SM.getSymName();
2210  // Emit it
2211  IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), OffsetNameStr,
2212  SM.getImm(), SM.isMemExpr());
2213  InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
2214 }
2215 
2216 // Inline assembly may use variable names with namespace alias qualifiers.
2217 bool X86AsmParser::ParseIntelInlineAsmIdentifier(
2218  const MCExpr *&Val, StringRef &Identifier, InlineAsmIdentifierInfo &Info,
2219  bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator) {
2220  MCAsmParser &Parser = getParser();
2221  assert(isParsingMSInlineAsm() && "Expected to be parsing inline assembly.");
2222  Val = nullptr;
2223 
2224  StringRef LineBuf(Identifier.data());
2225  SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
2226 
2227  const AsmToken &Tok = Parser.getTok();
2228  SMLoc Loc = Tok.getLoc();
2229 
2230  // Advance the token stream until the end of the current token is
2231  // after the end of what the frontend claimed.
2232  const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
2233  do {
2234  End = Tok.getEndLoc();
2235  getLexer().Lex();
2236  } while (End.getPointer() < EndPtr);
2237  Identifier = LineBuf;
2238 
2239  // The frontend should end parsing on an assembler token boundary, unless it
2240  // failed parsing.
2241  assert((End.getPointer() == EndPtr ||
2243  "frontend claimed part of a token?");
2244 
2245  // If the identifier lookup was unsuccessful, assume that we are dealing with
2246  // a label.
2248  StringRef InternalName =
2249  SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
2250  Loc, false);
2251  assert(InternalName.size() && "We should have an internal name here.");
2252  // Push a rewrite for replacing the identifier name with the internal name,
2253  // unless we are parsing the operand of an offset operator
2254  if (!IsParsingOffsetOperator)
2255  InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
2256  InternalName);
2257  else
2258  Identifier = InternalName;
2259  } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
2260  return false;
2261  // Create the symbol reference.
2262  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
2264  Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
2265  return false;
2266 }
2267 
2268 //ParseRoundingModeOp - Parse AVX-512 rounding mode operand
2269 bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
2270  MCAsmParser &Parser = getParser();
2271  const AsmToken &Tok = Parser.getTok();
2272  // Eat "{" and mark the current place.
2273  const SMLoc consumedToken = consumeToken();
2274  if (Tok.isNot(AsmToken::Identifier))
2275  return Error(Tok.getLoc(), "Expected an identifier after {");
2276  if (Tok.getIdentifier().startswith("r")){
2277  int rndMode = StringSwitch<int>(Tok.getIdentifier())
2282  .Default(-1);
2283  if (-1 == rndMode)
2284  return Error(Tok.getLoc(), "Invalid rounding mode.");
2285  Parser.Lex(); // Eat "r*" of r*-sae
2286  if (!getLexer().is(AsmToken::Minus))
2287  return Error(Tok.getLoc(), "Expected - at this point");
2288  Parser.Lex(); // Eat "-"
2289  Parser.Lex(); // Eat the sae
2290  if (!getLexer().is(AsmToken::RCurly))
2291  return Error(Tok.getLoc(), "Expected } at this point");
2292  SMLoc End = Tok.getEndLoc();
2293  Parser.Lex(); // Eat "}"
2294  const MCExpr *RndModeOp =
2295  MCConstantExpr::create(rndMode, Parser.getContext());
2296  Operands.push_back(X86Operand::CreateImm(RndModeOp, Start, End));
2297  return false;
2298  }
2299  if(Tok.getIdentifier().equals("sae")){
2300  Parser.Lex(); // Eat the sae
2301  if (!getLexer().is(AsmToken::RCurly))
2302  return Error(Tok.getLoc(), "Expected } at this point");
2303  Parser.Lex(); // Eat "}"
2304  Operands.push_back(X86Operand::CreateToken("{sae}", consumedToken));
2305  return false;
2306  }
2307  return Error(Tok.getLoc(), "unknown token in expression");
2308 }
2309 
2310 /// Parse the '.' operator.
2311 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
2312  SMLoc &End) {
2313  const AsmToken &Tok = getTok();
2315 
2316  // Drop the optional '.'.
2317  StringRef DotDispStr = Tok.getString();
2318  if (DotDispStr.startswith("."))
2319  DotDispStr = DotDispStr.drop_front(1);
2320  StringRef TrailingDot;
2321 
2322  // .Imm gets lexed as a real.
2323  if (Tok.is(AsmToken::Real)) {
2324  APInt DotDisp;
2325  DotDispStr.getAsInteger(10, DotDisp);
2326  Info.Offset = DotDisp.getZExtValue();
2327  } else if ((isParsingMSInlineAsm() || getParser().isParsingMasm()) &&
2328  Tok.is(AsmToken::Identifier)) {
2329  if (DotDispStr.endswith(".")) {
2330  TrailingDot = DotDispStr.substr(DotDispStr.size() - 1);
2331  DotDispStr = DotDispStr.drop_back(1);
2332  }
2333  const std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
2334  const StringRef Base = BaseMember.first, Member = BaseMember.second;
2335  if (getParser().lookUpField(SM.getType(), DotDispStr, Info) &&
2336  getParser().lookUpField(SM.getSymName(), DotDispStr, Info) &&
2337  getParser().lookUpField(DotDispStr, Info) &&
2338  (!SemaCallback ||
2339  SemaCallback->LookupInlineAsmField(Base, Member, Info.Offset)))
2340  return Error(Tok.getLoc(), "Unable to lookup field reference!");
2341  } else {
2342  return Error(Tok.getLoc(), "Unexpected token type!");
2343  }
2344 
2345  // Eat the DotExpression and update End
2346  End = SMLoc::getFromPointer(DotDispStr.data());
2347  const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
2348  while (Tok.getLoc().getPointer() < DotExprEndLoc)
2349  Lex();
2350  if (!TrailingDot.empty())
2351  getLexer().UnLex(AsmToken(AsmToken::Dot, TrailingDot));
2352  SM.addImm(Info.Offset);
2353  SM.setTypeInfo(Info.Type);
2354  return false;
2355 }
2356 
2357 /// Parse the 'offset' operator.
2358 /// This operator is used to specify the location of a given operand
2359 bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
2361  SMLoc &End) {
2362  // Eat offset, mark start of identifier.
2363  SMLoc Start = Lex().getLoc();
2364  ID = getTok().getString();
2365  if (!isParsingMSInlineAsm()) {
2366  if ((getTok().isNot(AsmToken::Identifier) &&
2367  getTok().isNot(AsmToken::String)) ||
2368  getParser().parsePrimaryExpr(Val, End, nullptr))
2369  return Error(Start, "unexpected token!");
2370  } else if (ParseIntelInlineAsmIdentifier(Val, ID, Info, false, End, true)) {
2371  return Error(Start, "unable to lookup expression");
2372  } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) {
2373  return Error(Start, "offset operator cannot yet handle constants");
2374  }
2375  return false;
2376 }
2377 
2378 // Query a candidate string for being an Intel assembly operator
2379 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
2380 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
2382  .Cases("TYPE","type",IOK_TYPE)
2383  .Cases("SIZE","size",IOK_SIZE)
2384  .Cases("LENGTH","length",IOK_LENGTH)
2385  .Default(IOK_INVALID);
2386 }
2387 
2388 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
2389 /// returns the number of elements in an array. It returns the value 1 for
2390 /// non-array variables. The SIZE operator returns the size of a C or C++
2391 /// variable. A variable's size is the product of its LENGTH and TYPE. The
2392 /// TYPE operator returns the size of a C or C++ type or variable. If the
2393 /// variable is an array, TYPE returns the size of a single element.
2394 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
2395  MCAsmParser &Parser = getParser();
2396  const AsmToken &Tok = Parser.getTok();
2397  Parser.Lex(); // Eat operator.
2398 
2399  const MCExpr *Val = nullptr;
2401  SMLoc Start = Tok.getLoc(), End;
2402  StringRef Identifier = Tok.getString();
2403  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
2404  /*IsUnevaluatedOperand=*/true, End))
2405  return 0;
2406 
2407  if (!Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
2408  Error(Start, "unable to lookup expression");
2409  return 0;
2410  }
2411 
2412  unsigned CVal = 0;
2413  switch(OpKind) {
2414  default: llvm_unreachable("Unexpected operand kind!");
2415  case IOK_LENGTH: CVal = Info.Var.Length; break;
2416  case IOK_SIZE: CVal = Info.Var.Size; break;
2417  case IOK_TYPE: CVal = Info.Var.Type; break;
2418  }
2419 
2420  return CVal;
2421 }
2422 
2423 // Query a candidate string for being an Intel assembly operator
2424 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
2425 unsigned X86AsmParser::IdentifyMasmOperator(StringRef Name) {
2426  return StringSwitch<unsigned>(Name.lower())
2427  .Case("type", MOK_TYPE)
2428  .Cases("size", "sizeof", MOK_SIZEOF)
2429  .Cases("length", "lengthof", MOK_LENGTHOF)
2430  .Default(MOK_INVALID);
2431 }
2432 
2433 /// Parse the 'LENGTHOF', 'SIZEOF', and 'TYPE' operators. The LENGTHOF operator
2434 /// returns the number of elements in an array. It returns the value 1 for
2435 /// non-array variables. The SIZEOF operator returns the size of a type or
2436 /// variable in bytes. A variable's size is the product of its LENGTH and TYPE.
2437 /// The TYPE operator returns the size of a variable. If the variable is an
2438 /// array, TYPE returns the size of a single element.
2439 bool X86AsmParser::ParseMasmOperator(unsigned OpKind, int64_t &Val) {
2440  MCAsmParser &Parser = getParser();
2441  SMLoc OpLoc = Parser.getTok().getLoc();
2442  Parser.Lex(); // Eat operator.
2443 
2444  Val = 0;
2445  if (OpKind == MOK_SIZEOF || OpKind == MOK_TYPE) {
2446  // Check for SIZEOF(<type>) and TYPE(<type>).
2447  bool InParens = Parser.getTok().is(AsmToken::LParen);
2448  const AsmToken &IDTok = InParens ? getLexer().peekTok() : Parser.getTok();
2449  AsmTypeInfo Type;
2450  if (IDTok.is(AsmToken::Identifier) &&
2451  !Parser.lookUpType(IDTok.getIdentifier(), Type)) {
2452  Val = Type.Size;
2453 
2454  // Eat tokens.
2455  if (InParens)
2456  parseToken(AsmToken::LParen);
2457  parseToken(AsmToken::Identifier);
2458  if (InParens)
2459  parseToken(AsmToken::RParen);
2460  }
2461  }
2462 
2463  if (!Val) {
2464  IntelExprStateMachine SM;
2465  SMLoc End, Start = Parser.getTok().getLoc();
2466  if (ParseIntelExpression(SM, End))
2467  return true;
2468 
2469  switch (OpKind) {
2470  default:
2471  llvm_unreachable("Unexpected operand kind!");
2472  case MOK_SIZEOF:
2473  Val = SM.getSize();
2474  break;
2475  case MOK_LENGTHOF:
2476  Val = SM.getLength();
2477  break;
2478  case MOK_TYPE:
2479  Val = SM.getElementSize();
2480  break;
2481  }
2482 
2483  if (!Val)
2484  return Error(OpLoc, "expression has unknown type", SMRange(Start, End));
2485  }
2486 
2487  return false;
2488 }
2489 
2490 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
2491  Size = StringSwitch<unsigned>(getTok().getString())
2492  .Cases("BYTE", "byte", 8)
2493  .Cases("WORD", "word", 16)
2494  .Cases("DWORD", "dword", 32)
2495  .Cases("FLOAT", "float", 32)
2496  .Cases("LONG", "long", 32)
2497  .Cases("FWORD", "fword", 48)
2498  .Cases("DOUBLE", "double", 64)
2499  .Cases("QWORD", "qword", 64)
2500  .Cases("MMWORD","mmword", 64)
2501  .Cases("XWORD", "xword", 80)
2502  .Cases("TBYTE", "tbyte", 80)
2503  .Cases("XMMWORD", "xmmword", 128)
2504  .Cases("YMMWORD", "ymmword", 256)
2505  .Cases("ZMMWORD", "zmmword", 512)
2506  .Default(0);
2507  if (Size) {
2508  const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
2509  if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
2510  return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
2511  Lex(); // Eat ptr.
2512  }
2513  return false;
2514 }
2515 
2516 bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) {
2517  MCAsmParser &Parser = getParser();
2518  const AsmToken &Tok = Parser.getTok();
2519  SMLoc Start, End;
2520 
2521  // Parse optional Size directive.
2522  unsigned Size;
2523  if (ParseIntelMemoryOperandSize(Size))
2524  return true;
2525  bool PtrInOperand = bool(Size);
2526 
2527  Start = Tok.getLoc();
2528 
2529  // Rounding mode operand.
2530  if (getLexer().is(AsmToken::LCurly))
2531  return ParseRoundingModeOp(Start, Operands);
2532 
2533  // Register operand.
2534  unsigned RegNo = 0;
2535  if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
2536  if (RegNo == X86::RIP)
2537  return Error(Start, "rip can only be used as a base register");
2538  // A Register followed by ':' is considered a segment override
2539  if (Tok.isNot(AsmToken::Colon)) {
2540  if (PtrInOperand)
2541  return Error(Start, "expected memory operand after 'ptr', "
2542  "found register operand instead");
2543  Operands.push_back(X86Operand::CreateReg(RegNo, Start, End));
2544  return false;
2545  }
2546  // An alleged segment override. check if we have a valid segment register
2547  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
2548  return Error(Start, "invalid segment register");
2549  // Eat ':' and update Start location
2550  Start = Lex().getLoc();
2551  }
2552 
2553  // Immediates and Memory
2554  IntelExprStateMachine SM;
2555  if (ParseIntelExpression(SM, End))
2556  return true;
2557 
2558  if (isParsingMSInlineAsm())
2559  RewriteIntelExpression(SM, Start, Tok.getLoc());
2560 
2561  int64_t Imm = SM.getImm();
2562  const MCExpr *Disp = SM.getSym();
2563  const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
2564  if (Disp && Imm)
2565  Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
2566  if (!Disp)
2567  Disp = ImmDisp;
2568 
2569  // RegNo != 0 specifies a valid segment register,
2570  // and we are parsing a segment override
2571  if (!SM.isMemExpr() && !RegNo) {
2572  if (isParsingMSInlineAsm() && SM.isOffsetOperator()) {
2573  const InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
2574  if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
2575  // Disp includes the address of a variable; make sure this is recorded
2576  // for later handling.
2577  Operands.push_back(X86Operand::CreateImm(Disp, Start, End,
2578  SM.getSymName(), Info.Var.Decl,
2579  Info.Var.IsGlobalLV));
2580  return false;
2581  }
2582  }
2583 
2584  Operands.push_back(X86Operand::CreateImm(Disp, Start, End));
2585  return false;
2586  }
2587 
2588  StringRef ErrMsg;
2589  unsigned BaseReg = SM.getBaseReg();
2590  unsigned IndexReg = SM.getIndexReg();
2591  if (IndexReg && BaseReg == X86::RIP)
2592  BaseReg = 0;
2593  unsigned Scale = SM.getScale();
2594  if (!PtrInOperand)
2595  Size = SM.getElementSize() << 3;
2596 
2597  if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
2598  (IndexReg == X86::ESP || IndexReg == X86::RSP))
2599  std::swap(BaseReg, IndexReg);
2600 
2601  // If BaseReg is a vector register and IndexReg is not, swap them unless
2602  // Scale was specified in which case it would be an error.
2603  if (Scale == 0 &&
2604  !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
2605  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
2606  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
2607  (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
2608  X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
2609  X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
2610  std::swap(BaseReg, IndexReg);
2611 
2612  if (Scale != 0 &&
2613  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
2614  return Error(Start, "16-bit addresses cannot have a scale");
2615 
2616  // If there was no explicit scale specified, change it to 1.
2617  if (Scale == 0)
2618  Scale = 1;
2619 
2620  // If this is a 16-bit addressing mode with the base and index in the wrong
2621  // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
2622  // shared with att syntax where order matters.
2623  if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
2624  (IndexReg == X86::BX || IndexReg == X86::BP))
2625  std::swap(BaseReg, IndexReg);
2626 
2627  if ((BaseReg || IndexReg) &&
2628  CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2629  ErrMsg))
2630  return Error(Start, ErrMsg);
2631  if (isParsingMSInlineAsm())
2632  return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale, Start,
2633  End, Size, SM.getSymName(),
2634  SM.getIdentifierInfo(), Operands);
2635 
2636  // When parsing x64 MS-style assembly, all non-absolute references to a named
2637  // variable default to RIP-relative.
2638  unsigned DefaultBaseReg = X86::NoRegister;
2639  bool MaybeDirectBranchDest = true;
2640 
2641  if (Parser.isParsingMasm()) {
2642  bool IsUnconditionalBranch =
2643  Name.equals_insensitive("jmp") || Name.equals_insensitive("call");
2644  if (is64BitMode() && SM.getElementSize() > 0) {
2645  DefaultBaseReg = X86::RIP;
2646  }
2647  if (IsUnconditionalBranch) {
2648  if (PtrInOperand) {
2649  MaybeDirectBranchDest = false;
2650  if (is64BitMode())
2651  DefaultBaseReg = X86::RIP;
2652  } else if (!BaseReg && !IndexReg && Disp &&
2653  Disp->getKind() == MCExpr::SymbolRef) {
2654  if (is64BitMode()) {
2655  if (SM.getSize() == 8) {
2656  MaybeDirectBranchDest = false;
2657  DefaultBaseReg = X86::RIP;
2658  }
2659  } else {
2660  if (SM.getSize() == 4 || SM.getSize() == 2)
2661  MaybeDirectBranchDest = false;
2662  }
2663  }
2664  }
2665  }
2666 
2667  if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))
2668  Operands.push_back(X86Operand::CreateMem(
2669  getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,
2670  Size, DefaultBaseReg, /*SymName=*/StringRef(), /*OpDecl=*/nullptr,
2671  /*FrontendSize=*/0, /*UseUpRegs=*/false, MaybeDirectBranchDest));
2672  else
2673  Operands.push_back(X86Operand::CreateMem(
2674  getPointerWidth(), Disp, Start, End, Size, /*SymName=*/StringRef(),
2675  /*OpDecl=*/nullptr, /*FrontendSize=*/0, /*UseUpRegs=*/false,
2676  MaybeDirectBranchDest));
2677  return false;
2678 }
2679 
2680 bool X86AsmParser::parseATTOperand(OperandVector &Operands) {
2681  MCAsmParser &Parser = getParser();
2682  switch (getLexer().getKind()) {
2683  case AsmToken::Dollar: {
2684  // $42 or $ID -> immediate.
2685  SMLoc Start = Parser.getTok().getLoc(), End;
2686  Parser.Lex();
2687  const MCExpr *Val;
2688  // This is an immediate, so we should not parse a register. Do a precheck
2689  // for '%' to supercede intra-register parse errors.
2690  SMLoc L = Parser.getTok().getLoc();
2691  if (check(getLexer().is(AsmToken::Percent), L,
2692  "expected immediate expression") ||
2693  getParser().parseExpression(Val, End) ||
2694  check(isa<X86MCExpr>(Val), L, "expected immediate expression"))
2695  return true;
2696  Operands.push_back(X86Operand::CreateImm(Val, Start, End));
2697  return false;
2698  }
2699  case AsmToken::LCurly: {
2700  SMLoc Start = Parser.getTok().getLoc();
2701  return ParseRoundingModeOp(Start, Operands);
2702  }
2703  default: {
2704  // This a memory operand or a register. We have some parsing complications
2705  // as a '(' may be part of an immediate expression or the addressing mode
2706  // block. This is complicated by the fact that an assembler-level variable
2707  // may refer either to a register or an immediate expression.
2708 
2709  SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
2710  const MCExpr *Expr = nullptr;
2711  unsigned Reg = 0;
2712  if (getLexer().isNot(AsmToken::LParen)) {
2713  // No '(' so this is either a displacement expression or a register.
2714  if (Parser.parseExpression(Expr, EndLoc))
2715  return true;
2716  if (auto *RE = dyn_cast<X86MCExpr>(Expr)) {
2717  // Segment Register. Reset Expr and copy value to register.
2718  Expr = nullptr;
2719  Reg = RE->getRegNo();
2720 
2721  // Check the register.
2722  if (Reg == X86::EIZ || Reg == X86::RIZ)
2723  return Error(
2724  Loc, "%eiz and %riz can only be used as index registers",
2725  SMRange(Loc, EndLoc));
2726  if (Reg == X86::RIP)
2727  return Error(Loc, "%rip can only be used as a base register",
2728  SMRange(Loc, EndLoc));
2729  // Return register that are not segment prefixes immediately.
2730  if (!Parser.parseOptionalToken(AsmToken::Colon)) {
2731  Operands.push_back(X86Operand::CreateReg(Reg, Loc, EndLoc));
2732  return false;
2733  }
2734  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
2735  return Error(Loc, "invalid segment register");
2736  // Accept a '*' absolute memory reference after the segment. Place it
2737  // before the full memory operand.
2738  if (getLexer().is(AsmToken::Star))
2739  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2740  }
2741  }
2742  // This is a Memory operand.
2743  return ParseMemOperand(Reg, Expr, Loc, EndLoc, Operands);
2744  }
2745  }
2746 }
2747 
2748 // X86::COND_INVALID if not a recognized condition code or alternate mnemonic,
2749 // otherwise the EFLAGS Condition Code enumerator.
2750 X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
2751  return StringSwitch<X86::CondCode>(CC)
2752  .Case("o", X86::COND_O) // Overflow
2753  .Case("no", X86::COND_NO) // No Overflow
2754  .Cases("b", "nae", X86::COND_B) // Below/Neither Above nor Equal
2755  .Cases("ae", "nb", X86::COND_AE) // Above or Equal/Not Below
2756  .Cases("e", "z", X86::COND_E) // Equal/Zero
2757  .Cases("ne", "nz", X86::COND_NE) // Not Equal/Not Zero
2758  .Cases("be", "na", X86::COND_BE) // Below or Equal/Not Above
2759  .Cases("a", "nbe", X86::COND_A) // Above/Neither Below nor Equal
2760  .Case("s", X86::COND_S) // Sign
2761  .Case("ns", X86::COND_NS) // No Sign
2762  .Cases("p", "pe", X86::COND_P) // Parity/Parity Even
2763  .Cases("np", "po", X86::COND_NP) // No Parity/Parity Odd
2764  .Cases("l", "nge", X86::COND_L) // Less/Neither Greater nor Equal
2765  .Cases("ge", "nl", X86::COND_GE) // Greater or Equal/Not Less
2766  .Cases("le", "ng", X86::COND_LE) // Less or Equal/Not Greater
2767  .Cases("g", "nle", X86::COND_G) // Greater/Neither Less nor Equal
2769 }
2770 
2771 // true on failure, false otherwise
2772 // If no {z} mark was found - Parser doesn't advance
2773 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2774  const SMLoc &StartLoc) {
2775  MCAsmParser &Parser = getParser();
2776  // Assuming we are just pass the '{' mark, quering the next token
2777  // Searched for {z}, but none was found. Return false, as no parsing error was
2778  // encountered
2779  if (!(getLexer().is(AsmToken::Identifier) &&
2780  (getLexer().getTok().getIdentifier() == "z")))
2781  return false;
2782  Parser.Lex(); // Eat z
2783  // Query and eat the '}' mark
2784  if (!getLexer().is(AsmToken::RCurly))
2785  return Error(getLexer().getLoc(), "Expected } at this point");
2786  Parser.Lex(); // Eat '}'
2787  // Assign Z with the {z} mark operand
2788  Z = X86Operand::CreateToken("{z}", StartLoc);
2789  return false;
2790 }
2791 
2792 // true on failure, false otherwise
2793 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
2794  MCAsmParser &Parser = getParser();
2795  if (getLexer().is(AsmToken::LCurly)) {
2796  // Eat "{" and mark the current place.
2797  const SMLoc consumedToken = consumeToken();
2798  // Distinguish {1to<NUM>} from {%k<NUM>}.
2799  if(getLexer().is(AsmToken::Integer)) {
2800  // Parse memory broadcasting ({1to<NUM>}).
2801  if (getLexer().getTok().getIntVal() != 1)
2802  return TokError("Expected 1to<NUM> at this point");
2803  StringRef Prefix = getLexer().getTok().getString();
2804  Parser.Lex(); // Eat first token of 1to8
2805  if (!getLexer().is(AsmToken::Identifier))
2806  return TokError("Expected 1to<NUM> at this point");
2807  // Recognize only reasonable suffixes.
2808  SmallVector<char, 5> BroadcastVector;
2809  StringRef BroadcastString = (Prefix + getLexer().getTok().getIdentifier())
2810  .toStringRef(BroadcastVector);
2811  if (!BroadcastString.startswith("1to"))
2812  return TokError("Expected 1to<NUM> at this point");
2813  const char *BroadcastPrimitive =
2814  StringSwitch<const char *>(BroadcastString)
2815  .Case("1to2", "{1to2}")
2816  .Case("1to4", "{1to4}")
2817  .Case("1to8", "{1to8}")
2818  .Case("1to16", "{1to16}")
2819  .Case("1to32", "{1to32}")
2820  .Default(nullptr);
2821  if (!BroadcastPrimitive)
2822  return TokError("Invalid memory broadcast primitive.");
2823  Parser.Lex(); // Eat trailing token of 1toN
2824  if (!getLexer().is(AsmToken::RCurly))
2825  return TokError("Expected } at this point");
2826  Parser.Lex(); // Eat "}"
2827  Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
2828  consumedToken));
2829  // No AVX512 specific primitives can pass
2830  // after memory broadcasting, so return.
2831  return false;
2832  } else {
2833  // Parse either {k}{z}, {z}{k}, {k} or {z}
2834  // last one have no meaning, but GCC accepts it
2835  // Currently, we're just pass a '{' mark
2836  std::unique_ptr<X86Operand> Z;
2837  if (ParseZ(Z, consumedToken))
2838  return true;
2839  // Reaching here means that parsing of the allegadly '{z}' mark yielded
2840  // no errors.
2841  // Query for the need of further parsing for a {%k<NUM>} mark
2842  if (!Z || getLexer().is(AsmToken::LCurly)) {
2843  SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2844  // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2845  // expected
2846  unsigned RegNo;
2847  SMLoc RegLoc;
2848  if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
2849  X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
2850  if (RegNo == X86::K0)
2851  return Error(RegLoc, "Register k0 can't be used as write mask");
2852  if (!getLexer().is(AsmToken::RCurly))
2853  return Error(getLexer().getLoc(), "Expected } at this point");
2854  Operands.push_back(X86Operand::CreateToken("{", StartLoc));
2855  Operands.push_back(
2856  X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
2857  Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2858  } else
2859  return Error(getLexer().getLoc(),
2860  "Expected an op-mask register at this point");
2861  // {%k<NUM>} mark is found, inquire for {z}
2862  if (getLexer().is(AsmToken::LCurly) && !Z) {
2863  // Have we've found a parsing error, or found no (expected) {z} mark
2864  // - report an error
2865  if (ParseZ(Z, consumeToken()) || !Z)
2866  return Error(getLexer().getLoc(),
2867  "Expected a {z} mark at this point");
2868 
2869  }
2870  // '{z}' on its own is meaningless, hence should be ignored.
2871  // on the contrary - have it been accompanied by a K register,
2872  // allow it.
2873  if (Z)
2874  Operands.push_back(std::move(Z));
2875  }
2876  }
2877  }
2878  return false;
2879 }
2880 
2881 /// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
2882 /// has already been parsed if present. disp may be provided as well.
2883 bool X86AsmParser::ParseMemOperand(unsigned SegReg, const MCExpr *Disp,
2884  SMLoc StartLoc, SMLoc EndLoc,
2886  MCAsmParser &Parser = getParser();
2887  SMLoc Loc;
2888  // Based on the initial passed values, we may be in any of these cases, we are
2889  // in one of these cases (with current position (*)):
2890 
2891  // 1. seg : * disp (base-index-scale-expr)
2892  // 2. seg : *(disp) (base-index-scale-expr)
2893  // 3. seg : *(base-index-scale-expr)
2894  // 4. disp *(base-index-scale-expr)
2895  // 5. *(disp) (base-index-scale-expr)
2896  // 6. *(base-index-scale-expr)
2897  // 7. disp *
2898  // 8. *(disp)
2899 
2900  // If we do not have an displacement yet, check if we're in cases 4 or 6 by
2901  // checking if the first object after the parenthesis is a register (or an
2902  // identifier referring to a register) and parse the displacement or default
2903  // to 0 as appropriate.
2904  auto isAtMemOperand = [this]() {
2905  if (this->getLexer().isNot(AsmToken::LParen))
2906  return false;
2907  AsmToken Buf[2];
2908  StringRef Id;
2909  auto TokCount = this->getLexer().peekTokens(Buf, true);
2910  if (TokCount == 0)
2911  return false;
2912  switch (Buf[0].getKind()) {
2913  case AsmToken::Percent:
2914  case AsmToken::Comma:
2915  return true;
2916  // These lower cases are doing a peekIdentifier.
2917  case AsmToken::At:
2918  case AsmToken::Dollar:
2919  if ((TokCount > 1) &&
2920  (Buf[1].is(AsmToken::Identifier) || Buf[1].is(AsmToken::String)) &&
2921  (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
2922  Id = StringRef(Buf[0].getLoc().getPointer(),
2923  Buf[1].getIdentifier().size() + 1);
2924  break;
2925  case AsmToken::Identifier:
2926  case AsmToken::String:
2927  Id = Buf[0].getIdentifier();
2928  break;
2929  default:
2930  return false;
2931  }
2932  // We have an ID. Check if it is bound to a register.
2933  if (!Id.empty()) {
2934  MCSymbol *Sym = this->getContext().getOrCreateSymbol(Id);
2935  if (Sym->isVariable()) {
2936  auto V = Sym->getVariableValue(/*SetUsed*/ false);
2937  return isa<X86MCExpr>(V);
2938  }
2939  }
2940  return false;
2941  };
2942 
2943  if (!Disp) {
2944  // Parse immediate if we're not at a mem operand yet.
2945  if (!isAtMemOperand()) {
2946  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Disp, EndLoc))
2947  return true;
2948  assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
2949  } else {
2950  // Disp is implicitly zero if we haven't parsed it yet.
2951  Disp = MCConstantExpr::create(0, Parser.getContext());
2952  }
2953  }
2954 
2955  // We are now either at the end of the operand or at the '(' at the start of a
2956  // base-index-scale-expr.
2957 
2958  if (!parseOptionalToken(AsmToken::LParen)) {
2959  if (SegReg == 0)
2960  Operands.push_back(
2961  X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
2962  else
2963  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
2964  0, 0, 1, StartLoc, EndLoc));
2965  return false;
2966  }
2967 
2968  // If we reached here, then eat the '(' and Process
2969  // the rest of the memory operand.
2970  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2971  SMLoc BaseLoc = getLexer().getLoc();
2972  const MCExpr *E;
2973  StringRef ErrMsg;
2974 
2975  // Parse BaseReg if one is provided.
2976  if (getLexer().isNot(AsmToken::Comma) && getLexer().isNot(AsmToken::RParen)) {
2977  if (Parser.parseExpression(E, EndLoc) ||
2978  check(!isa<X86MCExpr>(E), BaseLoc, "expected register here"))
2979  return true;
2980 
2981  // Check the register.
2982  BaseReg = cast<X86MCExpr>(E)->getRegNo();
2983  if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
2984  return Error(BaseLoc, "eiz and riz can only be used as index registers",
2985  SMRange(BaseLoc, EndLoc));
2986  }
2987 
2988  if (parseOptionalToken(AsmToken::Comma)) {
2989  // Following the comma we should have either an index register, or a scale
2990  // value. We don't support the later form, but we want to parse it
2991  // correctly.
2992  //
2993  // Even though it would be completely consistent to support syntax like
2994  // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2995  if (getLexer().isNot(AsmToken::RParen)) {
2996  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(E, EndLoc))
2997  return true;
2998 
2999  if (!isa<X86MCExpr>(E)) {
3000  // We've parsed an unexpected Scale Value instead of an index
3001  // register. Interpret it as an absolute.
3002  int64_t ScaleVal;
3003  if (!E->evaluateAsAbsolute(ScaleVal, getStreamer().getAssemblerPtr()))
3004  return Error(Loc, "expected absolute expression");
3005  if (ScaleVal != 1)
3006  Warning(Loc, "scale factor without index register is ignored");
3007  Scale = 1;
3008  } else { // IndexReg Found.
3009  IndexReg = cast<X86MCExpr>(E)->getRegNo();
3010 
3011  if (BaseReg == X86::RIP)
3012  return Error(Loc,
3013  "%rip as base register can not have an index register");
3014  if (IndexReg == X86::RIP)
3015  return Error(Loc, "%rip is not allowed as an index register");
3016 
3017  if (parseOptionalToken(AsmToken::Comma)) {
3018  // Parse the scale amount:
3019  // ::= ',' [scale-expression]
3020 
3021  // A scale amount without an index is ignored.
3022  if (getLexer().isNot(AsmToken::RParen)) {
3023  int64_t ScaleVal;
3024  if (Parser.parseTokenLoc(Loc) ||
3025  Parser.parseAbsoluteExpression(ScaleVal))
3026  return Error(Loc, "expected scale expression");
3027  Scale = (unsigned)ScaleVal;
3028  // Validate the scale amount.
3029  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
3030  Scale != 1)
3031  return Error(Loc, "scale factor in 16-bit address must be 1");
3032  if (checkScale(Scale, ErrMsg))
3033  return Error(Loc, ErrMsg);
3034  }
3035  }
3036  }
3037  }
3038  }
3039 
3040  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
3041  if (parseToken(AsmToken::RParen, "unexpected token in memory operand"))
3042  return true;
3043 
3044  // This is to support otherwise illegal operand (%dx) found in various
3045  // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
3046  // be supported. Mark such DX variants separately fix only in special cases.
3047  if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
3048  isa<MCConstantExpr>(Disp) &&
3049  cast<MCConstantExpr>(Disp)->getValue() == 0) {
3050  Operands.push_back(X86Operand::CreateDXReg(BaseLoc, BaseLoc));
3051  return false;
3052  }
3053 
3054  if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
3055  ErrMsg))
3056  return Error(BaseLoc, ErrMsg);
3057 
3058  if (SegReg || BaseReg || IndexReg)
3059  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
3060  BaseReg, IndexReg, Scale, StartLoc,
3061  EndLoc));
3062  else
3063  Operands.push_back(
3064  X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
3065  return false;
3066 }
3067 
3068 // Parse either a standard primary expression or a register.
3069 bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
3070  MCAsmParser &Parser = getParser();
3071  // See if this is a register first.
3072  if (getTok().is(AsmToken::Percent) ||
3073  (isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
3074  MatchRegisterName(Parser.getTok().getString()))) {
3075  SMLoc StartLoc = Parser.getTok().getLoc();
3076  unsigned RegNo;
3077  if (ParseRegister(RegNo, StartLoc, EndLoc))
3078  return true;
3079  Res = X86MCExpr::create(RegNo, Parser.getContext());
3080  return false;
3081  }
3082  return Parser.parsePrimaryExpr(Res, EndLoc, nullptr);
3083 }
3084 
3085 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
3086  SMLoc NameLoc, OperandVector &Operands) {
3087  MCAsmParser &Parser = getParser();
3088  InstInfo = &Info;
3089 
3090  // Reset the forced VEX encoding.
3091  ForcedVEXEncoding = VEXEncoding_Default;
3092  ForcedDispEncoding = DispEncoding_Default;
3093 
3094  // Parse pseudo prefixes.
3095  while (true) {
3096  if (Name == "{") {
3097  if (getLexer().isNot(AsmToken::Identifier))
3098  return Error(Parser.getTok().getLoc(), "Unexpected token after '{'");
3099  std::string Prefix = Parser.getTok().getString().lower();
3100  Parser.Lex(); // Eat identifier.
3101  if (getLexer().isNot(AsmToken::RCurly))
3102  return Error(Parser.getTok().getLoc(), "Expected '}'");
3103  Parser.Lex(); // Eat curly.
3104 
3105  if (Prefix == "vex")
3106  ForcedVEXEncoding = VEXEncoding_VEX;
3107  else if (Prefix == "vex2")
3108  ForcedVEXEncoding = VEXEncoding_VEX2;
3109  else if (Prefix == "vex3")
3110  ForcedVEXEncoding = VEXEncoding_VEX3;
3111  else if (Prefix == "evex")
3112  ForcedVEXEncoding = VEXEncoding_EVEX;
3113  else if (Prefix == "disp8")
3114  ForcedDispEncoding = DispEncoding_Disp8;
3115  else if (Prefix == "disp32")
3116  ForcedDispEncoding = DispEncoding_Disp32;
3117  else
3118  return Error(NameLoc, "unknown prefix");
3119 
3120  NameLoc = Parser.getTok().getLoc();
3121  if (getLexer().is(AsmToken::LCurly)) {
3122  Parser.Lex();
3123  Name = "{";
3124  } else {
3125  if (getLexer().isNot(AsmToken::Identifier))
3126  return Error(Parser.getTok().getLoc(), "Expected identifier");
3127  // FIXME: The mnemonic won't match correctly if its not in lower case.
3128  Name = Parser.getTok().getString();
3129  Parser.Lex();
3130  }
3131  continue;
3132  }
3133  // Parse MASM style pseudo prefixes.
3134  if (isParsingMSInlineAsm()) {
3135  if (Name.equals_insensitive("vex"))
3136  ForcedVEXEncoding = VEXEncoding_VEX;
3137  else if (Name.equals_insensitive("vex2"))
3138  ForcedVEXEncoding = VEXEncoding_VEX2;
3139  else if (Name.equals_insensitive("vex3"))
3140  ForcedVEXEncoding = VEXEncoding_VEX3;
3141  else if (Name.equals_insensitive("evex"))
3142  ForcedVEXEncoding = VEXEncoding_EVEX;
3143 
3144  if (ForcedVEXEncoding != VEXEncoding_Default) {
3145  if (getLexer().isNot(AsmToken::Identifier))
3146  return Error(Parser.getTok().getLoc(), "Expected identifier");
3147  // FIXME: The mnemonic won't match correctly if its not in lower case.
3148  Name = Parser.getTok().getString();
3149  NameLoc = Parser.getTok().getLoc();
3150  Parser.Lex();
3151  }
3152  }
3153  break;
3154  }
3155 
3156  // Support the suffix syntax for overriding displacement size as well.
3157  if (Name.consume_back(".d32")) {
3158  ForcedDispEncoding = DispEncoding_Disp32;
3159  } else if (Name.consume_back(".d8")) {
3160  ForcedDispEncoding = DispEncoding_Disp8;
3161  }
3162 
3163  StringRef PatchedName = Name;
3164 
3165  // Hack to skip "short" following Jcc.
3166  if (isParsingIntelSyntax() &&
3167  (PatchedName == "jmp" || PatchedName == "jc" || PatchedName == "jnc" ||
3168  PatchedName == "jcxz" || PatchedName == "jecxz" ||
3169  (PatchedName.startswith("j") &&
3170  ParseConditionCode(PatchedName.substr(1)) != X86::COND_INVALID))) {
3171  StringRef NextTok = Parser.getTok().getString();
3172  if (Parser.isParsingMasm() ? NextTok.equals_insensitive("short")
3173  : NextTok == "short") {
3174  SMLoc NameEndLoc =
3175  NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
3176  // Eat the short keyword.
3177  Parser.Lex();
3178  // MS and GAS ignore the short keyword; they both determine the jmp type
3179  // based on the distance of the label. (NASM does emit different code with
3180  // and without "short," though.)
3181  InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
3182  NextTok.size() + 1);
3183  }
3184  }
3185 
3186  // FIXME: Hack to recognize setneb as setne.
3187  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
3188  PatchedName != "setb" && PatchedName != "setnb")
3189  PatchedName = PatchedName.substr(0, Name.size()-1);
3190 
3191  unsigned ComparisonPredicate = ~0U;
3192 
3193  // FIXME: Hack to recognize cmp<comparison code>{sh,ss,sd,ph,ps,pd}.
3194  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
3195  (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
3196  PatchedName.endswith("sh") || PatchedName.endswith("ph") ||
3197  PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
3198  bool IsVCMP = PatchedName[0] == 'v';
3199  unsigned CCIdx = IsVCMP ? 4 : 3;
3200  unsigned CC = StringSwitch<unsigned>(
3201  PatchedName.slice(CCIdx, PatchedName.size() - 2))
3202  .Case("eq", 0x00)
3203  .Case("eq_oq", 0x00)
3204  .Case("lt", 0x01)
3205  .Case("lt_os", 0x01)
3206  .Case("le", 0x02)
3207  .Case("le_os", 0x02)
3208  .Case("unord", 0x03)
3209  .Case("unord_q", 0x03)
3210  .Case("neq", 0x04)
3211  .Case("neq_uq", 0x04)
3212  .Case("nlt", 0x05)
3213  .Case("nlt_us", 0x05)
3214  .Case("nle", 0x06)
3215  .Case("nle_us", 0x06)
3216  .Case("ord", 0x07)
3217  .Case("ord_q", 0x07)
3218  /* AVX only from here */
3219  .Case("eq_uq", 0x08)
3220  .Case("nge", 0x09)
3221  .Case("nge_us", 0x09)
3222  .Case("ngt", 0x0A)
3223  .Case("ngt_us", 0x0A)
3224  .Case("false", 0x0B)
3225  .Case("false_oq", 0x0B)
3226  .Case("neq_oq", 0x0C)
3227  .Case("ge", 0x0D)
3228  .Case("ge_os", 0x0D)
3229  .Case("gt", 0x0E)
3230  .Case("gt_os", 0x0E)
3231  .Case("true", 0x0F)
3232  .Case("true_uq", 0x0F)
3233  .Case("eq_os", 0x10)
3234  .Case("lt_oq", 0x11)
3235  .Case("le_oq", 0x12)
3236  .Case("unord_s", 0x13)
3237  .Case("neq_us", 0x14)
3238  .Case("nlt_uq", 0x15)
3239  .Case("nle_uq", 0x16)
3240  .Case("ord_s", 0x17)
3241  .Case("eq_us", 0x18)
3242  .Case("nge_uq", 0x19)
3243  .Case("ngt_uq", 0x1A)
3244  .Case("false_os", 0x1B)
3245  .Case("neq_os", 0x1C)
3246  .Case("ge_oq", 0x1D)
3247  .Case("gt_oq", 0x1E)
3248  .Case("true_us", 0x1F)
3249  .Default(~0U);
3250  if (CC != ~0U && (IsVCMP || CC < 8) &&
3251  (IsVCMP || PatchedName.back() != 'h')) {
3252  if (PatchedName.endswith("ss"))
3253  PatchedName = IsVCMP ? "vcmpss" : "cmpss";
3254  else if (PatchedName.endswith("sd"))
3255  PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
3256  else if (PatchedName.endswith("ps"))
3257  PatchedName = IsVCMP ? "vcmpps" : "cmpps";
3258  else if (PatchedName.endswith("pd"))
3259  PatchedName = IsVCMP ? "vcmppd" : "cmppd";
3260  else if (PatchedName.endswith("sh"))
3261  PatchedName = "vcmpsh";
3262  else if (PatchedName.endswith("ph"))
3263  PatchedName = "vcmpph";
3264  else
3265  llvm_unreachable("Unexpected suffix!");
3266 
3267  ComparisonPredicate = CC;
3268  }
3269  }
3270 
3271  // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3272  if (PatchedName.startswith("vpcmp") &&
3273  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3274  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3275  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3276  unsigned CC = StringSwitch<unsigned>(
3277  PatchedName.slice(5, PatchedName.size() - SuffixSize))
3278  .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
3279  .Case("lt", 0x1)
3280  .Case("le", 0x2)
3281  //.Case("false", 0x3) // Not a documented alias.
3282  .Case("neq", 0x4)
3283  .Case("nlt", 0x5)
3284  .Case("nle", 0x6)
3285  //.Case("true", 0x7) // Not a documented alias.
3286  .Default(~0U);
3287  if (CC != ~0U && (CC != 0 || SuffixSize == 2)) {
3288  switch (PatchedName.back()) {
3289  default: llvm_unreachable("Unexpected character!");
3290  case 'b': PatchedName = SuffixSize == 2 ? "vpcmpub" : "vpcmpb"; break;
3291  case 'w': PatchedName = SuffixSize == 2 ? "vpcmpuw" : "vpcmpw"; break;
3292  case 'd': PatchedName = SuffixSize == 2 ? "vpcmpud" : "vpcmpd"; break;
3293  case 'q': PatchedName = SuffixSize == 2 ? "vpcmpuq" : "vpcmpq"; break;
3294  }
3295  // Set up the immediate to push into the operands later.
3296  ComparisonPredicate = CC;
3297  }
3298  }
3299 
3300  // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3301  if (PatchedName.startswith("vpcom") &&
3302  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3303  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3304  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3305  unsigned CC = StringSwitch<unsigned>(
3306  PatchedName.slice(5, PatchedName.size() - SuffixSize))
3307  .Case("lt", 0x0)
3308  .Case("le", 0x1)
3309  .Case("gt", 0x2)
3310  .Case("ge", 0x3)
3311  .Case("eq", 0x4)
3312  .Case("neq", 0x5)
3313  .Case("false", 0x6)
3314  .Case("true", 0x7)
3315  .Default(~0U);
3316  if (CC != ~0U) {
3317  switch (PatchedName.back()) {
3318  default: llvm_unreachable("Unexpected character!");
3319  case 'b': PatchedName = SuffixSize == 2 ? "vpcomub" : "vpcomb"; break;
3320  case 'w': PatchedName = SuffixSize == 2 ? "vpcomuw" : "vpcomw"; break;
3321  case 'd': PatchedName = SuffixSize == 2 ? "vpcomud" : "vpcomd"; break;
3322  case 'q': PatchedName = SuffixSize == 2 ? "vpcomuq" : "vpcomq"; break;
3323  }
3324  // Set up the immediate to push into the operands later.
3325  ComparisonPredicate = CC;
3326  }
3327  }
3328 
3329 
3330  // Determine whether this is an instruction prefix.
3331  // FIXME:
3332  // Enhance prefixes integrity robustness. for example, following forms
3333  // are currently tolerated:
3334  // repz repnz <insn> ; GAS errors for the use of two similar prefixes
3335  // lock addq %rax, %rbx ; Destination operand must be of memory type
3336  // xacquire <insn> ; xacquire must be accompanied by 'lock'
3337  bool IsPrefix =
3339  .Cases("cs", "ds", "es", "fs", "gs", "ss", true)
3340  .Cases("rex64", "data32", "data16", "addr32", "addr16", true)
3341  .Cases("xacquire", "xrelease", true)
3342  .Cases("acquire", "release", isParsingIntelSyntax())
3343  .Default(false);
3344 
3345  auto isLockRepeatNtPrefix = [](StringRef N) {
3346  return StringSwitch<bool>(N)
3347  .Cases("lock", "rep", "repe", "repz", "repne", "repnz", "notrack", true)
3348  .Default(false);
3349  };
3350 
3351  bool CurlyAsEndOfStatement = false;
3352 
3353  unsigned Flags = X86::IP_NO_PREFIX;
3354  while (isLockRepeatNtPrefix(Name.lower())) {
3355  unsigned Prefix =
3357  .Cases("lock", "lock", X86::IP_HAS_LOCK)
3358  .Cases("rep", "repe", "repz", X86::IP_HAS_REPEAT)
3359  .Cases("repne", "repnz", X86::IP_HAS_REPEAT_NE)
3360  .Cases("notrack", "notrack", X86::IP_HAS_NOTRACK)
3361  .Default(X86::IP_NO_PREFIX); // Invalid prefix (impossible)
3362  Flags |= Prefix;
3363  if (getLexer().is(AsmToken::EndOfStatement)) {
3364  // We don't have real instr with the given prefix
3365  // let's use the prefix as the instr.
3366  // TODO: there could be several prefixes one after another
3367  Flags = X86::IP_NO_PREFIX;
3368  break;
3369  }
3370  // FIXME: The mnemonic won't match correctly if its not in lower case.
3371  Name = Parser.getTok().getString();
3372  Parser.Lex(); // eat the prefix
3373  // Hack: we could have something like "rep # some comment" or
3374  // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
3375  while (Name.startswith(";") || Name.startswith("\n") ||
3376  Name.startswith("#") || Name.startswith("\t") ||
3377  Name.startswith("/")) {
3378  // FIXME: The mnemonic won't match correctly if its not in lower case.
3379  Name = Parser.getTok().getString();
3380  Parser.Lex(); // go to next prefix or instr
3381  }
3382  }
3383 
3384  if (Flags)
3385  PatchedName = Name;
3386 
3387  // Hacks to handle 'data16' and 'data32'
3388  if (PatchedName == "data16" && is16BitMode()) {
3389  return Error(NameLoc, "redundant data16 prefix");
3390  }
3391  if (PatchedName == "data32") {
3392  if (is32BitMode())
3393  return Error(NameLoc, "redundant data32 prefix");
3394  if (is64BitMode())
3395  return Error(NameLoc, "'data32' is not supported in 64-bit mode");
3396  // Hack to 'data16' for the table lookup.
3397  PatchedName = "data16";
3398 
3399  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3400  StringRef Next = Parser.getTok().getString();
3401  getLexer().Lex();
3402  // data32 effectively changes the instruction suffix.
3403  // TODO Generalize.
3404  if (Next == "callw")
3405  Next = "calll";
3406  if (Next == "ljmpw")
3407  Next = "ljmpl";
3408 
3409  Name = Next;
3410  PatchedName = Name;
3411  ForcedDataPrefix = X86::Is32Bit;
3412  IsPrefix = false;
3413  }
3414  }
3415 
3416  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
3417 
3418  // Push the immediate if we extracted one from the mnemonic.
3419  if (ComparisonPredicate != ~0U && !isParsingIntelSyntax()) {
3420  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
3421  getParser().getContext());
3422  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
3423  }
3424 
3425  // This does the actual operand parsing. Don't parse any more if we have a
3426  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
3427  // just want to parse the "lock" as the first instruction and the "incl" as
3428  // the next one.
3429  if (getLexer().isNot(AsmToken::EndOfStatement) && !IsPrefix) {
3430  // Parse '*' modifier.
3431  if (getLexer().is(AsmToken::Star))
3432  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
3433 
3434  // Read the operands.
3435  while (true) {
3436  if (parseOperand(Operands, Name))
3437  return true;
3438  if (HandleAVX512Operand(Operands))
3439  return true;
3440 
3441  // check for comma and eat it
3442  if (getLexer().is(AsmToken::Comma))
3443  Parser.Lex();
3444  else
3445  break;
3446  }
3447 
3448  // In MS inline asm curly braces mark the beginning/end of a block,
3449  // therefore they should be interepreted as end of statement
3450  CurlyAsEndOfStatement =
3451  isParsingIntelSyntax() && isParsingMSInlineAsm() &&
3452  (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
3453  if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
3454  return TokError("unexpected token in argument list");
3455  }
3456 
3457  // Push the immediate if we extracted one from the mnemonic.
3458  if (ComparisonPredicate != ~0U && isParsingIntelSyntax()) {
3459  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
3460  getParser().getContext());
3461  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
3462  }
3463 
3464  // Consume the EndOfStatement or the prefix separator Slash
3465  if (getLexer().is(AsmToken::EndOfStatement) ||
3466  (IsPrefix && getLexer().is(AsmToken::Slash)))
3467  Parser.Lex();
3468  else if (CurlyAsEndOfStatement)
3469  // Add an actual EndOfStatement before the curly brace
3470  Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
3471  getLexer().getTok().getLoc(), 0);
3472 
3473  // This is for gas compatibility and cannot be done in td.
3474  // Adding "p" for some floating point with no argument.
3475  // For example: fsub --> fsubp
3476  bool IsFp =
3477  Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
3478  if (IsFp && Operands.size() == 1) {
3479  const char *Repl = StringSwitch<const char *>(Name)
3480  .Case("fsub", "fsubp")
3481  .Case("fdiv", "fdivp")
3482  .Case("fsubr", "fsubrp")
3483  .Case("fdivr", "fdivrp");
3484  static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
3485  }
3486 
3487  if ((Name == "mov" || Name == "movw" || Name == "movl") &&
3488  (Operands.size() == 3)) {
3489  X86Operand &Op1 = (X86Operand &)*Operands[1];
3490  X86Operand &Op2 = (X86Operand &)*Operands[2];
3491  SMLoc Loc = Op1.getEndLoc();
3492  // Moving a 32 or 16 bit value into a segment register has the same
3493  // behavior. Modify such instructions to always take shorter form.
3494  if (Op1.isReg() && Op2.isReg() &&
3495  X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
3496  Op2.getReg()) &&
3497  (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
3498  X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
3499  // Change instruction name to match new instruction.
3500  if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
3501  Name = is16BitMode() ? "movw" : "movl";
3502  Operands[0] = X86Operand::CreateToken(Name, NameLoc);
3503  }
3504  // Select the correct equivalent 16-/32-bit source register.
3505  unsigned Reg =
3506  getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
3507  Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
3508  }
3509  }
3510 
3511  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
3512  // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
3513  // documented form in various unofficial manuals, so a lot of code uses it.
3514  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
3515  Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
3516  Operands.size() == 3) {
3517  X86Operand &Op = (X86Operand &)*Operands.back();
3518  if (Op.isDXReg())
3519  Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3520  Op.getEndLoc());
3521  }
3522  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
3523  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
3524  Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
3525  Operands.size() == 3) {
3526  X86Operand &Op = (X86Operand &)*Operands[1];
3527  if (Op.isDXReg())
3528  Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3529  Op.getEndLoc());
3530  }
3531 
3533  bool HadVerifyError = false;
3534 
3535  // Append default arguments to "ins[bwld]"
3536  if (Name.startswith("ins") &&
3537  (Operands.size() == 1 || Operands.size() == 3) &&
3538  (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
3539  Name == "ins")) {
3540 
3541  AddDefaultSrcDestOperands(TmpOperands,
3542  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
3543  DefaultMemDIOperand(NameLoc));
3544  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3545  }
3546 
3547  // Append default arguments to "outs[bwld]"
3548  if (Name.startswith("outs") &&
3549  (Operands.size() == 1 || Operands.size() == 3) &&
3550  (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
3551  Name == "outsd" || Name == "outs")) {
3552  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
3553  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
3554  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3555  }
3556 
3557  // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
3558  // values of $SIREG according to the mode. It would be nice if this
3559  // could be achieved with InstAlias in the tables.
3560  if (Name.startswith("lods") &&
3561  (Operands.size() == 1 || Operands.size() == 2) &&
3562  (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
3563  Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
3564  TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
3565  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3566  }
3567 
3568  // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
3569  // values of $DIREG according to the mode. It would be nice if this
3570  // could be achieved with InstAlias in the tables.
3571  if (Name.startswith("stos") &&
3572  (Operands.size() == 1 || Operands.size() == 2) &&
3573  (Name == "stos" || Name == "stosb" || Name == "stosw" ||
3574  Name == "stosl" || Name == "stosd" || Name == "stosq")) {
3575  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
3576  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3577  }
3578 
3579  // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
3580  // values of $DIREG according to the mode. It would be nice if this
3581  // could be achieved with InstAlias in the tables.
3582  if (Name.startswith("scas") &&
3583  (Operands.size() == 1 || Operands.size() == 2) &&
3584  (Name == "scas" || Name == "scasb" || Name == "scasw" ||
3585  Name == "scasl" || Name == "scasd" || Name == "scasq")) {
3586  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
3587  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3588  }
3589 
3590  // Add default SI and DI operands to "cmps[bwlq]".
3591  if (Name.startswith("cmps") &&
3592  (Operands.size() == 1 || Operands.size() == 3) &&
3593  (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
3594  Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
3595  AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
3596  DefaultMemSIOperand(NameLoc));
3597  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3598  }
3599 
3600  // Add default SI and DI operands to "movs[bwlq]".
3601  if (((Name.startswith("movs") &&
3602  (Name == "movs" || Name == "movsb" || Name == "movsw" ||
3603  Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
3604  (Name.startswith("smov") &&
3605  (Name == "smov" || Name == "smovb" || Name == "smovw" ||
3606  Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
3607  (Operands.size() == 1 || Operands.size() == 3)) {
3608  if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
3609  Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
3610  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
3611  DefaultMemDIOperand(NameLoc));
3612  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3613  }
3614 
3615  // Check if we encountered an error for one the string insturctions
3616  if (HadVerifyError) {
3617  return HadVerifyError;
3618  }
3619 
3620  // Transforms "xlat mem8" into "xlatb"
3621  if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
3622  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
3623  if (Op1.isMem8()) {
3624  Warning(Op1.getStartLoc(), "memory operand is only for determining the "
3625  "size, (R|E)BX will be used for the location");
3626  Operands.pop_back();
3627  static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
3628  }
3629  }
3630 
3631  if (Flags)
3632  Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
3633  return false;
3634 }
3635 
3636 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
3637  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3638 
3639  switch (Inst.getOpcode()) {
3640  default: return false;
3641  case X86::JMP_1:
3642  // {disp32} forces a larger displacement as if the instruction was relaxed.
3643  // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3644  // This matches GNU assembler.
3645  if (ForcedDispEncoding == DispEncoding_Disp32) {
3646  Inst.setOpcode(is16BitMode() ? X86::JMP_2 : X86::JMP_4);
3647  return true;
3648  }
3649 
3650  return false;
3651  case X86::JCC_1:
3652  // {disp32} forces a larger displacement as if the instruction was relaxed.
3653  // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3654  // This matches GNU assembler.
3655  if (ForcedDispEncoding == DispEncoding_Disp32) {
3656  Inst.setOpcode(is16BitMode() ? X86::JCC_2 : X86::JCC_4);
3657  return true;
3658  }
3659 
3660  return false;
3661  case X86::VMOVZPQILo2PQIrr:
3662  case X86::VMOVAPDrr:
3663  case X86::VMOVAPDYrr:
3664  case X86::VMOVAPSrr:
3665  case X86::VMOVAPSYrr:
3666  case X86::VMOVDQArr:
3667  case X86::VMOVDQAYrr:
3668  case X86::VMOVDQUrr:
3669  case X86::VMOVDQUYrr:
3670  case X86::VMOVUPDrr:
3671  case X86::VMOVUPDYrr:
3672  case X86::VMOVUPSrr:
3673  case X86::VMOVUPSYrr: {
3674  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3675  // the registers is extended, but other isn't.
3676  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
3677  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
3678  MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8)
3679  return false;
3680 
3681  unsigned NewOpc;
3682  switch (Inst.getOpcode()) {
3683  default: llvm_unreachable("Invalid opcode");
3684  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
3685  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
3686  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
3687  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
3688  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
3689  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
3690  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
3691  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
3692  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
3693  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
3694  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
3695  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
3696  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
3697  }
3698  Inst.setOpcode(NewOpc);
3699  return true;
3700  }
3701  case X86::VMOVSDrr:
3702  case X86::VMOVSSrr: {
3703  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3704  // the registers is extended, but other isn't.
3705  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
3706  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
3707  MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8)
3708  return false;
3709 
3710  unsigned NewOpc;
3711  switch (Inst.getOpcode()) {
3712  default: llvm_unreachable("Invalid opcode");
3713  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
3714  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
3715  }
3716  Inst.setOpcode(NewOpc);
3717  return true;
3718  }
3719  case X86::RCR8ri: case X86::RCR16ri: case X86::RCR32ri: case X86::RCR64ri:
3720  case X86::RCL8ri: case X86::RCL16ri: case X86::RCL32ri: case X86::RCL64ri:
3721  case X86::ROR8ri: case X86::ROR16ri: case X86::ROR32ri: case X86::ROR64ri:
3722  case X86::ROL8ri: case X86::ROL16ri: case X86::ROL32ri: case X86::ROL64ri:
3723  case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri: case X86::SAR64ri:
3724  case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri: case X86::SHR64ri:
3725  case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri: case X86::SHL64ri: {
3726  // Optimize s{hr,ar,hl} $1, <op> to "shift <op>". Similar for rotate.
3727  // FIXME: It would be great if we could just do this with an InstAlias.
3728  if (!Inst.getOperand(2).isImm() || Inst.getOperand(2).getImm() != 1)
3729  return false;
3730 
3731  unsigned NewOpc;
3732  switch (Inst.getOpcode()) {
3733  default: llvm_unreachable("Invalid opcode");
3734  case X86::RCR8ri: NewOpc = X86::RCR8r1; break;
3735  case X86::RCR16ri: NewOpc = X86::RCR16r1; break;
3736  case X86::RCR32ri: NewOpc = X86::RCR32r1; break;
3737  case X86::RCR64ri: NewOpc = X86::RCR64r1; break;
3738  case X86::RCL8ri: NewOpc = X86::RCL8r1; break;
3739  case X86::RCL16ri: NewOpc = X86::RCL16r1; break;
3740  case X86::RCL32ri: NewOpc = X86::RCL32r1; break;
3741  case X86::RCL64ri: NewOpc = X86::RCL64r1; break;
3742  case X86::ROR8ri: NewOpc = X86::ROR8r1; break;
3743  case X86::ROR16ri: NewOpc = X86::ROR16r1; break;
3744  case X86::ROR32ri: NewOpc = X86::ROR32r1; break;
3745  case X86::ROR64ri: NewOpc = X86::ROR64r1; break;
3746  case X86::ROL8ri: NewOpc = X86::ROL8r1; break;
3747  case X86::ROL16ri: NewOpc = X86::ROL16r1; break;
3748  case X86::ROL32ri: NewOpc = X86::ROL32r1; break;
3749  case X86::ROL64ri: NewOpc = X86::ROL64r1; break;
3750  case X86::SAR8ri: NewOpc = X86::SAR8r1; break;
3751  case X86::SAR16ri: NewOpc = X86::SAR16r1; break;
3752  case X86::SAR32ri: NewOpc = X86::SAR32r1; break;
3753  case X86::SAR64ri: NewOpc = X86::SAR64r1; break;
3754  case X86::SHR8ri: NewOpc = X86::SHR8r1; break;
3755  case X86::SHR16ri: NewOpc = X86::SHR16r1; break;
3756  case X86::SHR32ri: NewOpc = X86::SHR32r1; break;
3757  case X86::SHR64ri: NewOpc = X86::SHR64r1; break;
3758  case X86::SHL8ri: NewOpc = X86::SHL8r1; break;
3759  case X86::SHL16ri: NewOpc = X86::SHL16r1; break;
3760  case X86::SHL32ri: NewOpc = X86::SHL32r1; break;
3761  case X86::SHL64ri: NewOpc = X86::SHL64r1; break;
3762  }
3763 
3764  MCInst TmpInst;
3765  TmpInst.setOpcode(NewOpc);
3766  TmpInst.addOperand(Inst.getOperand(0));
3767  TmpInst.addOperand(Inst.getOperand(1));
3768  Inst = TmpInst;
3769  return true;
3770  }
3771  case X86::RCR8mi: case X86::RCR16mi: case X86::RCR32mi: case X86::RCR64mi:
3772  case X86::RCL8mi: case X86::RCL16mi: case X86::RCL32mi: case X86::RCL64mi:
3773  case X86::ROR8mi: case X86::ROR16mi: case X86::ROR32mi: case X86::ROR64mi:
3774  case X86::ROL8mi: case X86::ROL16mi: case X86::ROL32mi: case X86::ROL64mi:
3775  case X86::SAR8mi: case X86::SAR16mi: case X86::SAR32mi: case X86::SAR64mi:
3776  case X86::SHR8mi: case X86::SHR16mi: case X86::SHR32mi: case X86::SHR64mi:
3777  case X86::SHL8mi: case X86::SHL16mi: case X86::SHL32mi: case X86::SHL64mi: {
3778  // Optimize s{hr,ar,hl} $1, <op> to "shift <op>". Similar for rotate.
3779  // FIXME: It would be great if we could just do this with an InstAlias.
3780  if (!Inst.getOperand(X86::AddrNumOperands).isImm() ||
3781  Inst.getOperand(X86::AddrNumOperands).getImm() != 1)
3782  return false;
3783 
3784  unsigned NewOpc;
3785  switch (Inst.getOpcode()) {
3786  default: llvm_unreachable("Invalid opcode");
3787  case X86::RCR8mi: NewOpc = X86::RCR8m1; break;
3788  case X86::RCR16mi: NewOpc = X86::RCR16m1; break;
3789  case X86::RCR32mi: NewOpc = X86::RCR32m1; break;
3790  case X86::RCR64mi: NewOpc = X86::RCR64m1; break;
3791  case X86::RCL8mi: NewOpc = X86::RCL8m1; break;
3792  case X86::RCL16mi: NewOpc = X86::RCL16m1; break;
3793  case X86::RCL32mi: NewOpc = X86::RCL32m1; break;
3794  case X86::RCL64mi: NewOpc = X86::RCL64m1; break;
3795  case X86::ROR8mi: NewOpc = X86::ROR8m1; break;
3796  case X86::ROR16mi: NewOpc = X86::ROR16m1; break;
3797  case X86::ROR32mi: NewOpc = X86::ROR32m1; break;
3798  case X86::ROR64mi: NewOpc = X86::ROR64m1; break;
3799  case X86::ROL8mi: NewOpc = X86::ROL8m1; break;
3800  case X86::ROL16mi: NewOpc = X86::ROL16m1; break;
3801  case X86::ROL32mi: NewOpc = X86::ROL32m1; break;
3802  case X86::ROL64mi: NewOpc = X86::ROL64m1; break;
3803  case X86::SAR8mi: NewOpc = X86::SAR8m1; break;
3804  case X86::SAR16mi: NewOpc = X86::SAR16m1; break;
3805  case X86::SAR32mi: NewOpc = X86::SAR32m1; break;
3806  case X86::SAR64mi: NewOpc = X86::SAR64m1; break;
3807  case X86::SHR8mi: NewOpc = X86::SHR8m1; break;
3808  case X86::SHR16mi: NewOpc = X86::SHR16m1; break;
3809  case X86::SHR32mi: NewOpc = X86::SHR32m1; break;
3810  case X86::SHR64mi: NewOpc = X86::SHR64m1; break;
3811  case X86::SHL8mi: NewOpc = X86::SHL8m1; break;
3812  case X86::SHL16mi: NewOpc = X86::SHL16m1; break;
3813  case X86::SHL32mi: NewOpc = X86::SHL32m1; break;
3814  case X86::SHL64mi: NewOpc = X86::SHL64m1; break;
3815  }
3816 
3817  MCInst TmpInst;
3818  TmpInst.setOpcode(NewOpc);
3819  for (int i = 0; i != X86::AddrNumOperands; ++i)
3820  TmpInst.addOperand(Inst.getOperand(i));
3821  Inst = TmpInst;
3822  return true;
3823  }
3824  case X86::INT: {
3825  // Transforms "int $3" into "int3" as a size optimization. We can't write an
3826  // instalias with an immediate operand yet.
3827  if (!Inst.getOperand(0).isImm() || Inst.getOperand(0).getImm() != 3)
3828  return false;
3829 
3830  MCInst TmpInst;
3831  TmpInst.setOpcode(X86::INT3);
3832  Inst = TmpInst;
3833  return true;
3834  }
3835  }
3836 }
3837 
3838 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
3839  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3840 
3841  switch (Inst.getOpcode()) {
3842  case X86::VGATHERDPDYrm:
3843  case X86::VGATHERDPDrm:
3844  case X86::VGATHERDPSYrm:
3845  case X86::VGATHERDPSrm:
3846  case X86::VGATHERQPDYrm:
3847  case X86::VGATHERQPDrm:
3848  case X86::VGATHERQPSYrm:
3849  case X86::VGATHERQPSrm:
3850  case X86::VPGATHERDDYrm:
3851  case X86::VPGATHERDDrm:
3852  case X86::VPGATHERDQYrm:
3853  case X86::VPGATHERDQrm:
3854  case X86::VPGATHERQDYrm:
3855  case X86::VPGATHERQDrm:
3856  case X86::VPGATHERQQYrm:
3857  case X86::VPGATHERQQrm: {
3858  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
3859  unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
3860  unsigned Index =
3861  MRI->getEncodingValue(Inst.getOperand(3 + X86::AddrIndexReg).getReg());
3862  if (Dest == Mask || Dest == Index || Mask == Index)
3863  return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
3864  "registers should be distinct");
3865  break;
3866  }
3867  case X86::VGATHERDPDZ128rm:
3868  case X86::VGATHERDPDZ256rm:
3869  case X86::VGATHERDPDZrm:
3870  case X86::VGATHERDPSZ128rm:
3871  case X86::VGATHERDPSZ256rm:
3872  case X86::VGATHERDPSZrm:
3873  case X86::VGATHERQPDZ128rm:
3874  case X86::VGATHERQPDZ256rm:
3875  case X86::VGATHERQPDZrm:
3876  case X86::VGATHERQPSZ128rm:
3877  case X86::VGATHERQPSZ256rm:
3878  case X86::VGATHERQPSZrm:
3879  case X86::VPGATHERDDZ128rm:
3880  case X86::VPGATHERDDZ256rm:
3881  case X86::VPGATHERDDZrm:
3882  case X86::VPGATHERDQZ128rm:
3883  case X86::VPGATHERDQZ256rm:
3884  case X86::VPGATHERDQZrm:
3885  case X86::VPGATHERQDZ128rm:
3886  case X86::VPGATHERQDZ256rm:
3887  case X86::VPGATHERQDZrm:
3888  case X86::VPGATHERQQZ128rm:
3889  case X86::VPGATHERQQZ256rm:
3890  case X86::VPGATHERQQZrm: {
3891  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
3892  unsigned Index =
3893  MRI->getEncodingValue(Inst.getOperand(4 + X86::AddrIndexReg).getReg());
3894  if (Dest == Index)
3895  return Warning(Ops[0]->getStartLoc(), "index and destination registers "
3896  "should be distinct");
3897  break;
3898  }
3899  case X86::V4FMADDPSrm:
3900  case X86::V4FMADDPSrmk:
3901  case X86::V4FMADDPSrmkz:
3902  case X86::V4FMADDSSrm:
3903  case X86::V4FMADDSSrmk:
3904  case X86::V4FMADDSSrmkz:
3905  case X86::V4FNMADDPSrm:
3906  case X86::V4FNMADDPSrmk:
3907  case X86::V4FNMADDPSrmkz:
3908  case X86::V4FNMADDSSrm:
3909  case X86::V4FNMADDSSrmk:
3910  case X86::V4FNMADDSSrmkz:
3911  case X86::VP4DPWSSDSrm:
3912  case X86::VP4DPWSSDSrmk:
3913  case X86::VP4DPWSSDSrmkz:
3914  case X86::VP4DPWSSDrm:
3915  case X86::VP4DPWSSDrmk:
3916  case X86::VP4DPWSSDrmkz: {
3917  unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
3919  unsigned Src2Enc = MRI->getEncodingValue(Src2);
3920  if (Src2Enc % 4 != 0) {
3922  unsigned GroupStart = (Src2Enc / 4) * 4;
3923  unsigned GroupEnd = GroupStart + 3;
3924  return Warning(Ops[0]->getStartLoc(),
3925  "source register '" + RegName + "' implicitly denotes '" +
3926  RegName.take_front(3) + Twine(GroupStart) + "' to '" +
3927  RegName.take_front(3) + Twine(GroupEnd) +
3928  "' source group");
3929  }
3930  break;
3931  }
3932  case X86::VFCMADDCPHZ128m:
3933  case X86::VFCMADDCPHZ256m:
3934  case X86::VFCMADDCPHZm:
3935  case X86::VFCMADDCPHZ128mb:
3936  case X86::VFCMADDCPHZ256mb:
3937  case X86::VFCMADDCPHZmb:
3938  case X86::VFCMADDCPHZ128mbk:
3939  case X86::VFCMADDCPHZ256mbk:
3940  case X86::VFCMADDCPHZmbk:
3941  case X86::VFCMADDCPHZ128mbkz:
3942  case X86::VFCMADDCPHZ256mbkz:
3943  case X86::VFCMADDCPHZmbkz:
3944  case X86::VFCMADDCPHZ128mk:
3945  case X86::VFCMADDCPHZ256mk:
3946  case X86::VFCMADDCPHZmk:
3947  case X86::VFCMADDCPHZ128mkz:
3948  case X86::VFCMADDCPHZ256mkz:
3949  case X86::VFCMADDCPHZmkz:
3950  case X86::VFCMADDCPHZ128r:
3951  case X86::VFCMADDCPHZ256r:
3952  case X86::VFCMADDCPHZr:
3953  case X86::VFCMADDCPHZ128rk:
3954  case X86::VFCMADDCPHZ256rk:
3955  case X86::VFCMADDCPHZrk:
3956  case X86::VFCMADDCPHZ128rkz:
3957  case X86::VFCMADDCPHZ256rkz:
3958  case X86::VFCMADDCPHZrkz:
3959  case X86::VFCMADDCPHZrb:
3960  case X86::VFCMADDCPHZrbk:
3961  case X86::VFCMADDCPHZrbkz:
3962  case X86::VFCMADDCSHZm:
3963  case X86::VFCMADDCSHZmk:
3964  case X86::VFCMADDCSHZmkz:
3965  case X86::VFCMADDCSHZr:
3966  case X86::VFCMADDCSHZrb:
3967  case X86::VFCMADDCSHZrbk:
3968  case X86::VFCMADDCSHZrbkz:
3969  case X86::VFCMADDCSHZrk:
3970  case X86::VFCMADDCSHZrkz:
3971  case X86::VFMADDCPHZ128m:
3972  case X86::VFMADDCPHZ256m:
3973  case X86::VFMADDCPHZm:
3974  case X86::VFMADDCPHZ128mb:
3975  case X86::VFMADDCPHZ256mb:
3976  case X86::VFMADDCPHZmb:
3977  case X86::VFMADDCPHZ128mbk:
3978  case X86::VFMADDCPHZ256mbk:
3979  case X86::VFMADDCPHZmbk:
3980  case X86::VFMADDCPHZ128mbkz:
3981  case X86::VFMADDCPHZ256mbkz:
3982  case X86::VFMADDCPHZmbkz:
3983  case X86::VFMADDCPHZ128mk:
3984  case X86::VFMADDCPHZ256mk:
3985  case X86::VFMADDCPHZmk:
3986  case X86::VFMADDCPHZ128mkz:
3987  case X86::VFMADDCPHZ256mkz:
3988  case X86::VFMADDCPHZmkz:
3989  case X86::VFMADDCPHZ128r:
3990  case X86::VFMADDCPHZ256r:
3991  case X86::VFMADDCPHZr:
3992  case X86::VFMADDCPHZ128rk:
3993  case X86::VFMADDCPHZ256rk:
3994  case X86::VFMADDCPHZrk:
3995  case X86::VFMADDCPHZ128rkz:
3996  case X86::VFMADDCPHZ256rkz:
3997  case X86::VFMADDCPHZrkz:
3998  case X86::VFMADDCPHZrb:
3999  case X86::VFMADDCPHZrbk:
4000  case X86::VFMADDCPHZrbkz:
4001  case X86::VFMADDCSHZm:
4002  case X86::VFMADDCSHZmk:
4003  case X86::VFMADDCSHZmkz:
4004  case X86::VFMADDCSHZr:
4005  case X86::VFMADDCSHZrb:
4006  case X86::VFMADDCSHZrbk:
4007  case X86::VFMADDCSHZrbkz:
4008  case X86::VFMADDCSHZrk:
4009  case X86::VFMADDCSHZrkz: {
4010  unsigned Dest = Inst.getOperand(0).getReg();
4011  for (unsigned i = 2; i < Inst.getNumOperands(); i++)
4012  if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
4013  return Warning(Ops[0]->getStartLoc(), "Destination register should be "
4014  "distinct from source registers");
4015  break;
4016  }
4017  case X86::VFCMULCPHZ128rm:
4018  case X86::VFCMULCPHZ256rm:
4019  case X86::VFCMULCPHZrm:
4020  case X86::VFCMULCPHZ128rmb:
4021  case X86::VFCMULCPHZ256rmb:
4022  case X86::VFCMULCPHZrmb:
4023  case X86::VFCMULCPHZ128rmbk:
4024  case X86::VFCMULCPHZ256rmbk:
4025  case X86::VFCMULCPHZrmbk:
4026  case X86::VFCMULCPHZ128rmbkz:
4027  case X86::VFCMULCPHZ256rmbkz:
4028  case X86::VFCMULCPHZrmbkz:
4029  case X86::VFCMULCPHZ128rmk:
4030  case X86::VFCMULCPHZ256rmk:
4031  case X86::VFCMULCPHZrmk:
4032  case X86::VFCMULCPHZ128rmkz:
4033  case X86::VFCMULCPHZ256rmkz:
4034  case X86::VFCMULCPHZrmkz:
4035  case X86::VFCMULCPHZ128rr:
4036  case X86::VFCMULCPHZ256rr:
4037  case X86::VFCMULCPHZrr:
4038  case X86::VFCMULCPHZ128rrk:
4039  case X86::VFCMULCPHZ256rrk:
4040  case X86::VFCMULCPHZrrk:
4041  case X86::VFCMULCPHZ128rrkz:
4042  case X86::VFCMULCPHZ256rrkz:
4043  case X86::VFCMULCPHZrrkz:
4044  case X86::VFCMULCPHZrrb:
4045  case X86::VFCMULCPHZrrbk:
4046  case X86::VFCMULCPHZrrbkz:
4047  case X86::VFCMULCSHZrm:
4048  case X86::VFCMULCSHZrmk:
4049  case X86::VFCMULCSHZrmkz:
4050  case X86::VFCMULCSHZrr:
4051  case X86::VFCMULCSHZrrb:
4052  case X86::VFCMULCSHZrrbk:
4053  case X86::VFCMULCSHZrrbkz:
4054  case X86::VFCMULCSHZrrk:
4055  case X86::VFCMULCSHZrrkz:
4056  case X86::VFMULCPHZ128rm:
4057  case X86::VFMULCPHZ256rm:
4058  case X86::VFMULCPHZrm:
4059  case X86::VFMULCPHZ128rmb:
4060  case X86::VFMULCPHZ256rmb:
4061  case X86::VFMULCPHZrmb:
4062  case X86::VFMULCPHZ128rmbk:
4063  case X86::VFMULCPHZ256rmbk:
4064  case X86::VFMULCPHZrmbk:
4065  case X86::VFMULCPHZ128rmbkz:
4066  case X86::VFMULCPHZ256rmbkz:
4067  case X86::VFMULCPHZrmbkz:
4068  case X86::VFMULCPHZ128rmk:
4069  case X86::VFMULCPHZ256rmk:
4070  case X86::VFMULCPHZrmk:
4071  case X86::VFMULCPHZ128rmkz:
4072  case X86::VFMULCPHZ256rmkz:
4073  case X86::VFMULCPHZrmkz:
4074  case X86::VFMULCPHZ128rr:
4075  case X86::VFMULCPHZ256rr:
4076  case X86::VFMULCPHZrr:
4077  case X86::VFMULCPHZ128rrk:
4078  case X86::VFMULCPHZ256rrk:
4079  case X86::VFMULCPHZrrk:
4080  case X86::VFMULCPHZ128rrkz:
4081  case X86::VFMULCPHZ256rrkz:
4082  case X86::VFMULCPHZrrkz:
4083  case X86::VFMULCPHZrrb:
4084  case X86::VFMULCPHZrrbk:
4085  case X86::VFMULCPHZrrbkz:
4086  case X86::VFMULCSHZrm:
4087  case X86::VFMULCSHZrmk:
4088  case X86::VFMULCSHZrmkz:
4089  case X86::VFMULCSHZrr:
4090  case X86::VFMULCSHZrrb:
4091  case X86::VFMULCSHZrrbk:
4092  case X86::VFMULCSHZrrbkz:
4093  case X86::VFMULCSHZrrk:
4094  case X86::VFMULCSHZrrkz: {
4095  unsigned Dest = Inst.getOperand(0).getReg();
4096  for (unsigned i = 1; i < Inst.getNumOperands(); i++)
4097  if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
4098  return Warning(Ops[0]->getStartLoc(), "Destination register should be "
4099  "distinct from source registers");
4100  break;
4101  }
4102  }
4103 
4104  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
4105  // Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to
4106  // check this with the legacy encoding, VEX/EVEX/XOP don't use REX.
4107  if ((MCID.TSFlags & X86II::EncodingMask) == 0) {
4108  MCPhysReg HReg = X86::NoRegister;
4109  bool UsesRex = MCID.TSFlags & X86II::REX_W;
4110  unsigned NumOps = Inst.getNumOperands();
4111  for (unsigned i = 0; i != NumOps; ++i) {
4112  const MCOperand &MO = Inst.getOperand(i);
4113  if (!MO.isReg())
4114  continue;
4115  unsigned Reg = MO.getReg();
4116  if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
4117  HReg = Reg;
4120  UsesRex = true;
4121  }
4122 
4123  if (UsesRex && HReg != X86::NoRegister) {
4125  return Error(Ops[0]->getStartLoc(),
4126  "can't encode '" + RegName + "' in an instruction requiring "
4127  "REX prefix");
4128  }
4129  }
4130 
4131  return false;
4132 }
4133 
4134 static const char *getSubtargetFeatureName(uint64_t Val);
4135 
4136 void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) {
4137  Warning(Loc, "Instruction may be vulnerable to LVI and "
4138  "requires manual mitigation");
4139  Note(SMLoc(), "See https://software.intel.com/"
4140  "security-software-guidance/insights/"
4141  "deep-dive-load-value-injection#specialinstructions"
4142  " for more information");
4143 }
4144 
4145 /// RET instructions and also instructions that indirect calls/jumps from memory
4146 /// combine a load and a branch within a single instruction. To mitigate these
4147 /// instructions against LVI, they must be decomposed into separate load and
4148 /// branch instructions, with an LFENCE in between. For more details, see:
4149 /// - X86LoadValueInjectionRetHardening.cpp
4150 /// - X86LoadValueInjectionIndirectThunks.cpp
4151 /// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4152 ///
4153 /// Returns `true` if a mitigation was applied or warning was emitted.
4154 void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
4155  // Information on control-flow instructions that require manual mitigation can
4156  // be found here:
4157  // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4158  switch (Inst.getOpcode()) {
4159  case X86::RET16:
4160  case X86::RET32:
4161  case X86::RET64:
4162  case X86::RETI16:
4163  case X86::RETI32:
4164  case X86::RETI64: {
4165  MCInst ShlInst, FenceInst;
4166  bool Parse32 = is32BitMode() || Code16GCC;
4167  unsigned Basereg =
4168  is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP);
4169  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
4170  auto ShlMemOp = X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
4171  /*BaseReg=*/Basereg, /*IndexReg=*/0,
4172  /*Scale=*/1, SMLoc{}, SMLoc{}, 0);
4173  ShlInst.setOpcode(X86::SHL64mi);
4174  ShlMemOp->addMemOperands(ShlInst, 5);
4175  ShlInst.addOperand(MCOperand::createImm(0));
4176  FenceInst.setOpcode(X86::LFENCE);
4177  Out.emitInstruction(ShlInst, getSTI());
4178  Out.emitInstruction(FenceInst, getSTI());
4179  return;
4180  }
4181  case X86::JMP16m:
4182  case X86::JMP32m:
4183  case X86::JMP64m:
4184  case X86::CALL16m:
4185  case X86::CALL32m:
4186  case X86::CALL64m:
4187  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4188  return;
4189  }
4190 }
4191 
4192 /// To mitigate LVI, every instruction that performs a load can be followed by
4193 /// an LFENCE instruction to squash any potential mis-speculation. There are
4194 /// some instructions that require additional considerations, and may requre
4195 /// manual mitigation. For more details, see:
4196 /// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4197 ///
4198 /// Returns `true` if a mitigation was applied or warning was emitted.
4199 void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
4200  MCStreamer &Out) {
4201  auto Opcode = Inst.getOpcode();
4202  auto Flags = Inst.getFlags();
4203  if ((Flags & X86::IP_HAS_REPEAT) || (Flags & X86::IP_HAS_REPEAT_NE)) {
4204  // Information on REP string instructions that require manual mitigation can
4205  // be found here:
4206  // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4207  switch (Opcode) {
4208  case X86::CMPSB:
4209  case X86::CMPSW:
4210  case X86::CMPSL:
4211  case X86::CMPSQ:
4212  case X86::SCASB:
4213  case X86::SCASW:
4214  case X86::SCASL:
4215  case X86::SCASQ:
4216  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4217  return;
4218  }
4219  } else if (Opcode == X86::REP_PREFIX || Opcode == X86::REPNE_PREFIX) {
4220  // If a REP instruction is found on its own line, it may or may not be
4221  // followed by a vulnerable instruction. Emit a warning just in case.
4222  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4223  return;
4224  }
4225 
4226  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
4227 
4228  // Can't mitigate after terminators or calls. A control flow change may have
4229  // already occurred.
4230  if (MCID.isTerminator() || MCID.isCall())
4231  return;
4232 
4233  // LFENCE has the mayLoad property, don't double fence.
4234  if (MCID.mayLoad() && Inst.getOpcode() != X86::LFENCE) {
4235  MCInst FenceInst;
4236  FenceInst.setOpcode(X86::LFENCE);
4237  Out.emitInstruction(FenceInst, getSTI());
4238  }
4239 }
4240 
4241 void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
4242  MCStreamer &Out) {
4243  if (LVIInlineAsmHardening &&
4244  getSTI().getFeatureBits()[X86::FeatureLVIControlFlowIntegrity])
4245  applyLVICFIMitigation(Inst, Out);
4246 
4247  Out.emitInstruction(Inst, getSTI());
4248 
4249  if (LVIInlineAsmHardening &&
4250  getSTI().getFeatureBits()[X86::FeatureLVILoadHardening])
4251  applyLVILoadHardeningMitigation(Inst, Out);
4252 }
4253 
4254 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4256  MCStreamer &Out, uint64_t &ErrorInfo,
4257  bool MatchingInlineAsm) {
4258  if (isParsingIntelSyntax())
4259  return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
4260  MatchingInlineAsm);
4261  return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
4262  MatchingInlineAsm);
4263 }
4264 
4265 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
4267  bool MatchingInlineAsm) {
4268  // FIXME: This should be replaced with a real .td file alias mechanism.
4269  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
4270  // call.
4271  const char *Repl = StringSwitch<const char *>(Op.getToken())
4272  .Case("finit", "fninit")
4273  .Case("fsave", "fnsave")
4274  .Case("fstcw", "fnstcw")
4275  .Case("fstcww", "fnstcw")
4276  .Case("fstenv", "fnstenv")
4277  .Case("fstsw", "fnstsw")
4278  .Case("fstsww", "fnstsw")
4279  .Case("fclex", "fnclex")
4280  .Default(nullptr);
4281  if (Repl) {
4282  MCInst Inst;
4283  Inst.setOpcode(X86::WAIT);
4284  Inst.setLoc(IDLoc);
4285  if (!MatchingInlineAsm)
4286  emitInstruction(Inst, Operands, Out);
4287  Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
4288  }
4289 }
4290 
4291 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
4292  const FeatureBitset &MissingFeatures,
4293  bool MatchingInlineAsm) {
4294  assert(MissingFeatures.any() && "Unknown missing feature!");
4297  OS << "instruction requires:";
4298  for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
4299  if (MissingFeatures[i])
4300  OS << ' ' << getSubtargetFeatureName(i);
4301  }
4302  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
4303 }
4304 
4306  unsigned Result = 0;
4307  X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
4308  if (Prefix.isPrefix()) {
4309  Result = Prefix.getPrefix();
4310  Operands.pop_back();
4311  }
4312  return Result;
4313 }
4314 
4315 unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4316  unsigned Opc = Inst.getOpcode();
4317  const MCInstrDesc &MCID = MII.get(Opc);
4318 
4319  if (ForcedVEXEncoding == VEXEncoding_EVEX &&
4321  return Match_Unsupported;
4322 
4323  if ((ForcedVEXEncoding == VEXEncoding_VEX ||
4324  ForcedVEXEncoding == VEXEncoding_VEX2 ||
4325  ForcedVEXEncoding == VEXEncoding_VEX3) &&
4327  return Match_Unsupported;
4328 
4329  // These instructions are only available with {vex}, {vex2} or {vex3} prefix
4330  if (MCID.TSFlags & X86II::ExplicitVEXPrefix &&
4331  (ForcedVEXEncoding != VEXEncoding_VEX &&
4332  ForcedVEXEncoding != VEXEncoding_VEX2 &&
4333  ForcedVEXEncoding != VEXEncoding_VEX3))
4334  return Match_Unsupported;
4335 
4336  return Match_Success;
4337 }
4338 
4339 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
4341  MCStreamer &Out,
4343  bool MatchingInlineAsm) {
4344  assert(!Operands.empty() && "Unexpect empty operand list!");
4345  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4346  SMRange EmptyRange = None;
4347 
4348  // First, handle aliases that expand to multiple instructions.
4349  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands,
4350  Out, MatchingInlineAsm);
4351  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4352  unsigned Prefixes = getPrefixes(Operands);
4353 
4354  MCInst Inst;
4355 
4356  // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
4357  // encoder and printer.
4358  if (ForcedVEXEncoding == VEXEncoding_VEX)
4359  Prefixes |= X86::IP_USE_VEX;
4360  else if (ForcedVEXEncoding == VEXEncoding_VEX2)
4361  Prefixes |= X86::IP_USE_VEX2;
4362  else if (ForcedVEXEncoding == VEXEncoding_VEX3)
4363  Prefixes |= X86::IP_USE_VEX3;
4364  else if (ForcedVEXEncoding == VEXEncoding_EVEX)
4365  Prefixes |= X86::IP_USE_EVEX;
4366 
4367  // Set encoded flags for {disp8} and {disp32}.
4368  if (ForcedDispEncoding == DispEncoding_Disp8)
4369  Prefixes |= X86::IP_USE_DISP8;
4370  else if (ForcedDispEncoding == DispEncoding_Disp32)
4371  Prefixes |= X86::IP_USE_DISP32;
4372 
4373  if (Prefixes)
4374  Inst.setFlags(Prefixes);
4375 
4376  // In 16-bit mode, if data32 is specified, temporarily switch to 32-bit mode
4377  // when matching the instruction.
4378  if (ForcedDataPrefix == X86::Is32Bit)
4379  SwitchMode(X86::Is32Bit);
4380  // First, try a direct match.
4381  FeatureBitset MissingFeatures;
4382  unsigned OriginalError = MatchInstruction(Operands, Inst, ErrorInfo,
4383  MissingFeatures, MatchingInlineAsm,
4384  isParsingIntelSyntax());
4385  if (ForcedDataPrefix == X86::Is32Bit) {
4386  SwitchMode(X86::Is16Bit);
4387  ForcedDataPrefix = 0;
4388  }
4389  switch (OriginalError) {
4390  default: llvm_unreachable("Unexpected match result!");
4391  case Match_Success:
4392  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4393  return true;
4394  // Some instructions need post-processing to, for example, tweak which
4395  // encoding is selected. Loop on it while changes happen so the
4396  // individual transformations can chain off each other.
4397  if (!MatchingInlineAsm)
4398  while (processInstruction(Inst, Operands))
4399  ;
4400 
4401  Inst.setLoc(IDLoc);
4402  if (!MatchingInlineAsm)
4403  emitInstruction(Inst, Operands, Out);
4404  Opcode = Inst.getOpcode();
4405  return false;
4406  case Match_InvalidImmUnsignedi4: {
4407  SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4408  if (ErrorLoc == SMLoc())
4409  ErrorLoc = IDLoc;
4410  return Error(ErrorLoc, "immediate must be an integer in range [0, 15]",
4411  EmptyRange, MatchingInlineAsm);
4412  }
4413  case Match_MissingFeature:
4414  return ErrorMissingFeature(IDLoc, MissingFeatures, MatchingInlineAsm);
4415  case Match_InvalidOperand:
4416  case Match_MnemonicFail:
4417  case Match_Unsupported:
4418  break;
4419  }
4420  if (Op.getToken().empty()) {
4421  Error(IDLoc, "instruction must have size higher than 0", EmptyRange,
4422  MatchingInlineAsm);
4423  return true;
4424  }
4425 
4426  // FIXME: Ideally, we would only attempt suffix matches for things which are
4427  // valid prefixes, and we could just infer the right unambiguous
4428  // type. However, that requires substantially more matcher support than the
4429  // following hack.
4430 
4431  // Change the operand to point to a temporary token.
4432  StringRef Base = Op.getToken();
4433  SmallString<16> Tmp;
4434  Tmp += Base;
4435  Tmp += ' ';
4436  Op.setTokenValue(Tmp);
4437 
4438  // If this instruction starts with an 'f', then it is a floating point stack
4439  // instruction. These come in up to three forms for 32-bit, 64-bit, and
4440  // 80-bit floating point, which use the suffixes s,l,t respectively.
4441  //
4442  // Otherwise, we assume that this may be an integer instruction, which comes
4443  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
4444  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
4445  // MemSize corresponding to Suffixes. { 8, 16, 32, 64 } { 32, 64, 80, 0 }
4446  const char *MemSize = Base[0] != 'f' ? "\x08\x10\x20\x40" : "\x20\x40\x50\0";
4447 
4448  // Check for the various suffix matches.
4449  uint64_t ErrorInfoIgnore;
4450  FeatureBitset ErrorInfoMissingFeatures; // Init suppresses compiler warnings.
4451  unsigned Match[4];
4452 
4453  // Some instruction like VPMULDQ is NOT the variant of VPMULD but a new one.
4454  // So we should make sure the suffix matcher only works for memory variant
4455  // that has the same size with the suffix.
4456  // FIXME: This flag is a workaround for legacy instructions that didn't
4457  // declare non suffix variant assembly.
4458  bool HasVectorReg = false;
4459  X86Operand *MemOp = nullptr;
4460  for (const auto &Op : Operands) {
4461  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4462  if (X86Op->isVectorReg())
4463  HasVectorReg = true;
4464  else if (X86Op->isMem()) {
4465  MemOp = X86Op;
4466  assert(MemOp->Mem.Size == 0 && "Memory size always 0 under ATT syntax");
4467  // Have we found an unqualified memory operand,
4468  // break. IA allows only one memory operand.
4469  break;
4470  }
4471  }
4472 
4473  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
4474  Tmp.back() = Suffixes[I];
4475  if (MemOp && HasVectorReg)
4476  MemOp->Mem.Size = MemSize[I];
4477  Match[I] = Match_MnemonicFail;
4478  if (MemOp || !HasVectorReg) {
4479  Match[I] =
4480  MatchInstruction(Operands, Inst, ErrorInfoIgnore, MissingFeatures,
4481  MatchingInlineAsm, isParsingIntelSyntax());
4482  // If this returned as a missing feature failure, remember that.
4483  if (Match[I] == Match_MissingFeature)
4484  ErrorInfoMissingFeatures = MissingFeatures;
4485  }
4486  }
4487 
4488  // Restore the old token.
4489  Op.setTokenValue(Base);
4490 
4491  // If exactly one matched, then we treat that as a successful match (and the
4492  // instruction will already have been filled in correctly, since the failing
4493  // matches won't have modified it).
4494  unsigned NumSuccessfulMatches = llvm::count(Match, Match_Success);
4495  if (NumSuccessfulMatches == 1) {
4496  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4497  return true;
4498  // Some instructions need post-processing to, for example, tweak which
4499  // encoding is selected. Loop on it while changes happen so the
4500  // individual transformations can chain off each other.
4501  if (!MatchingInlineAsm)
4502  while (processInstruction(Inst, Operands))
4503  ;
4504 
4505  Inst.setLoc(IDLoc);
4506  if (!MatchingInlineAsm)
4507  emitInstruction(Inst, Operands, Out);
4508  Opcode = Inst.getOpcode();
4509  return false;
4510  }
4511 
4512  // Otherwise, the match failed, try to produce a decent error message.
4513 
4514  // If we had multiple suffix matches, then identify this as an ambiguous
4515  // match.
4516  if (NumSuccessfulMatches > 1) {
4517  char MatchChars[4];
4518  unsigned NumMatches = 0;
4519  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
4520  if (Match[I] == Match_Success)
4521  MatchChars[NumMatches++] = Suffixes[I];
4522 
4525  OS << "ambiguous instructions require an explicit suffix (could be ";
4526  for (unsigned i = 0; i != NumMatches; ++i) {
4527  if (i != 0)
4528  OS << ", ";
4529  if (i + 1 == NumMatches)
4530  OS << "or ";
4531  OS << "'" << Base << MatchChars[i] << "'";
4532  }
4533  OS << ")";
4534  Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
4535  return true;
4536  }
4537 
4538  // Okay, we know that none of the variants matched successfully.
4539 
4540  // If all of the instructions reported an invalid mnemonic, then the original
4541  // mnemonic was invalid.
4542  if (llvm::count(Match, Match_MnemonicFail) == 4) {
4543  if (OriginalError == Match_MnemonicFail)
4544  return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
4545  Op.getLocRange(), MatchingInlineAsm);
4546 
4547  if (OriginalError == Match_Unsupported)
4548  return Error(IDLoc, "unsupported instruction", EmptyRange,
4549  MatchingInlineAsm);
4550 
4551  assert(OriginalError == Match_InvalidOperand && "Unexpected error");
4552  // Recover location info for the operand if we know which was the problem.
4553  if (ErrorInfo != ~0ULL) {
4554  if (ErrorInfo >= Operands.size())
4555  return Error(IDLoc, "too few operands for instruction", EmptyRange,
4556  MatchingInlineAsm);
4557 
4558  X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
4559  if (Operand.getStartLoc().isValid()) {
4560  SMRange OperandRange = Operand.getLocRange();
4561  return Error(Operand.getStartLoc(), "invalid operand for instruction",
4562  OperandRange, MatchingInlineAsm);
4563  }
4564  }
4565 
4566  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4567  MatchingInlineAsm);
4568  }
4569 
4570  // If one instruction matched as unsupported, report this as unsupported.
4571  if (llvm::count(Match, Match_Unsupported) == 1) {
4572  return Error(IDLoc, "unsupported instruction", EmptyRange,
4573  MatchingInlineAsm);
4574  }
4575 
4576  // If one instruction matched with a missing feature, report this as a
4577  // missing feature.
4578  if (llvm::count(Match, Match_MissingFeature) == 1) {
4579  ErrorInfo = Match_MissingFeature;
4580  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
4581  MatchingInlineAsm);
4582  }
4583 
4584  // If one instruction matched with an invalid operand, report this as an
4585  // operand failure.
4586  if (llvm::count(Match, Match_InvalidOperand) == 1) {
4587  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4588  MatchingInlineAsm);
4589  }
4590 
4591  // If all of these were an outright failure, report it in a useless way.
4592  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
4593  EmptyRange, MatchingInlineAsm);
4594  return true;
4595 }
4596 
4597 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
4599  MCStreamer &Out,
4601  bool MatchingInlineAsm) {
4602  assert(!Operands.empty() && "Unexpect empty operand list!");
4603  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4604  StringRef Mnemonic = (static_cast<X86Operand &>(*Operands[0])).getToken();
4605  SMRange EmptyRange = None;
4606  StringRef Base = (static_cast<X86Operand &>(*Operands[0])).getToken();
4607  unsigned Prefixes = getPrefixes(Operands);
4608 
4609  // First, handle aliases that expand to multiple instructions.
4610  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands, Out, MatchingInlineAsm);
4611  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4612 
4613  MCInst Inst;
4614 
4615  // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
4616  // encoder and printer.
4617  if (ForcedVEXEncoding == VEXEncoding_VEX)
4618  Prefixes |= X86::IP_USE_VEX;
4619  else if (ForcedVEXEncoding == VEXEncoding_VEX2)
4620  Prefixes |= X86::IP_USE_VEX2;
4621  else if (ForcedVEXEncoding == VEXEncoding_VEX3)
4622  Prefixes |= X86::IP_USE_VEX3;
4623  else if (ForcedVEXEncoding == VEXEncoding_EVEX)
4624  Prefixes |= X86::IP_USE_EVEX;
4625 
4626  // Set encoded flags for {disp8} and {disp32}.
4627  if (ForcedDispEncoding == DispEncoding_Disp8)
4628  Prefixes |= X86::IP_USE_DISP8;
4629  else if (ForcedDispEncoding == DispEncoding_Disp32)
4630  Prefixes |= X86::IP_USE_DISP32;
4631 
4632  if (Prefixes)
4633  Inst.setFlags(Prefixes);
4634 
4635  // Find one unsized memory operand, if present.
4636  X86Operand *UnsizedMemOp = nullptr;
4637  for (const auto &Op : Operands) {
4638  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4639  if (X86Op->isMemUnsized()) {
4640  UnsizedMemOp = X86Op;
4641  // Have we found an unqualified memory operand,
4642  // break. IA allows only one memory operand.
4643  break;
4644  }
4645  }
4646 
4647  // Allow some instructions to have implicitly pointer-sized operands. This is
4648  // compatible with gas.
4649  if (UnsizedMemOp) {
4650  static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
4651  for (const char *Instr : PtrSizedInstrs) {
4652  if (Mnemonic == Instr) {
4653  UnsizedMemOp->Mem.Size = getPointerWidth();
4654  break;
4655  }
4656  }
4657  }
4658 
4660  FeatureBitset ErrorInfoMissingFeatures;
4661  FeatureBitset MissingFeatures;
4662 
4663  // If unsized push has immediate operand we should default the default pointer
4664  // size for the size.
4665  if (Mnemonic == "push" && Operands.size() == 2) {
4666  auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
4667  if (X86Op->isImm()) {
4668  // If it's not a constant fall through and let remainder take care of it.
4669  const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
4670  unsigned Size = getPointerWidth();
4671  if (CE &&
4672  (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
4673  SmallString<16> Tmp;
4674  Tmp += Base;
4675  Tmp += (is64BitMode())
4676  ? "q"
4677  : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
4678  Op.setTokenValue(Tmp);
4679  // Do match in ATT mode to allow explicit suffix usage.
4680  Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
4681  MissingFeatures, MatchingInlineAsm,
4682  false /*isParsingIntelSyntax()*/));
4683  Op.setTokenValue(Base);
4684  }
4685  }
4686  }
4687 
4688  // If an unsized memory operand is present, try to match with each memory
4689  // operand size. In Intel assembly, the size is not part of the instruction
4690  // mnemonic.
4691  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
4692  static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
4693  for (unsigned Size : MopSizes) {
4694  UnsizedMemOp->Mem.Size = Size;
4695  uint64_t ErrorInfoIgnore;
4696  unsigned LastOpcode = Inst.getOpcode();
4697  unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
4698  MissingFeatures, MatchingInlineAsm,
4699  isParsingIntelSyntax());
4700  if (Match.empty() || LastOpcode != Inst.getOpcode())
4701  Match.push_back(M);
4702 
4703  // If this returned as a missing feature failure, remember that.
4704  if (Match.back() == Match_MissingFeature)
4705  ErrorInfoMissingFeatures = MissingFeatures;
4706  }
4707 
4708  // Restore the size of the unsized memory operand if we modified it.
4709  UnsizedMemOp->Mem.Size = 0;
4710  }
4711 
4712  // If we haven't matched anything yet, this is not a basic integer or FPU
4713  // operation. There shouldn't be any ambiguity in our mnemonic table, so try
4714  // matching with the unsized operand.
4715  if (Match.empty()) {
4716  Match.push_back(MatchInstruction(
4717  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
4718  isParsingIntelSyntax()));
4719  // If this returned as a missing feature failure, remember that.
4720  if (Match.back() == Match_MissingFeature)
4721  ErrorInfoMissingFeatures = MissingFeatures;
4722  }
4723 
4724  // Restore the size of the unsized memory operand if we modified it.
4725  if (UnsizedMemOp)
4726  UnsizedMemOp->Mem.Size = 0;
4727 
4728  // If it's a bad mnemonic, all results will be the same.
4729  if (Match.back() == Match_MnemonicFail) {
4730  return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
4731  Op.getLocRange(), MatchingInlineAsm);
4732  }
4733 
4734  unsigned NumSuccessfulMatches = llvm::count(Match, Match_Success);
4735 
4736  // If matching was ambiguous and we had size information from the frontend,
4737  // try again with that. This handles cases like "movxz eax, m8/m16".
4738  if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
4739  UnsizedMemOp->getMemFrontendSize()) {
4740  UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
4741  unsigned M = MatchInstruction(
4742  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
4743  isParsingIntelSyntax());
4744  if (M == Match_Success)
4745  NumSuccessfulMatches = 1;
4746 
4747  // Add a rewrite that encodes the size information we used from the
4748  // frontend.
4749  InstInfo->AsmRewrites->emplace_back(
4750  AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
4751  /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
4752  }
4753 
4754  // If exactly one matched, then we treat that as a successful match (and the
4755  // instruction will already have been filled in correctly, since the failing
4756  // matches won't have modified it).
4757  if (NumSuccessfulMatches == 1) {
4758  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4759  return true;
4760  // Some instructions need post-processing to, for example, tweak which
4761  // encoding is selected. Loop on it while changes happen so the individual
4762  // transformations can chain off each other.
4763  if (!MatchingInlineAsm)
4764  while (processInstruction(Inst, Operands))
4765  ;
4766  Inst.setLoc(IDLoc);
4767  if (!MatchingInlineAsm)
4768  emitInstruction(Inst, Operands, Out);
4769  Opcode = Inst.getOpcode();
4770  return false;
4771  } else if (NumSuccessfulMatches > 1) {
4772  assert(UnsizedMemOp &&
4773  "multiple matches only possible with unsized memory operands");
4774  return Error(UnsizedMemOp->getStartLoc(),
4775  "ambiguous operand size for instruction '" + Mnemonic + "\'",
4776  UnsizedMemOp->getLocRange());
4777  }
4778 
4779  // If one instruction matched as unsupported, report this as unsupported.
4780  if (llvm::count(Match, Match_Unsupported) == 1) {
4781  return Error(IDLoc, "unsupported instruction", EmptyRange,
4782  MatchingInlineAsm);
4783  }
4784 
4785  // If one instruction matched with a missing feature, report this as a
4786  // missing feature.
4787  if (llvm::count(Match, Match_MissingFeature) == 1) {
4788  ErrorInfo = Match_MissingFeature;
4789  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
4790  MatchingInlineAsm);
4791  }
4792 
4793  // If one instruction matched with an invalid operand, report this as an
4794  // operand failure.
4795  if (llvm::count(Match, Match_InvalidOperand) == 1) {
4796  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4797  MatchingInlineAsm);
4798  }
4799 
4800  if (llvm::count(Match, Match_InvalidImmUnsignedi4) == 1) {
4801  SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4802  if (ErrorLoc == SMLoc())
4803  ErrorLoc = IDLoc;
4804  return Error(ErrorLoc, "immediate must be an integer in range [0, 15]",
4805  EmptyRange, MatchingInlineAsm);
4806  }
4807 
4808  // If all of these were an outright failure, report it in a useless way.
4809  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
4810  MatchingInlineAsm);
4811 }
4812 
4813 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
4814  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
4815 }
4816 
4817 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
4818  MCAsmParser &Parser = getParser();
4819  StringRef IDVal = DirectiveID.getIdentifier();
4820  if (IDVal.startswith(".arch"))
4821  return parseDirectiveArch();
4822  if (IDVal.startswith(".code"))
4823  return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
4824  else if (IDVal.startswith(".att_syntax")) {
4825  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4826  if (Parser.getTok().getString() == "prefix")
4827  Parser.Lex();
4828  else if (Parser.getTok().getString() == "noprefix")
4829  return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
4830  "supported: registers must have a "
4831  "'%' prefix in .att_syntax");
4832  }
4833  getParser().setAssemblerDialect(0);
4834  return false;
4835  } else if (IDVal.startswith(".intel_syntax")) {
4836  getParser().setAssemblerDialect(1);
4837  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4838  if (Parser.getTok().getString() == "noprefix")
4839  Parser.Lex();
4840  else if (Parser.getTok().getString() == "prefix")
4841  return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
4842  "supported: registers must not have "
4843  "a '%' prefix in .intel_syntax");
4844  }
4845  return false;
4846  } else if (IDVal == ".nops")
4847  return parseDirectiveNops(DirectiveID.getLoc());
4848  else if (IDVal == ".even")
4849  return parseDirectiveEven(DirectiveID.getLoc());
4850  else if (IDVal == ".cv_fpo_proc")
4851  return parseDirectiveFPOProc(DirectiveID.getLoc());
4852  else if (IDVal == ".cv_fpo_setframe")
4853  return parseDirectiveFPOSetFrame(DirectiveID.getLoc());
4854  else if (IDVal == ".cv_fpo_pushreg")
4855  return parseDirectiveFPOPushReg(DirectiveID.getLoc());
4856  else if (IDVal == ".cv_fpo_stackalloc")
4857  return parseDirectiveFPOStackAlloc(DirectiveID.getLoc());
4858  else if (IDVal == ".cv_fpo_stackalign")
4859  return parseDirectiveFPOStackAlign(DirectiveID.getLoc());
4860  else if (IDVal == ".cv_fpo_endprologue")
4861  return parseDirectiveFPOEndPrologue(DirectiveID.getLoc());
4862  else if (IDVal == ".cv_fpo_endproc")
4863  return parseDirectiveFPOEndProc(DirectiveID.getLoc());
4864  else if (IDVal == ".seh_pushreg" ||
4865  (Parser.isParsingMasm() && IDVal.equals_insensitive(".pushreg")))
4866  return parseDirectiveSEHPushReg(DirectiveID.getLoc());
4867  else if (IDVal == ".seh_setframe" ||
4868  (Parser.isParsingMasm() && IDVal.equals_insensitive(".setframe")))
4869  return parseDirectiveSEHSetFrame(DirectiveID.getLoc());
4870  else if (IDVal == ".seh_savereg" ||
4871  (Parser.isParsingMasm() && IDVal.equals_insensitive(".savereg")))
4872  return parseDirectiveSEHSaveReg(DirectiveID.getLoc());
4873  else if (IDVal == ".seh_savexmm" ||
4874  (Parser.isParsingMasm() && IDVal.equals_insensitive(".savexmm128")))
4875  return parseDirectiveSEHSaveXMM(DirectiveID.getLoc());
4876  else if (IDVal == ".seh_pushframe" ||
4877  (Parser.isParsingMasm() && IDVal.equals_insensitive(".pushframe")))
4878  return parseDirectiveSEHPushFrame(DirectiveID.getLoc());
4879 
4880  return true;
4881 }
4882 
4883 bool X86AsmParser::parseDirectiveArch() {
4884  // Ignore .arch for now.
4885  getParser().parseStringToEndOfStatement();
4886  return false;
4887 }
4888 
4889 /// parseDirectiveNops
4890 /// ::= .nops size[, control]
4891 bool X86AsmParser::parseDirectiveNops(SMLoc L) {
4892  int64_t NumBytes = 0, Control = 0;
4893  SMLoc NumBytesLoc, ControlLoc;
4894  const MCSubtargetInfo& STI = getSTI();
4895  NumBytesLoc = getTok().getLoc();
4896  if (getParser().checkForValidSection() ||
4897  getParser().parseAbsoluteExpression(NumBytes))
4898  return true;
4899 
4900  if (parseOptionalToken(AsmToken::Comma)) {
4901  ControlLoc = getTok().getLoc();
4902  if (getParser().parseAbsoluteExpression(Control))
4903  return true;
4904  }
4905  if (getParser().parseToken(AsmToken::EndOfStatement,
4906  "unexpected token in '.nops' directive"))
4907  return true;
4908 
4909  if (NumBytes <= 0) {
4910  Error(NumBytesLoc, "'.nops' directive with non-positive size");
4911  return false;
4912  }
4913 
4914  if (Control < 0) {
4915  Error(ControlLoc, "'.nops' directive with negative NOP size");
4916  return false;
4917  }
4918 
4919  /// Emit nops
4920  getParser().getStreamer().emitNops(NumBytes, Control, L, STI);
4921 
4922  return false;
4923 }
4924 
4925 /// parseDirectiveEven
4926 /// ::= .even
4927 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
4928  if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
4929  return false;
4930 
4931  const MCSection *Section = getStreamer().getCurrentSectionOnly();
4932  if (!Section) {
4933  getStreamer().initSections(false, getSTI());
4934  Section = getStreamer().getCurrentSectionOnly();
4935  }
4936  if (Section->useCodeAlign())
4937  getStreamer().emitCodeAlignment(2, &getSTI(), 0);
4938  else
4939  getStreamer().emitValueToAlignment(2, 0, 1, 0);
4940  return false;
4941 }
4942 
4943 /// ParseDirectiveCode
4944 /// ::= .code16 | .code32 | .code64
4945 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
4946  MCAsmParser &Parser = getParser();
4947  Code16GCC = false;
4948  if (IDVal == ".code16") {
4949  Parser.Lex();
4950  if (!is16BitMode()) {
4951  SwitchMode(X86::Is16Bit);
4952  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
4953  }
4954  } else if (IDVal == ".code16gcc") {
4955  // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
4956  Parser.Lex();
4957  Code16GCC = true;
4958  if (!is16BitMode()) {
4959  SwitchMode(X86::Is16Bit);
4960  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
4961  }
4962  } else if (IDVal == ".code32") {
4963  Parser.Lex();
4964  if (!is32BitMode()) {
4965  SwitchMode(X86::Is32Bit);
4966  getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
4967  }
4968  } else if (IDVal == ".code64") {
4969  Parser.Lex();
4970  if (!is64BitMode()) {
4971  SwitchMode(X86::Is64Bit);
4972  getParser().getStreamer().emitAssemblerFlag(MCAF_Code64);
4973  }
4974  } else {
4975  Error(L, "unknown directive " + IDVal);
4976  return false;
4977  }
4978 
4979  return false;
4980 }
4981 
4982 // .cv_fpo_proc foo
4983 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
4984  MCAsmParser &Parser = getParser();
4985  StringRef ProcName;
4986  int64_t ParamsSize;
4987  if (Parser.parseIdentifier(ProcName))
4988  return Parser.TokError("expected symbol name");
4989  if (Parser.parseIntToken(ParamsSize, "expected parameter byte count"))
4990  return true;
4991  if (!isUIntN(32, ParamsSize))
4992  return Parser.TokError("parameters size out of range");
4993  if (parseEOL())
4994  return true;
4995  MCSymbol *ProcSym = getContext().getOrCreateSymbol(ProcName);
4996  return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
4997 }
4998 
4999 // .cv_fpo_setframe ebp
5000 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
5001  unsigned Reg;
5002  SMLoc DummyLoc;
5003  if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
5004  return true;
5005  return getTargetStreamer().emitFPOSetFrame(Reg, L);
5006 }
5007 
5008 // .cv_fpo_pushreg ebx
5009 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
5010  unsigned Reg;
5011  SMLoc DummyLoc;
5012  if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
5013  return true;
5014  return getTargetStreamer().emitFPOPushReg(Reg, L);
5015 }
5016 
5017 // .cv_fpo_stackalloc 20
5018 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
5019  MCAsmParser &Parser = getParser();
5020  int64_t Offset;
5021  if (Parser.parseIntToken(Offset, "expected offset") || parseEOL())
5022  return true;
5023  return getTargetStreamer().emitFPOStackAlloc(Offset, L);
5024 }
5025 
5026 // .cv_fpo_stackalign 8
5027 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
5028  MCAsmParser &Parser = getParser();
5029  int64_t Offset;
5030  if (Parser.parseIntToken(Offset, "expected offset") || parseEOL())
5031  return true;
5032  return getTargetStreamer().emitFPOStackAlign(Offset, L);
5033 }
5034 
5035 // .cv_fpo_endprologue
5036 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
5037  MCAsmParser &Parser = getParser();
5038  if (Parser.parseEOL())
5039  return true;
5040  return getTargetStreamer().emitFPOEndPrologue(L);
5041 }
5042 
5043 // .cv_fpo_endproc
5044 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
5045  MCAsmParser &Parser = getParser();
5046  if (Parser.parseEOL())
5047  return true;
5048  return getTargetStreamer().emitFPOEndProc(L);
5049 }
5050 
5051 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
5052  unsigned &RegNo) {
5053  SMLoc startLoc = getLexer().getLoc();
5054  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
5055 
5056  // Try parsing the argument as a register first.
5057  if (getLexer().getTok().isNot(AsmToken::Integer)) {
5058  SMLoc endLoc;
5059  if (ParseRegister(RegNo, startLoc, endLoc))
5060  return true;
5061 
5062  if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) {
5063  return Error(startLoc,
5064  "register is not supported for use with this directive");
5065  }
5066  } else {
5067  // Otherwise, an integer number matching the encoding of the desired
5068  // register may appear.
5069  int64_t EncodedReg;
5070  if (getParser().parseAbsoluteExpression(EncodedReg))
5071  return true;
5072 
5073  // The SEH register number is the same as the encoding register number. Map
5074  // from the encoding back to the LLVM register number.
5075  RegNo = 0;
5076  for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
5077  if (MRI->getEncodingValue(Reg) == EncodedReg) {
5078  RegNo = Reg;
5079  break;
5080  }
5081  }
5082  if (RegNo == 0) {
5083  return Error(startLoc,
5084  "incorrect register number for use with this directive");
5085  }
5086  }
5087 
5088  return false;
5089 }
5090 
5091 bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
5092  unsigned Reg = 0;
5093  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5094  return true;
5095 
5096  if (getLexer().isNot(AsmToken::EndOfStatement))
5097  return TokError("unexpected token in directive");
5098 
5099  getParser().Lex();
5100  getStreamer().EmitWinCFIPushReg(Reg, Loc);
5101  return false;
5102 }
5103 
5104 bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
5105  unsigned Reg = 0;
5106  int64_t Off;
5107  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5108  return true;
5109  if (getLexer().isNot(AsmToken::Comma))
5110  return TokError("you must specify a stack pointer offset");
5111 
5112  getParser().Lex();
5113  if (getParser().parseAbsoluteExpression(Off))
5114  return true;
5115 
5116  if (getLexer().isNot(AsmToken::EndOfStatement))
5117  return TokError("unexpected token in directive");
5118 
5119  getParser().Lex();
5120  getStreamer().EmitWinCFISetFrame(Reg, Off, Loc);
5121  return false;
5122 }
5123 
5124 bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
5125  unsigned Reg = 0;
5126  int64_t Off;
5127  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5128  return true;
5129  if (getLexer().isNot(AsmToken::Comma))
5130  return TokError("you must specify an offset on the stack");
5131 
5132  getParser().Lex();
5133  if (getParser().parseAbsoluteExpression(Off))
5134  return true;
5135 
5136  if (getLexer().isNot(AsmToken::EndOfStatement))
5137  return TokError("unexpected token in directive");
5138 
5139  getParser().Lex();
5140  getStreamer().EmitWinCFISaveReg(Reg, Off, Loc);
5141  return false;
5142 }
5143 
5144 bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) {
5145  unsigned Reg = 0;
5146  int64_t Off;
5147  if (parseSEHRegisterNumber(X86::VR128XRegClassID, Reg))
5148  return true;
5149  if (getLexer().isNot(AsmToken::Comma))
5150  return TokError("you must specify an offset on the stack");
5151 
5152  getParser().Lex();
5153  if (getParser().parseAbsoluteExpression(Off))
5154  return true;
5155 
5156  if (getLexer().isNot(AsmToken::EndOfStatement))
5157  return TokError("unexpected token in directive");
5158 
5159  getParser().Lex();
5160  getStreamer().EmitWinCFISaveXMM(Reg, Off, Loc);
5161  return false;
5162 }
5163 
5164 bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) {
5165  bool Code = false;
5166  StringRef CodeID;
5167  if (getLexer().is(AsmToken::At)) {
5168  SMLoc startLoc = getLexer().getLoc();
5169  getParser().Lex();
5170  if (!getParser().parseIdentifier(CodeID)) {
5171  if (CodeID != "code")
5172  return Error(startLoc, "expected @code");
5173  Code = true;
5174  }
5175  }
5176 
5177  if (getLexer().isNot(AsmToken::EndOfStatement))
5178  return TokError("unexpected token in directive");
5179 
5180  getParser().Lex();
5181  getStreamer().EmitWinCFIPushFrame(Code, Loc);
5182  return false;
5183 }
5184 
5185 // Force static initialization.
5189 }
5190 
5191 #define GET_REGISTER_MATCHER
5192 #define GET_MATCHER_IMPLEMENTATION
5193 #define GET_SUBTARGET_FEATURE_NAME
5194 #include "X86GenAsmMatcher.inc"
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::MCTargetStreamer::getStreamer
MCStreamer & getStreamer()
Definition: MCStreamer.h:101
checkScale
static bool checkScale(unsigned Scale, StringRef &ErrMsg)
Definition: X86AsmParser.cpp:49
i
i
Definition: README.txt:29
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
llvm::StringRef::back
LLVM_NODISCARD char back() const
back - Get the last character in the string.
Definition: StringRef.h:168
llvm::AsmFieldInfo::Offset
unsigned Offset
Definition: MCAsmParser.h:105
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:286
llvm::MCAsmParser::Error
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:99
getSubtargetFeatureName
static const char * getSubtargetFeatureName(uint64_t Val)
llvm::X86Operand::getEndLoc
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:101
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::X86Operand::CreateMem
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0, bool UseUpRegs=false, bool MaybeDirectBranchDest=true)
Create an absolute memory operand.
Definition: X86Operand.h:682
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::AsmToken::is
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
llvm::X86Operand::Mem
struct MemOp Mem
Definition: X86Operand.h:86
llvm::MCAsmLexer
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:37
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:160
llvm::pdb::PDB_DataKind::Member
@ Member
llvm::StringRef::endswith
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:297
llvm::X86::TO_POS_INF
@ TO_POS_INF
Definition: X86BaseInfo.h:49
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::AsmToken::LBrac
@ LBrac
Definition: MCAsmMacro.h:48
Note
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles Note
Definition: README.txt:239
llvm::AsmToken::Dot
@ Dot
Definition: MCAsmMacro.h:49
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
llvm::AsmToken::EndOfStatement
@ EndOfStatement
Definition: MCAsmMacro.h:42
llvm::X86Operand::isMem8
bool isMem8() const
Definition: X86Operand.h:309
llvm::MCAsmParser::parseEOL
bool parseEOL()
Definition: MCAsmParser.cpp:47
llvm::AsmToken::getIntVal
int64_t getIntVal() const
Definition: MCAsmMacro.h:115
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:60
llvm::X86::COND_BE
@ COND_BE
Definition: X86BaseInfo.h:87
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::tgtok::Code
@ Code
Definition: TGLexer.h:50
MCParsedAsmOperand.h
llvm::MCAsmParser::parseIdentifier
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents.
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
CH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference CH
Definition: README-X86-64.txt:44
llvm::X86::COND_P
@ COND_P
Definition: X86BaseInfo.h:91
llvm::X86::COND_GE
@ COND_GE
Definition: X86BaseInfo.h:94
llvm::MCSymbol::isUndefined
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:252
llvm::pdb::PDB_BuiltinType::Variant
@ Variant
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MemOp
Definition: TargetLowering.h:111
llvm::X86::COND_L
@ COND_L
Definition: X86BaseInfo.h:93
llvm::X86::IP_HAS_LOCK
@ IP_HAS_LOCK
Definition: X86BaseInfo.h:62
startswith
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:28
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::X86::IP_USE_DISP8
@ IP_USE_DISP8
Definition: X86BaseInfo.h:68
llvm::AsmToken::Integer
@ Integer
Definition: MCAsmMacro.h:32
llvm::MCAsmParser::parseOptionalToken
bool parseOptionalToken(AsmToken::TokenKind T)
Attempt to parse and consume token, returning true on success.
Definition: MCAsmParser.cpp:78
llvm::AsmTypeInfo::Name
StringRef Name
Definition: MCAsmParser.h:97
llvm::FenceInst
An instruction for ordering other memory operations.
Definition: Instructions.h:445
llvm::X86Operand::isMem
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:305
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::InlineAsmIdentifierInfo
Definition: MCAsmParser.h:37
STLExtras.h
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:654
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::X86::CondCode
CondCode
Definition: X86BaseInfo.h:80
llvm::InlineAsmIdentifierInfo::IK_EnumVal
@ IK_EnumVal
Definition: MCAsmParser.h:41
llvm::StringRef::slice
LLVM_NODISCARD StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:732
llvm::X86::COND_INVALID
@ COND_INVALID
Definition: X86BaseInfo.h:107
llvm::getX86SubSuperRegisterOrZero
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:740
getSym
static ModuleSymbolTable::Symbol getSym(DataRefImpl &Symb)
Definition: IRObjectFile.cpp:37
MCAsmParser.h
llvm::X86II::VEX
@ VEX
Definition: X86BaseInfo.h:908
llvm::X86::COND_S
@ COND_S
Definition: X86BaseInfo.h:89
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
MCTargetAsmParser.h
llvm::X86::IP_HAS_NOTRACK
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:63
llvm::X86Operand::isReg
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:478
llvm::MCAsmParser::parseAbsoluteExpression
virtual bool parseAbsoluteExpression(int64_t &Res)=0
Parse an expression which must evaluate to an absolute value.
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
llvm::X86::COND_O
@ COND_O
Definition: X86BaseInfo.h:81
llvm::X86Operand::CreatePrefix
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:660
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::AsmToken::Minus
@ Minus
Definition: MCAsmMacro.h:45
llvm::ARMBuildAttrs::Section
@ Section
Legacy Tags.
Definition: ARMBuildAttributes.h:82
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:611
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
CommandLine.h
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:201
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::AsmToken::Dollar
@ Dollar
Definition: MCAsmMacro.h:49
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1366
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::MCAsmParser::parseExpression
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1338
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:127
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
SmallString.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:749
getPrefixes
static unsigned getPrefixes(OperandVector &Operands)
Definition: X86AsmParser.cpp:4305
llvm::AsmToken::GreaterGreater
@ GreaterGreater
Definition: MCAsmMacro.h:54
llvm::AsmTypeInfo::Size
unsigned Size
Definition: MCAsmParser.h:98
llvm::X86II::EncodingMask
@ EncodingMask
Definition: X86BaseInfo.h:905
Twine.h
llvm::MCAsmParser::parseIntToken
bool parseIntToken(int64_t &V, const Twine &ErrMsg)
Definition: MCAsmParser.cpp:70
llvm::X86::IP_USE_EVEX
@ IP_USE_EVEX
Definition: X86BaseInfo.h:67
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::AsmTypeInfo
Definition: MCAsmParser.h:96
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::X86II::isX86_64ExtendedReg
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1185
llvm::MCAF_Code16
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:54
MCInst.h
false
Definition: StackSlotColoring.cpp:141
llvm::MCInstrDesc::isTerminator
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:298
check
#define check(cond)
llvm::MCSymbol::getVariableValue
const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
Definition: MCSymbol.h:298
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::dwarf::toStringRef
StringRef toStringRef(const Optional< DWARFFormValue > &V, StringRef Default={})
Take an optional DWARFFormValue and try to extract a string value from it.
Definition: DWARFFormValue.h:193
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target desc