LLVM  14.0.0git
X86AsmParser.cpp
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1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "MCTargetDesc/X86MCExpr.h"
14 #include "X86AsmParserCommon.h"
15 #include "X86Operand.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallString.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSection.h"
31 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSymbol.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/SourceMgr.h"
39 #include <algorithm>
40 #include <memory>
41 
42 using namespace llvm;
43 
45  "x86-experimental-lvi-inline-asm-hardening",
46  cl::desc("Harden inline assembly code that may be vulnerable to Load Value"
47  " Injection (LVI). This feature is experimental."), cl::Hidden);
48 
49 static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
50  if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
51  ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
52  return true;
53  }
54  return false;
55 }
56 
57 namespace {
58 
59 static const char OpPrecedence[] = {
60  0, // IC_OR
61  1, // IC_XOR
62  2, // IC_AND
63  4, // IC_LSHIFT
64  4, // IC_RSHIFT
65  5, // IC_PLUS
66  5, // IC_MINUS
67  6, // IC_MULTIPLY
68  6, // IC_DIVIDE
69  6, // IC_MOD
70  7, // IC_NOT
71  8, // IC_NEG
72  9, // IC_RPAREN
73  10, // IC_LPAREN
74  0, // IC_IMM
75  0, // IC_REGISTER
76  3, // IC_EQ
77  3, // IC_NE
78  3, // IC_LT
79  3, // IC_LE
80  3, // IC_GT
81  3 // IC_GE
82 };
83 
84 class X86AsmParser : public MCTargetAsmParser {
85  ParseInstructionInfo *InstInfo;
86  bool Code16GCC;
87  unsigned ForcedDataPrefix = 0;
88 
89  enum VEXEncoding {
90  VEXEncoding_Default,
91  VEXEncoding_VEX,
92  VEXEncoding_VEX2,
93  VEXEncoding_VEX3,
94  VEXEncoding_EVEX,
95  };
96 
97  VEXEncoding ForcedVEXEncoding = VEXEncoding_Default;
98 
99  enum DispEncoding {
100  DispEncoding_Default,
101  DispEncoding_Disp8,
102  DispEncoding_Disp32,
103  };
104 
105  DispEncoding ForcedDispEncoding = DispEncoding_Default;
106 
107 private:
108  SMLoc consumeToken() {
109  MCAsmParser &Parser = getParser();
110  SMLoc Result = Parser.getTok().getLoc();
111  Parser.Lex();
112  return Result;
113  }
114 
115  X86TargetStreamer &getTargetStreamer() {
116  assert(getParser().getStreamer().getTargetStreamer() &&
117  "do not have a target streamer");
118  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
119  return static_cast<X86TargetStreamer &>(TS);
120  }
121 
122  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
123  uint64_t &ErrorInfo, FeatureBitset &MissingFeatures,
124  bool matchingInlineAsm, unsigned VariantID = 0) {
125  // In Code16GCC mode, match as 32-bit.
126  if (Code16GCC)
127  SwitchMode(X86::Mode32Bit);
128  unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
129  MissingFeatures, matchingInlineAsm,
130  VariantID);
131  if (Code16GCC)
132  SwitchMode(X86::Mode16Bit);
133  return rv;
134  }
135 
136  enum InfixCalculatorTok {
137  IC_OR = 0,
138  IC_XOR,
139  IC_AND,
140  IC_LSHIFT,
141  IC_RSHIFT,
142  IC_PLUS,
143  IC_MINUS,
144  IC_MULTIPLY,
145  IC_DIVIDE,
146  IC_MOD,
147  IC_NOT,
148  IC_NEG,
149  IC_RPAREN,
150  IC_LPAREN,
151  IC_IMM,
152  IC_REGISTER,
153  IC_EQ,
154  IC_NE,
155  IC_LT,
156  IC_LE,
157  IC_GT,
158  IC_GE
159  };
160 
161  enum IntelOperatorKind {
162  IOK_INVALID = 0,
163  IOK_LENGTH,
164  IOK_SIZE,
165  IOK_TYPE,
166  };
167 
168  enum MasmOperatorKind {
169  MOK_INVALID = 0,
170  MOK_LENGTHOF,
171  MOK_SIZEOF,
172  MOK_TYPE,
173  };
174 
175  class InfixCalculator {
176  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
177  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
178  SmallVector<ICToken, 4> PostfixStack;
179 
180  bool isUnaryOperator(InfixCalculatorTok Op) const {
181  return Op == IC_NEG || Op == IC_NOT;
182  }
183 
184  public:
185  int64_t popOperand() {
186  assert (!PostfixStack.empty() && "Poped an empty stack!");
187  ICToken Op = PostfixStack.pop_back_val();
188  if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
189  return -1; // The invalid Scale value will be caught later by checkScale
190  return Op.second;
191  }
192  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
193  assert ((Op == IC_IMM || Op == IC_REGISTER) &&
194  "Unexpected operand!");
195  PostfixStack.push_back(std::make_pair(Op, Val));
196  }
197 
198  void popOperator() { InfixOperatorStack.pop_back(); }
199  void pushOperator(InfixCalculatorTok Op) {
200  // Push the new operator if the stack is empty.
201  if (InfixOperatorStack.empty()) {
202  InfixOperatorStack.push_back(Op);
203  return;
204  }
205 
206  // Push the new operator if it has a higher precedence than the operator
207  // on the top of the stack or the operator on the top of the stack is a
208  // left parentheses.
209  unsigned Idx = InfixOperatorStack.size() - 1;
210  InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
211  if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
212  InfixOperatorStack.push_back(Op);
213  return;
214  }
215 
216  // The operator on the top of the stack has higher precedence than the
217  // new operator.
218  unsigned ParenCount = 0;
219  while (1) {
220  // Nothing to process.
221  if (InfixOperatorStack.empty())
222  break;
223 
224  Idx = InfixOperatorStack.size() - 1;
225  StackOp = InfixOperatorStack[Idx];
226  if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
227  break;
228 
229  // If we have an even parentheses count and we see a left parentheses,
230  // then stop processing.
231  if (!ParenCount && StackOp == IC_LPAREN)
232  break;
233 
234  if (StackOp == IC_RPAREN) {
235  ++ParenCount;
236  InfixOperatorStack.pop_back();
237  } else if (StackOp == IC_LPAREN) {
238  --ParenCount;
239  InfixOperatorStack.pop_back();
240  } else {
241  InfixOperatorStack.pop_back();
242  PostfixStack.push_back(std::make_pair(StackOp, 0));
243  }
244  }
245  // Push the new operator.
246  InfixOperatorStack.push_back(Op);
247  }
248 
249  int64_t execute() {
250  // Push any remaining operators onto the postfix stack.
251  while (!InfixOperatorStack.empty()) {
252  InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
253  if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
254  PostfixStack.push_back(std::make_pair(StackOp, 0));
255  }
256 
257  if (PostfixStack.empty())
258  return 0;
259 
260  SmallVector<ICToken, 16> OperandStack;
261  for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
262  ICToken Op = PostfixStack[i];
263  if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
264  OperandStack.push_back(Op);
265  } else if (isUnaryOperator(Op.first)) {
266  assert (OperandStack.size() > 0 && "Too few operands.");
267  ICToken Operand = OperandStack.pop_back_val();
268  assert (Operand.first == IC_IMM &&
269  "Unary operation with a register!");
270  switch (Op.first) {
271  default:
272  report_fatal_error("Unexpected operator!");
273  break;
274  case IC_NEG:
275  OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
276  break;
277  case IC_NOT:
278  OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
279  break;
280  }
281  } else {
282  assert (OperandStack.size() > 1 && "Too few operands.");
283  int64_t Val;
284  ICToken Op2 = OperandStack.pop_back_val();
285  ICToken Op1 = OperandStack.pop_back_val();
286  switch (Op.first) {
287  default:
288  report_fatal_error("Unexpected operator!");
289  break;
290  case IC_PLUS:
291  Val = Op1.second + Op2.second;
292  OperandStack.push_back(std::make_pair(IC_IMM, Val));
293  break;
294  case IC_MINUS:
295  Val = Op1.second - Op2.second;
296  OperandStack.push_back(std::make_pair(IC_IMM, Val));
297  break;
298  case IC_MULTIPLY:
299  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
300  "Multiply operation with an immediate and a register!");
301  Val = Op1.second * Op2.second;
302  OperandStack.push_back(std::make_pair(IC_IMM, Val));
303  break;
304  case IC_DIVIDE:
305  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
306  "Divide operation with an immediate and a register!");
307  assert (Op2.second != 0 && "Division by zero!");
308  Val = Op1.second / Op2.second;
309  OperandStack.push_back(std::make_pair(IC_IMM, Val));
310  break;
311  case IC_MOD:
312  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
313  "Modulo operation with an immediate and a register!");
314  Val = Op1.second % Op2.second;
315  OperandStack.push_back(std::make_pair(IC_IMM, Val));
316  break;
317  case IC_OR:
318  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
319  "Or operation with an immediate and a register!");
320  Val = Op1.second | Op2.second;
321  OperandStack.push_back(std::make_pair(IC_IMM, Val));
322  break;
323  case IC_XOR:
324  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
325  "Xor operation with an immediate and a register!");
326  Val = Op1.second ^ Op2.second;
327  OperandStack.push_back(std::make_pair(IC_IMM, Val));
328  break;
329  case IC_AND:
330  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
331  "And operation with an immediate and a register!");
332  Val = Op1.second & Op2.second;
333  OperandStack.push_back(std::make_pair(IC_IMM, Val));
334  break;
335  case IC_LSHIFT:
336  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
337  "Left shift operation with an immediate and a register!");
338  Val = Op1.second << Op2.second;
339  OperandStack.push_back(std::make_pair(IC_IMM, Val));
340  break;
341  case IC_RSHIFT:
342  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
343  "Right shift operation with an immediate and a register!");
344  Val = Op1.second >> Op2.second;
345  OperandStack.push_back(std::make_pair(IC_IMM, Val));
346  break;
347  case IC_EQ:
348  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
349  "Equals operation with an immediate and a register!");
350  Val = (Op1.second == Op2.second) ? -1 : 0;
351  OperandStack.push_back(std::make_pair(IC_IMM, Val));
352  break;
353  case IC_NE:
354  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
355  "Not-equals operation with an immediate and a register!");
356  Val = (Op1.second != Op2.second) ? -1 : 0;
357  OperandStack.push_back(std::make_pair(IC_IMM, Val));
358  break;
359  case IC_LT:
360  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
361  "Less-than operation with an immediate and a register!");
362  Val = (Op1.second < Op2.second) ? -1 : 0;
363  OperandStack.push_back(std::make_pair(IC_IMM, Val));
364  break;
365  case IC_LE:
366  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
367  "Less-than-or-equal operation with an immediate and a "
368  "register!");
369  Val = (Op1.second <= Op2.second) ? -1 : 0;
370  OperandStack.push_back(std::make_pair(IC_IMM, Val));
371  break;
372  case IC_GT:
373  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
374  "Greater-than operation with an immediate and a register!");
375  Val = (Op1.second > Op2.second) ? -1 : 0;
376  OperandStack.push_back(std::make_pair(IC_IMM, Val));
377  break;
378  case IC_GE:
379  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
380  "Greater-than-or-equal operation with an immediate and a "
381  "register!");
382  Val = (Op1.second >= Op2.second) ? -1 : 0;
383  OperandStack.push_back(std::make_pair(IC_IMM, Val));
384  break;
385  }
386  }
387  }
388  assert (OperandStack.size() == 1 && "Expected a single result.");
389  return OperandStack.pop_back_val().second;
390  }
391  };
392 
393  enum IntelExprState {
394  IES_INIT,
395  IES_OR,
396  IES_XOR,
397  IES_AND,
398  IES_EQ,
399  IES_NE,
400  IES_LT,
401  IES_LE,
402  IES_GT,
403  IES_GE,
404  IES_LSHIFT,
405  IES_RSHIFT,
406  IES_PLUS,
407  IES_MINUS,
408  IES_OFFSET,
409  IES_CAST,
410  IES_NOT,
411  IES_MULTIPLY,
412  IES_DIVIDE,
413  IES_MOD,
414  IES_LBRAC,
415  IES_RBRAC,
416  IES_LPAREN,
417  IES_RPAREN,
418  IES_REGISTER,
419  IES_INTEGER,
420  IES_IDENTIFIER,
421  IES_ERROR
422  };
423 
424  class IntelExprStateMachine {
425  IntelExprState State, PrevState;
426  unsigned BaseReg, IndexReg, TmpReg, Scale;
427  int64_t Imm;
428  const MCExpr *Sym;
429  StringRef SymName;
430  InfixCalculator IC;
432  short BracCount;
433  bool MemExpr;
434  bool OffsetOperator;
435  SMLoc OffsetOperatorLoc;
436  AsmTypeInfo CurType;
437 
438  bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
439  if (Sym) {
440  ErrMsg = "cannot use more than one symbol in memory operand";
441  return true;
442  }
443  Sym = Val;
444  SymName = ID;
445  return false;
446  }
447 
448  public:
449  IntelExprStateMachine()
450  : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
451  TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
452  MemExpr(false), OffsetOperator(false) {}
453 
454  void addImm(int64_t imm) { Imm += imm; }
455  short getBracCount() const { return BracCount; }
456  bool isMemExpr() const { return MemExpr; }
457  bool isOffsetOperator() const { return OffsetOperator; }
458  SMLoc getOffsetLoc() const { return OffsetOperatorLoc; }
459  unsigned getBaseReg() const { return BaseReg; }
460  unsigned getIndexReg() const { return IndexReg; }
461  unsigned getScale() const { return Scale; }
462  const MCExpr *getSym() const { return Sym; }
463  StringRef getSymName() const { return SymName; }
464  StringRef getType() const { return CurType.Name; }
465  unsigned getSize() const { return CurType.Size; }
466  unsigned getElementSize() const { return CurType.ElementSize; }
467  unsigned getLength() const { return CurType.Length; }
468  int64_t getImm() { return Imm + IC.execute(); }
469  bool isValidEndState() const {
470  return State == IES_RBRAC || State == IES_INTEGER;
471  }
472  bool hadError() const { return State == IES_ERROR; }
473  const InlineAsmIdentifierInfo &getIdentifierInfo() const { return Info; }
474 
475  void onOr() {
476  IntelExprState CurrState = State;
477  switch (State) {
478  default:
479  State = IES_ERROR;
480  break;
481  case IES_INTEGER:
482  case IES_RPAREN:
483  case IES_REGISTER:
484  State = IES_OR;
485  IC.pushOperator(IC_OR);
486  break;
487  }
488  PrevState = CurrState;
489  }
490  void onXor() {
491  IntelExprState CurrState = State;
492  switch (State) {
493  default:
494  State = IES_ERROR;
495  break;
496  case IES_INTEGER:
497  case IES_RPAREN:
498  case IES_REGISTER:
499  State = IES_XOR;
500  IC.pushOperator(IC_XOR);
501  break;
502  }
503  PrevState = CurrState;
504  }
505  void onAnd() {
506  IntelExprState CurrState = State;
507  switch (State) {
508  default:
509  State = IES_ERROR;
510  break;
511  case IES_INTEGER:
512  case IES_RPAREN:
513  case IES_REGISTER:
514  State = IES_AND;
515  IC.pushOperator(IC_AND);
516  break;
517  }
518  PrevState = CurrState;
519  }
520  void onEq() {
521  IntelExprState CurrState = State;
522  switch (State) {
523  default:
524  State = IES_ERROR;
525  break;
526  case IES_INTEGER:
527  case IES_RPAREN:
528  case IES_REGISTER:
529  State = IES_EQ;
530  IC.pushOperator(IC_EQ);
531  break;
532  }
533  PrevState = CurrState;
534  }
535  void onNE() {
536  IntelExprState CurrState = State;
537  switch (State) {
538  default:
539  State = IES_ERROR;
540  break;
541  case IES_INTEGER:
542  case IES_RPAREN:
543  case IES_REGISTER:
544  State = IES_NE;
545  IC.pushOperator(IC_NE);
546  break;
547  }
548  PrevState = CurrState;
549  }
550  void onLT() {
551  IntelExprState CurrState = State;
552  switch (State) {
553  default:
554  State = IES_ERROR;
555  break;
556  case IES_INTEGER:
557  case IES_RPAREN:
558  case IES_REGISTER:
559  State = IES_LT;
560  IC.pushOperator(IC_LT);
561  break;
562  }
563  PrevState = CurrState;
564  }
565  void onLE() {
566  IntelExprState CurrState = State;
567  switch (State) {
568  default:
569  State = IES_ERROR;
570  break;
571  case IES_INTEGER:
572  case IES_RPAREN:
573  case IES_REGISTER:
574  State = IES_LE;
575  IC.pushOperator(IC_LE);
576  break;
577  }
578  PrevState = CurrState;
579  }
580  void onGT() {
581  IntelExprState CurrState = State;
582  switch (State) {
583  default:
584  State = IES_ERROR;
585  break;
586  case IES_INTEGER:
587  case IES_RPAREN:
588  case IES_REGISTER:
589  State = IES_GT;
590  IC.pushOperator(IC_GT);
591  break;
592  }
593  PrevState = CurrState;
594  }
595  void onGE() {
596  IntelExprState CurrState = State;
597  switch (State) {
598  default:
599  State = IES_ERROR;
600  break;
601  case IES_INTEGER:
602  case IES_RPAREN:
603  case IES_REGISTER:
604  State = IES_GE;
605  IC.pushOperator(IC_GE);
606  break;
607  }
608  PrevState = CurrState;
609  }
610  void onLShift() {
611  IntelExprState CurrState = State;
612  switch (State) {
613  default:
614  State = IES_ERROR;
615  break;
616  case IES_INTEGER:
617  case IES_RPAREN:
618  case IES_REGISTER:
619  State = IES_LSHIFT;
620  IC.pushOperator(IC_LSHIFT);
621  break;
622  }
623  PrevState = CurrState;
624  }
625  void onRShift() {
626  IntelExprState CurrState = State;
627  switch (State) {
628  default:
629  State = IES_ERROR;
630  break;
631  case IES_INTEGER:
632  case IES_RPAREN:
633  case IES_REGISTER:
634  State = IES_RSHIFT;
635  IC.pushOperator(IC_RSHIFT);
636  break;
637  }
638  PrevState = CurrState;
639  }
640  bool onPlus(StringRef &ErrMsg) {
641  IntelExprState CurrState = State;
642  switch (State) {
643  default:
644  State = IES_ERROR;
645  break;
646  case IES_INTEGER:
647  case IES_RPAREN:
648  case IES_REGISTER:
649  case IES_OFFSET:
650  State = IES_PLUS;
651  IC.pushOperator(IC_PLUS);
652  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
653  // If we already have a BaseReg, then assume this is the IndexReg with
654  // no explicit scale.
655  if (!BaseReg) {
656  BaseReg = TmpReg;
657  } else {
658  if (IndexReg) {
659  ErrMsg = "BaseReg/IndexReg already set!";
660  return true;
661  }
662  IndexReg = TmpReg;
663  Scale = 0;
664  }
665  }
666  break;
667  }
668  PrevState = CurrState;
669  return false;
670  }
671  bool onMinus(StringRef &ErrMsg) {
672  IntelExprState CurrState = State;
673  switch (State) {
674  default:
675  State = IES_ERROR;
676  break;
677  case IES_OR:
678  case IES_XOR:
679  case IES_AND:
680  case IES_EQ:
681  case IES_NE:
682  case IES_LT:
683  case IES_LE:
684  case IES_GT:
685  case IES_GE:
686  case IES_LSHIFT:
687  case IES_RSHIFT:
688  case IES_PLUS:
689  case IES_NOT:
690  case IES_MULTIPLY:
691  case IES_DIVIDE:
692  case IES_MOD:
693  case IES_LPAREN:
694  case IES_RPAREN:
695  case IES_LBRAC:
696  case IES_RBRAC:
697  case IES_INTEGER:
698  case IES_REGISTER:
699  case IES_INIT:
700  case IES_OFFSET:
701  State = IES_MINUS;
702  // push minus operator if it is not a negate operator
703  if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
704  CurrState == IES_INTEGER || CurrState == IES_RBRAC ||
705  CurrState == IES_OFFSET)
706  IC.pushOperator(IC_MINUS);
707  else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
708  // We have negate operator for Scale: it's illegal
709  ErrMsg = "Scale can't be negative";
710  return true;
711  } else
712  IC.pushOperator(IC_NEG);
713  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
714  // If we already have a BaseReg, then assume this is the IndexReg with
715  // no explicit scale.
716  if (!BaseReg) {
717  BaseReg = TmpReg;
718  } else {
719  if (IndexReg) {
720  ErrMsg = "BaseReg/IndexReg already set!";
721  return true;
722  }
723  IndexReg = TmpReg;
724  Scale = 0;
725  }
726  }
727  break;
728  }
729  PrevState = CurrState;
730  return false;
731  }
732  void onNot() {
733  IntelExprState CurrState = State;
734  switch (State) {
735  default:
736  State = IES_ERROR;
737  break;
738  case IES_OR:
739  case IES_XOR:
740  case IES_AND:
741  case IES_EQ:
742  case IES_NE:
743  case IES_LT:
744  case IES_LE:
745  case IES_GT:
746  case IES_GE:
747  case IES_LSHIFT:
748  case IES_RSHIFT:
749  case IES_PLUS:
750  case IES_MINUS:
751  case IES_NOT:
752  case IES_MULTIPLY:
753  case IES_DIVIDE:
754  case IES_MOD:
755  case IES_LPAREN:
756  case IES_LBRAC:
757  case IES_INIT:
758  State = IES_NOT;
759  IC.pushOperator(IC_NOT);
760  break;
761  }
762  PrevState = CurrState;
763  }
764  bool onRegister(unsigned Reg, StringRef &ErrMsg) {
765  IntelExprState CurrState = State;
766  switch (State) {
767  default:
768  State = IES_ERROR;
769  break;
770  case IES_PLUS:
771  case IES_LPAREN:
772  case IES_LBRAC:
773  State = IES_REGISTER;
774  TmpReg = Reg;
775  IC.pushOperand(IC_REGISTER);
776  break;
777  case IES_MULTIPLY:
778  // Index Register - Scale * Register
779  if (PrevState == IES_INTEGER) {
780  if (IndexReg) {
781  ErrMsg = "BaseReg/IndexReg already set!";
782  return true;
783  }
784  State = IES_REGISTER;
785  IndexReg = Reg;
786  // Get the scale and replace the 'Scale * Register' with '0'.
787  Scale = IC.popOperand();
788  if (checkScale(Scale, ErrMsg))
789  return true;
790  IC.pushOperand(IC_IMM);
791  IC.popOperator();
792  } else {
793  State = IES_ERROR;
794  }
795  break;
796  }
797  PrevState = CurrState;
798  return false;
799  }
800  bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
801  const InlineAsmIdentifierInfo &IDInfo,
802  const AsmTypeInfo &Type, bool ParsingMSInlineAsm,
803  StringRef &ErrMsg) {
804  // InlineAsm: Treat an enum value as an integer
805  if (ParsingMSInlineAsm)
807  return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
808  // Treat a symbolic constant like an integer
809  if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
810  return onInteger(CE->getValue(), ErrMsg);
811  PrevState = State;
812  switch (State) {
813  default:
814  State = IES_ERROR;
815  break;
816  case IES_CAST:
817  case IES_PLUS:
818  case IES_MINUS:
819  case IES_NOT:
820  case IES_INIT:
821  case IES_LBRAC:
822  case IES_LPAREN:
823  if (setSymRef(SymRef, SymRefName, ErrMsg))
824  return true;
825  MemExpr = true;
826  State = IES_INTEGER;
827  IC.pushOperand(IC_IMM);
828  if (ParsingMSInlineAsm)
829  Info = IDInfo;
830  setTypeInfo(Type);
831  break;
832  }
833  return false;
834  }
835  bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
836  IntelExprState CurrState = State;
837  switch (State) {
838  default:
839  State = IES_ERROR;
840  break;
841  case IES_PLUS:
842  case IES_MINUS:
843  case IES_NOT:
844  case IES_OR:
845  case IES_XOR:
846  case IES_AND:
847  case IES_EQ:
848  case IES_NE:
849  case IES_LT:
850  case IES_LE:
851  case IES_GT:
852  case IES_GE:
853  case IES_LSHIFT:
854  case IES_RSHIFT:
855  case IES_DIVIDE:
856  case IES_MOD:
857  case IES_MULTIPLY:
858  case IES_LPAREN:
859  case IES_INIT:
860  case IES_LBRAC:
861  State = IES_INTEGER;
862  if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
863  // Index Register - Register * Scale
864  if (IndexReg) {
865  ErrMsg = "BaseReg/IndexReg already set!";
866  return true;
867  }
868  IndexReg = TmpReg;
869  Scale = TmpInt;
870  if (checkScale(Scale, ErrMsg))
871  return true;
872  // Get the scale and replace the 'Register * Scale' with '0'.
873  IC.popOperator();
874  } else {
875  IC.pushOperand(IC_IMM, TmpInt);
876  }
877  break;
878  }
879  PrevState = CurrState;
880  return false;
881  }
882  void onStar() {
883  PrevState = State;
884  switch (State) {
885  default:
886  State = IES_ERROR;
887  break;
888  case IES_INTEGER:
889  case IES_REGISTER:
890  case IES_RPAREN:
891  State = IES_MULTIPLY;
892  IC.pushOperator(IC_MULTIPLY);
893  break;
894  }
895  }
896  void onDivide() {
897  PrevState = State;
898  switch (State) {
899  default:
900  State = IES_ERROR;
901  break;
902  case IES_INTEGER:
903  case IES_RPAREN:
904  State = IES_DIVIDE;
905  IC.pushOperator(IC_DIVIDE);
906  break;
907  }
908  }
909  void onMod() {
910  PrevState = State;
911  switch (State) {
912  default:
913  State = IES_ERROR;
914  break;
915  case IES_INTEGER:
916  case IES_RPAREN:
917  State = IES_MOD;
918  IC.pushOperator(IC_MOD);
919  break;
920  }
921  }
922  bool onLBrac() {
923  if (BracCount)
924  return true;
925  PrevState = State;
926  switch (State) {
927  default:
928  State = IES_ERROR;
929  break;
930  case IES_RBRAC:
931  case IES_INTEGER:
932  case IES_RPAREN:
933  State = IES_PLUS;
934  IC.pushOperator(IC_PLUS);
935  CurType.Length = 1;
936  CurType.Size = CurType.ElementSize;
937  break;
938  case IES_INIT:
939  case IES_CAST:
940  assert(!BracCount && "BracCount should be zero on parsing's start");
941  State = IES_LBRAC;
942  break;
943  }
944  MemExpr = true;
945  BracCount++;
946  return false;
947  }
948  bool onRBrac() {
949  IntelExprState CurrState = State;
950  switch (State) {
951  default:
952  State = IES_ERROR;
953  break;
954  case IES_INTEGER:
955  case IES_OFFSET:
956  case IES_REGISTER:
957  case IES_RPAREN:
958  if (BracCount-- != 1)
959  return true;
960  State = IES_RBRAC;
961  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
962  // If we already have a BaseReg, then assume this is the IndexReg with
963  // no explicit scale.
964  if (!BaseReg) {
965  BaseReg = TmpReg;
966  } else {
967  assert (!IndexReg && "BaseReg/IndexReg already set!");
968  IndexReg = TmpReg;
969  Scale = 0;
970  }
971  }
972  break;
973  }
974  PrevState = CurrState;
975  return false;
976  }
977  void onLParen() {
978  IntelExprState CurrState = State;
979  switch (State) {
980  default:
981  State = IES_ERROR;
982  break;
983  case IES_PLUS:
984  case IES_MINUS:
985  case IES_NOT:
986  case IES_OR:
987  case IES_XOR:
988  case IES_AND:
989  case IES_EQ:
990  case IES_NE:
991  case IES_LT:
992  case IES_LE:
993  case IES_GT:
994  case IES_GE:
995  case IES_LSHIFT:
996  case IES_RSHIFT:
997  case IES_MULTIPLY:
998  case IES_DIVIDE:
999  case IES_MOD:
1000  case IES_LPAREN:
1001  case IES_INIT:
1002  case IES_LBRAC:
1003  State = IES_LPAREN;
1004  IC.pushOperator(IC_LPAREN);
1005  break;
1006  }
1007  PrevState = CurrState;
1008  }
1009  void onRParen() {
1010  PrevState = State;
1011  switch (State) {
1012  default:
1013  State = IES_ERROR;
1014  break;
1015  case IES_INTEGER:
1016  case IES_OFFSET:
1017  case IES_REGISTER:
1018  case IES_RBRAC:
1019  case IES_RPAREN:
1020  State = IES_RPAREN;
1021  IC.pushOperator(IC_RPAREN);
1022  break;
1023  }
1024  }
1025  bool onOffset(const MCExpr *Val, SMLoc OffsetLoc, StringRef ID,
1026  const InlineAsmIdentifierInfo &IDInfo,
1027  bool ParsingMSInlineAsm, StringRef &ErrMsg) {
1028  PrevState = State;
1029  switch (State) {
1030  default:
1031  ErrMsg = "unexpected offset operator expression";
1032  return true;
1033  case IES_PLUS:
1034  case IES_INIT:
1035  case IES_LBRAC:
1036  if (setSymRef(Val, ID, ErrMsg))
1037  return true;
1038  OffsetOperator = true;
1039  OffsetOperatorLoc = OffsetLoc;
1040  State = IES_OFFSET;
1041  // As we cannot yet resolve the actual value (offset), we retain
1042  // the requested semantics by pushing a '0' to the operands stack
1043  IC.pushOperand(IC_IMM);
1044  if (ParsingMSInlineAsm) {
1045  Info = IDInfo;
1046  }
1047  break;
1048  }
1049  return false;
1050  }
1051  void onCast(AsmTypeInfo Info) {
1052  PrevState = State;
1053  switch (State) {
1054  default:
1055  State = IES_ERROR;
1056  break;
1057  case IES_LPAREN:
1058  setTypeInfo(Info);
1059  State = IES_CAST;
1060  break;
1061  }
1062  }
1063  void setTypeInfo(AsmTypeInfo Type) { CurType = Type; }
1064  };
1065 
1066  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
1067  bool MatchingInlineAsm = false) {
1068  MCAsmParser &Parser = getParser();
1069  if (MatchingInlineAsm) {
1070  if (!getLexer().isAtStartOfStatement())
1071  Parser.eatToEndOfStatement();
1072  return false;
1073  }
1074  return Parser.Error(L, Msg, Range);
1075  }
1076 
1077  bool MatchRegisterByName(unsigned &RegNo, StringRef RegName, SMLoc StartLoc,
1078  SMLoc EndLoc);
1079  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
1080  bool RestoreOnFailure);
1081 
1082  std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
1083  std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
1084  bool IsSIReg(unsigned Reg);
1085  unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1086  void
1087  AddDefaultSrcDestOperands(OperandVector &Operands,
1088  std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1089  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
1090  bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
1091  OperandVector &FinalOperands);
1092  bool ParseOperand(OperandVector &Operands);
1093  bool ParseATTOperand(OperandVector &Operands);
1094  bool ParseIntelOperand(OperandVector &Operands);
1095  bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
1097  bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
1098  unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
1099  unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
1100  unsigned IdentifyMasmOperator(StringRef Name);
1101  bool ParseMasmOperator(unsigned OpKind, int64_t &Val);
1102  bool ParseRoundingModeOp(SMLoc Start, OperandVector &Operands);
1103  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1104  bool &ParseError, SMLoc &End);
1105  bool ParseMasmNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1106  bool &ParseError, SMLoc &End);
1107  void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
1108  SMLoc End);
1109  bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
1110  bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
1112  bool IsUnevaluatedOperand, SMLoc &End,
1113  bool IsParsingOffsetOperator = false);
1114 
1115  bool ParseMemOperand(unsigned SegReg, const MCExpr *Disp, SMLoc StartLoc,
1116  SMLoc EndLoc, OperandVector &Operands);
1117 
1118  X86::CondCode ParseConditionCode(StringRef CCode);
1119 
1120  bool ParseIntelMemoryOperandSize(unsigned &Size);
1121  bool CreateMemForMSInlineAsm(unsigned SegReg, const MCExpr *Disp,
1122  unsigned BaseReg, unsigned IndexReg,
1123  unsigned Scale, SMLoc Start, SMLoc End,
1124  unsigned Size, StringRef Identifier,
1127 
1128  bool parseDirectiveArch();
1129  bool parseDirectiveNops(SMLoc L);
1130  bool parseDirectiveEven(SMLoc L);
1131  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
1132 
1133  /// CodeView FPO data directives.
1134  bool parseDirectiveFPOProc(SMLoc L);
1135  bool parseDirectiveFPOSetFrame(SMLoc L);
1136  bool parseDirectiveFPOPushReg(SMLoc L);
1137  bool parseDirectiveFPOStackAlloc(SMLoc L);
1138  bool parseDirectiveFPOStackAlign(SMLoc L);
1139  bool parseDirectiveFPOEndPrologue(SMLoc L);
1140  bool parseDirectiveFPOEndProc(SMLoc L);
1141 
1142  /// SEH directives.
1143  bool parseSEHRegisterNumber(unsigned RegClassID, unsigned &RegNo);
1144  bool parseDirectiveSEHPushReg(SMLoc);
1145  bool parseDirectiveSEHSetFrame(SMLoc);
1146  bool parseDirectiveSEHSaveReg(SMLoc);
1147  bool parseDirectiveSEHSaveXMM(SMLoc);
1148  bool parseDirectiveSEHPushFrame(SMLoc);
1149 
1150  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1151 
1152  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
1153  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
1154 
1155  // Load Value Injection (LVI) Mitigations for machine code
1156  void emitWarningForSpecialLVIInstruction(SMLoc Loc);
1157  void applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out);
1158  void applyLVILoadHardeningMitigation(MCInst &Inst, MCStreamer &Out);
1159 
1160  /// Wrapper around MCStreamer::emitInstruction(). Possibly adds
1161  /// instrumentation around Inst.
1162  void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
1163 
1164  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1167  bool MatchingInlineAsm) override;
1168 
1169  void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
1170  MCStreamer &Out, bool MatchingInlineAsm);
1171 
1172  bool ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures,
1173  bool MatchingInlineAsm);
1174 
1175  bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
1178  bool MatchingInlineAsm);
1179 
1180  bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
1183  bool MatchingInlineAsm);
1184 
1185  bool OmitRegisterFromClobberLists(unsigned RegNo) override;
1186 
1187  /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
1188  /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
1189  /// return false if no parsing errors occurred, true otherwise.
1190  bool HandleAVX512Operand(OperandVector &Operands);
1191 
1192  bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
1193 
1194  bool is64BitMode() const {
1195  // FIXME: Can tablegen auto-generate this?
1196  return getSTI().getFeatureBits()[X86::Mode64Bit];
1197  }
1198  bool is32BitMode() const {
1199  // FIXME: Can tablegen auto-generate this?
1200  return getSTI().getFeatureBits()[X86::Mode32Bit];
1201  }
1202  bool is16BitMode() const {
1203  // FIXME: Can tablegen auto-generate this?
1204  return getSTI().getFeatureBits()[X86::Mode16Bit];
1205  }
1206  void SwitchMode(unsigned mode) {
1207  MCSubtargetInfo &STI = copySTI();
1208  FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
1209  FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
1210  FeatureBitset FB = ComputeAvailableFeatures(
1211  STI.ToggleFeature(OldMode.flip(mode)));
1212  setAvailableFeatures(FB);
1213 
1214  assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
1215  }
1216 
1217  unsigned getPointerWidth() {
1218  if (is16BitMode()) return 16;
1219  if (is32BitMode()) return 32;
1220  if (is64BitMode()) return 64;
1221  llvm_unreachable("invalid mode");
1222  }
1223 
1224  bool isParsingIntelSyntax() {
1225  return getParser().getAssemblerDialect();
1226  }
1227 
1228  /// @name Auto-generated Matcher Functions
1229  /// {
1230 
1231 #define GET_ASSEMBLER_HEADER
1232 #include "X86GenAsmMatcher.inc"
1233 
1234  /// }
1235 
1236 public:
1237  enum X86MatchResultTy {
1238  Match_Unsupported = FIRST_TARGET_MATCH_RESULT_TY,
1239 #define GET_OPERAND_DIAGNOSTIC_TYPES
1240 #include "X86GenAsmMatcher.inc"
1241  };
1242 
1243  X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
1244  const MCInstrInfo &mii, const MCTargetOptions &Options)
1245  : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
1246  Code16GCC(false) {
1247 
1248  Parser.addAliasForDirective(".word", ".2byte");
1249 
1250  // Initialize the set of available features.
1251  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
1252  }
1253 
1254  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
1255  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1256  SMLoc &EndLoc) override;
1257 
1258  bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
1259 
1260  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1261  SMLoc NameLoc, OperandVector &Operands) override;
1262 
1263  bool ParseDirective(AsmToken DirectiveID) override;
1264 };
1265 } // end anonymous namespace
1266 
1267 /// @name Auto-generated Match Functions
1268 /// {
1269 
1270 static unsigned MatchRegisterName(StringRef Name);
1271 
1272 /// }
1273 
1274 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
1275  unsigned Scale, bool Is64BitMode,
1276  StringRef &ErrMsg) {
1277  // If we have both a base register and an index register make sure they are
1278  // both 64-bit or 32-bit registers.
1279  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1280 
1281  if (BaseReg != 0 &&
1282  !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
1283  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||
1284  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||
1285  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {
1286  ErrMsg = "invalid base+index expression";
1287  return true;
1288  }
1289 
1290  if (IndexReg != 0 &&
1291  !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1292  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1293  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1294  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1295  X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1296  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1297  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
1298  ErrMsg = "invalid base+index expression";
1299  return true;
1300  }
1301 
1302  if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1303  IndexReg == X86::EIP || IndexReg == X86::RIP ||
1304  IndexReg == X86::ESP || IndexReg == X86::RSP) {
1305  ErrMsg = "invalid base+index expression";
1306  return true;
1307  }
1308 
1309  // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1310  // and then only in non-64-bit modes.
1311  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1312  (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1313  BaseReg != X86::SI && BaseReg != X86::DI))) {
1314  ErrMsg = "invalid 16-bit base register";
1315  return true;
1316  }
1317 
1318  if (BaseReg == 0 &&
1319  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1320  ErrMsg = "16-bit memory operand may not include only index register";
1321  return true;
1322  }
1323 
1324  if (BaseReg != 0 && IndexReg != 0) {
1325  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1326  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1327  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1328  IndexReg == X86::EIZ)) {
1329  ErrMsg = "base register is 64-bit, but index register is not";
1330  return true;
1331  }
1332  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1333  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1334  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1335  IndexReg == X86::RIZ)) {
1336  ErrMsg = "base register is 32-bit, but index register is not";
1337  return true;
1338  }
1339  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
1340  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1341  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1342  ErrMsg = "base register is 16-bit, but index register is not";
1343  return true;
1344  }
1345  if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1346  (IndexReg != X86::SI && IndexReg != X86::DI)) {
1347  ErrMsg = "invalid 16-bit base/index register combination";
1348  return true;
1349  }
1350  }
1351  }
1352 
1353  // RIP/EIP-relative addressing is only supported in 64-bit mode.
1354  if (!Is64BitMode && BaseReg != 0 &&
1355  (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1356  ErrMsg = "IP-relative addressing requires 64-bit mode";
1357  return true;
1358  }
1359 
1360  return checkScale(Scale, ErrMsg);
1361 }
1362 
1363 bool X86AsmParser::MatchRegisterByName(unsigned &RegNo, StringRef RegName,
1364  SMLoc StartLoc, SMLoc EndLoc) {
1365  // If we encounter a %, ignore it. This code handles registers with and
1366  // without the prefix, unprefixed registers can occur in cfi directives.
1367  RegName.consume_front("%");
1368 
1369  RegNo = MatchRegisterName(RegName);
1370 
1371  // If the match failed, try the register name as lowercase.
1372  if (RegNo == 0)
1373  RegNo = MatchRegisterName(RegName.lower());
1374 
1375  // The "flags" and "mxcsr" registers cannot be referenced directly.
1376  // Treat it as an identifier instead.
1377  if (isParsingMSInlineAsm() && isParsingIntelSyntax() &&
1378  (RegNo == X86::EFLAGS || RegNo == X86::MXCSR))
1379  RegNo = 0;
1380 
1381  if (!is64BitMode()) {
1382  // FIXME: This should be done using Requires<Not64BitMode> and
1383  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1384  // checked.
1385  if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1386  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1388  X86II::isX86_64ExtendedReg(RegNo)) {
1389  return Error(StartLoc,
1390  "register %" + RegName + " is only available in 64-bit mode",
1391  SMRange(StartLoc, EndLoc));
1392  }
1393  }
1394 
1395  // If this is "db[0-15]", match it as an alias
1396  // for dr[0-15].
1397  if (RegNo == 0 && RegName.startswith("db")) {
1398  if (RegName.size() == 3) {
1399  switch (RegName[2]) {
1400  case '0':
1401  RegNo = X86::DR0;
1402  break;
1403  case '1':
1404  RegNo = X86::DR1;
1405  break;
1406  case '2':
1407  RegNo = X86::DR2;
1408  break;
1409  case '3':
1410  RegNo = X86::DR3;
1411  break;
1412  case '4':
1413  RegNo = X86::DR4;
1414  break;
1415  case '5':
1416  RegNo = X86::DR5;
1417  break;
1418  case '6':
1419  RegNo = X86::DR6;
1420  break;
1421  case '7':
1422  RegNo = X86::DR7;
1423  break;
1424  case '8':
1425  RegNo = X86::DR8;
1426  break;
1427  case '9':
1428  RegNo = X86::DR9;
1429  break;
1430  }
1431  } else if (RegName.size() == 4 && RegName[2] == '1') {
1432  switch (RegName[3]) {
1433  case '0':
1434  RegNo = X86::DR10;
1435  break;
1436  case '1':
1437  RegNo = X86::DR11;
1438  break;
1439  case '2':
1440  RegNo = X86::DR12;
1441  break;
1442  case '3':
1443  RegNo = X86::DR13;
1444  break;
1445  case '4':
1446  RegNo = X86::DR14;
1447  break;
1448  case '5':
1449  RegNo = X86::DR15;
1450  break;
1451  }
1452  }
1453  }
1454 
1455  if (RegNo == 0) {
1456  if (isParsingIntelSyntax())
1457  return true;
1458  return Error(StartLoc, "invalid register name", SMRange(StartLoc, EndLoc));
1459  }
1460  return false;
1461 }
1462 
1463 bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1464  SMLoc &EndLoc, bool RestoreOnFailure) {
1465  MCAsmParser &Parser = getParser();
1466  MCAsmLexer &Lexer = getLexer();
1467  RegNo = 0;
1468 
1469  SmallVector<AsmToken, 5> Tokens;
1470  auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() {
1471  if (RestoreOnFailure) {
1472  while (!Tokens.empty()) {
1473  Lexer.UnLex(Tokens.pop_back_val());
1474  }
1475  }
1476  };
1477 
1478  const AsmToken &PercentTok = Parser.getTok();
1479  StartLoc = PercentTok.getLoc();
1480 
1481  // If we encounter a %, ignore it. This code handles registers with and
1482  // without the prefix, unprefixed registers can occur in cfi directives.
1483  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent)) {
1484  Tokens.push_back(PercentTok);
1485  Parser.Lex(); // Eat percent token.
1486  }
1487 
1488  const AsmToken &Tok = Parser.getTok();
1489  EndLoc = Tok.getEndLoc();
1490 
1491  if (Tok.isNot(AsmToken::Identifier)) {
1492  OnFailure();
1493  if (isParsingIntelSyntax()) return true;
1494  return Error(StartLoc, "invalid register name",
1495  SMRange(StartLoc, EndLoc));
1496  }
1497 
1498  if (MatchRegisterByName(RegNo, Tok.getString(), StartLoc, EndLoc)) {
1499  OnFailure();
1500  return true;
1501  }
1502 
1503  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1504  if (RegNo == X86::ST0) {
1505  Tokens.push_back(Tok);
1506  Parser.Lex(); // Eat 'st'
1507 
1508  // Check to see if we have '(4)' after %st.
1509  if (Lexer.isNot(AsmToken::LParen))
1510  return false;
1511  // Lex the paren.
1512  Tokens.push_back(Parser.getTok());
1513  Parser.Lex();
1514 
1515  const AsmToken &IntTok = Parser.getTok();
1516  if (IntTok.isNot(AsmToken::Integer)) {
1517  OnFailure();
1518  return Error(IntTok.getLoc(), "expected stack index");
1519  }
1520  switch (IntTok.getIntVal()) {
1521  case 0: RegNo = X86::ST0; break;
1522  case 1: RegNo = X86::ST1; break;
1523  case 2: RegNo = X86::ST2; break;
1524  case 3: RegNo = X86::ST3; break;
1525  case 4: RegNo = X86::ST4; break;
1526  case 5: RegNo = X86::ST5; break;
1527  case 6: RegNo = X86::ST6; break;
1528  case 7: RegNo = X86::ST7; break;
1529  default:
1530  OnFailure();
1531  return Error(IntTok.getLoc(), "invalid stack index");
1532  }
1533 
1534  // Lex IntTok
1535  Tokens.push_back(IntTok);
1536  Parser.Lex();
1537  if (Lexer.isNot(AsmToken::RParen)) {
1538  OnFailure();
1539  return Error(Parser.getTok().getLoc(), "expected ')'");
1540  }
1541 
1542  EndLoc = Parser.getTok().getEndLoc();
1543  Parser.Lex(); // Eat ')'
1544  return false;
1545  }
1546 
1547  EndLoc = Parser.getTok().getEndLoc();
1548 
1549  if (RegNo == 0) {
1550  OnFailure();
1551  if (isParsingIntelSyntax()) return true;
1552  return Error(StartLoc, "invalid register name",
1553  SMRange(StartLoc, EndLoc));
1554  }
1555 
1556  Parser.Lex(); // Eat identifier token.
1557  return false;
1558 }
1559 
1560 bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1561  SMLoc &EndLoc) {
1562  return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1563 }
1564 
1565 OperandMatchResultTy X86AsmParser::tryParseRegister(unsigned &RegNo,
1566  SMLoc &StartLoc,
1567  SMLoc &EndLoc) {
1568  bool Result =
1569  ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1570  bool PendingErrors = getParser().hasPendingError();
1571  getParser().clearPendingErrors();
1572  if (PendingErrors)
1573  return MatchOperand_ParseFail;
1574  if (Result)
1575  return MatchOperand_NoMatch;
1576  return MatchOperand_Success;
1577 }
1578 
1579 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1580  bool Parse32 = is32BitMode() || Code16GCC;
1581  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1582  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1583  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1584  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1585  Loc, Loc, 0);
1586 }
1587 
1588 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1589  bool Parse32 = is32BitMode() || Code16GCC;
1590  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1591  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1592  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1593  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1594  Loc, Loc, 0);
1595 }
1596 
1597 bool X86AsmParser::IsSIReg(unsigned Reg) {
1598  switch (Reg) {
1599  default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1600  case X86::RSI:
1601  case X86::ESI:
1602  case X86::SI:
1603  return true;
1604  case X86::RDI:
1605  case X86::EDI:
1606  case X86::DI:
1607  return false;
1608  }
1609 }
1610 
1611 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1612  bool IsSIReg) {
1613  switch (RegClassID) {
1614  default: llvm_unreachable("Unexpected register class");
1615  case X86::GR64RegClassID:
1616  return IsSIReg ? X86::RSI : X86::RDI;
1617  case X86::GR32RegClassID:
1618  return IsSIReg ? X86::ESI : X86::EDI;
1619  case X86::GR16RegClassID:
1620  return IsSIReg ? X86::SI : X86::DI;
1621  }
1622 }
1623 
1624 void X86AsmParser::AddDefaultSrcDestOperands(
1625  OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1626  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1627  if (isParsingIntelSyntax()) {
1628  Operands.push_back(std::move(Dst));
1629  Operands.push_back(std::move(Src));
1630  }
1631  else {
1632  Operands.push_back(std::move(Src));
1633  Operands.push_back(std::move(Dst));
1634  }
1635 }
1636 
1637 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1638  OperandVector &FinalOperands) {
1639 
1640  if (OrigOperands.size() > 1) {
1641  // Check if sizes match, OrigOperands also contains the instruction name
1642  assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1643  "Operand size mismatch");
1644 
1646  // Verify types match
1647  int RegClassID = -1;
1648  for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1649  X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1650  X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1651 
1652  if (FinalOp.isReg() &&
1653  (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1654  // Return false and let a normal complaint about bogus operands happen
1655  return false;
1656 
1657  if (FinalOp.isMem()) {
1658 
1659  if (!OrigOp.isMem())
1660  // Return false and let a normal complaint about bogus operands happen
1661  return false;
1662 
1663  unsigned OrigReg = OrigOp.Mem.BaseReg;
1664  unsigned FinalReg = FinalOp.Mem.BaseReg;
1665 
1666  // If we've already encounterd a register class, make sure all register
1667  // bases are of the same register class
1668  if (RegClassID != -1 &&
1669  !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1670  return Error(OrigOp.getStartLoc(),
1671  "mismatching source and destination index registers");
1672  }
1673 
1674  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1675  RegClassID = X86::GR64RegClassID;
1676  else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1677  RegClassID = X86::GR32RegClassID;
1678  else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1679  RegClassID = X86::GR16RegClassID;
1680  else
1681  // Unexpected register class type
1682  // Return false and let a normal complaint about bogus operands happen
1683  return false;
1684 
1685  bool IsSI = IsSIReg(FinalReg);
1686  FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1687 
1688  if (FinalReg != OrigReg) {
1689  std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1690  Warnings.push_back(std::make_pair(
1691  OrigOp.getStartLoc(),
1692  "memory operand is only for determining the size, " + RegName +
1693  " will be used for the location"));
1694  }
1695 
1696  FinalOp.Mem.Size = OrigOp.Mem.Size;
1697  FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1698  FinalOp.Mem.BaseReg = FinalReg;
1699  }
1700  }
1701 
1702  // Produce warnings only if all the operands passed the adjustment - prevent
1703  // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1704  for (auto &WarningMsg : Warnings) {
1705  Warning(WarningMsg.first, WarningMsg.second);
1706  }
1707 
1708  // Remove old operands
1709  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1710  OrigOperands.pop_back();
1711  }
1712  // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1713  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1714  OrigOperands.push_back(std::move(FinalOperands[i]));
1715 
1716  return false;
1717 }
1718 
1719 bool X86AsmParser::ParseOperand(OperandVector &Operands) {
1720  if (isParsingIntelSyntax())
1721  return ParseIntelOperand(Operands);
1722 
1723  return ParseATTOperand(Operands);
1724 }
1725 
1726 bool X86AsmParser::CreateMemForMSInlineAsm(
1727  unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1728  unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
1730  // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1731  // some other label reference.
1733  // Insert an explicit size if the user didn't have one.
1734  if (!Size) {
1735  Size = getPointerWidth();
1736  InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1737  /*Len=*/0, Size);
1738  }
1739  // Create an absolute memory reference in order to match against
1740  // instructions taking a PC relative operand.
1741  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
1742  End, Size, Identifier,
1743  Info.Label.Decl));
1744  return false;
1745  }
1746  // We either have a direct symbol reference, or an offset from a symbol. The
1747  // parser always puts the symbol on the LHS, so look there for size
1748  // calculation purposes.
1749  unsigned FrontendSize = 0;
1750  void *Decl = nullptr;
1751  bool IsGlobalLV = false;
1752  if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
1753  // Size is in terms of bits in this context.
1754  FrontendSize = Info.Var.Type * 8;
1755  Decl = Info.Var.Decl;
1756  IsGlobalLV = Info.Var.IsGlobalLV;
1757  }
1758  // It is widely common for MS InlineAsm to use a global variable and one/two
1759  // registers in a mmory expression, and though unaccessible via rip/eip.
1760  if (IsGlobalLV && (BaseReg || IndexReg)) {
1761  Operands.push_back(
1762  X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
1763  return false;
1764  }
1765  // Otherwise, we set the base register to a non-zero value
1766  // if we don't know the actual value at this time. This is necessary to
1767  // get the matching correct in some cases.
1768  BaseReg = BaseReg ? BaseReg : 1;
1769  Operands.push_back(X86Operand::CreateMem(
1770  getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
1771  Size,
1772  /*DefaultBaseReg=*/X86::RIP, Identifier, Decl, FrontendSize));
1773  return false;
1774 }
1775 
1776 // Some binary bitwise operators have a named synonymous
1777 // Query a candidate string for being such a named operator
1778 // and if so - invoke the appropriate handler
1779 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
1780  IntelExprStateMachine &SM,
1781  bool &ParseError, SMLoc &End) {
1782  // A named operator should be either lower or upper case, but not a mix...
1783  // except in MASM, which uses full case-insensitivity.
1784  if (Name.compare(Name.lower()) && Name.compare(Name.upper()) &&
1785  !getParser().isParsingMasm())
1786  return false;
1787  if (Name.equals_insensitive("not")) {
1788  SM.onNot();
1789  } else if (Name.equals_insensitive("or")) {
1790  SM.onOr();
1791  } else if (Name.equals_insensitive("shl")) {
1792  SM.onLShift();
1793  } else if (Name.equals_insensitive("shr")) {
1794  SM.onRShift();
1795  } else if (Name.equals_insensitive("xor")) {
1796  SM.onXor();
1797  } else if (Name.equals_insensitive("and")) {
1798  SM.onAnd();
1799  } else if (Name.equals_insensitive("mod")) {
1800  SM.onMod();
1801  } else if (Name.equals_insensitive("offset")) {
1802  SMLoc OffsetLoc = getTok().getLoc();
1803  const MCExpr *Val = nullptr;
1804  StringRef ID;
1806  ParseError = ParseIntelOffsetOperator(Val, ID, Info, End);
1807  if (ParseError)
1808  return true;
1809  StringRef ErrMsg;
1810  ParseError =
1811  SM.onOffset(Val, OffsetLoc, ID, Info, isParsingMSInlineAsm(), ErrMsg);
1812  if (ParseError)
1813  return Error(SMLoc::getFromPointer(Name.data()), ErrMsg);
1814  } else {
1815  return false;
1816  }
1817  if (!Name.equals_insensitive("offset"))
1818  End = consumeToken();
1819  return true;
1820 }
1821 bool X86AsmParser::ParseMasmNamedOperator(StringRef Name,
1822  IntelExprStateMachine &SM,
1823  bool &ParseError, SMLoc &End) {
1824  if (Name.equals_insensitive("eq")) {
1825  SM.onEq();
1826  } else if (Name.equals_insensitive("ne")) {
1827  SM.onNE();
1828  } else if (Name.equals_insensitive("lt")) {
1829  SM.onLT();
1830  } else if (Name.equals_insensitive("le")) {
1831  SM.onLE();
1832  } else if (Name.equals_insensitive("gt")) {
1833  SM.onGT();
1834  } else if (Name.equals_insensitive("ge")) {
1835  SM.onGE();
1836  } else {
1837  return false;
1838  }
1839  End = consumeToken();
1840  return true;
1841 }
1842 
1843 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1844  MCAsmParser &Parser = getParser();
1845  StringRef ErrMsg;
1846 
1848  bool Done = false;
1849  while (!Done) {
1850  // Get a fresh reference on each loop iteration in case the previous
1851  // iteration moved the token storage during UnLex().
1852  const AsmToken &Tok = Parser.getTok();
1853 
1854  bool UpdateLocLex = true;
1855  AsmToken::TokenKind TK = getLexer().getKind();
1856 
1857  switch (TK) {
1858  default:
1859  if ((Done = SM.isValidEndState()))
1860  break;
1861  return Error(Tok.getLoc(), "unknown token in expression");
1862  case AsmToken::Error:
1863  return Error(getLexer().getErrLoc(), getLexer().getErr());
1864  break;
1866  Done = true;
1867  break;
1868  case AsmToken::Real:
1869  // DotOperator: [ebx].0
1870  UpdateLocLex = false;
1871  if (ParseIntelDotOperator(SM, End))
1872  return true;
1873  break;
1874  case AsmToken::Dot:
1875  if (!Parser.isParsingMasm()) {
1876  if ((Done = SM.isValidEndState()))
1877  break;
1878  return Error(Tok.getLoc(), "unknown token in expression");
1879  }
1880  // MASM allows spaces around the dot operator (e.g., "var . x")
1881  Lex();
1882  UpdateLocLex = false;
1883  if (ParseIntelDotOperator(SM, End))
1884  return true;
1885  break;
1886  case AsmToken::Dollar:
1887  if (!Parser.isParsingMasm()) {
1888  if ((Done = SM.isValidEndState()))
1889  break;
1890  return Error(Tok.getLoc(), "unknown token in expression");
1891  }
1893  case AsmToken::String: {
1894  if (Parser.isParsingMasm()) {
1895  // MASM parsers handle strings in expressions as constants.
1896  SMLoc ValueLoc = Tok.getLoc();
1897  int64_t Res;
1898  const MCExpr *Val;
1899  if (Parser.parsePrimaryExpr(Val, End, nullptr))
1900  return true;
1901  UpdateLocLex = false;
1902  if (!Val->evaluateAsAbsolute(Res, getStreamer().getAssemblerPtr()))
1903  return Error(ValueLoc, "expected absolute value");
1904  if (SM.onInteger(Res, ErrMsg))
1905  return Error(ValueLoc, ErrMsg);
1906  break;
1907  }
1909  }
1910  case AsmToken::At:
1911  case AsmToken::Identifier: {
1912  SMLoc IdentLoc = Tok.getLoc();
1913  StringRef Identifier = Tok.getString();
1914  UpdateLocLex = false;
1915  if (Parser.isParsingMasm()) {
1916  size_t DotOffset = Identifier.find_first_of('.');
1917  if (DotOffset != StringRef::npos) {
1918  consumeToken();
1919  StringRef LHS = Identifier.slice(0, DotOffset);
1920  StringRef Dot = Identifier.slice(DotOffset, DotOffset + 1);
1921  StringRef RHS = Identifier.slice(DotOffset + 1, StringRef::npos);
1922  if (!RHS.empty()) {
1923  getLexer().UnLex(AsmToken(AsmToken::Identifier, RHS));
1924  }
1925  getLexer().UnLex(AsmToken(AsmToken::Dot, Dot));
1926  if (!LHS.empty()) {
1927  getLexer().UnLex(AsmToken(AsmToken::Identifier, LHS));
1928  }
1929  break;
1930  }
1931  }
1932  // (MASM only) <TYPE> PTR operator
1933  if (Parser.isParsingMasm()) {
1934  const AsmToken &NextTok = getLexer().peekTok();
1935  if (NextTok.is(AsmToken::Identifier) &&
1936  NextTok.getIdentifier().equals_insensitive("ptr")) {
1937  AsmTypeInfo Info;
1938  if (Parser.lookUpType(Identifier, Info))
1939  return Error(Tok.getLoc(), "unknown type");
1940  SM.onCast(Info);
1941  // Eat type and PTR.
1942  consumeToken();
1943  End = consumeToken();
1944  break;
1945  }
1946  }
1947  // Register, or (MASM only) <register>.<field>
1948  unsigned Reg;
1949  if (Tok.is(AsmToken::Identifier)) {
1950  if (!ParseRegister(Reg, IdentLoc, End, /*RestoreOnFailure=*/true)) {
1951  if (SM.onRegister(Reg, ErrMsg))
1952  return Error(IdentLoc, ErrMsg);
1953  break;
1954  }
1955  if (Parser.isParsingMasm()) {
1956  const std::pair<StringRef, StringRef> IDField =
1957  Tok.getString().split('.');
1958  const StringRef ID = IDField.first, Field = IDField.second;
1959  SMLoc IDEndLoc = SMLoc::getFromPointer(ID.data() + ID.size());
1960  if (!Field.empty() &&
1961  !MatchRegisterByName(Reg, ID, IdentLoc, IDEndLoc)) {
1962  if (SM.onRegister(Reg, ErrMsg))
1963  return Error(IdentLoc, ErrMsg);
1964 
1966  SMLoc FieldStartLoc = SMLoc::getFromPointer(Field.data());
1967  if (Parser.lookUpField(Field, Info))
1968  return Error(FieldStartLoc, "unknown offset");
1969  else if (SM.onPlus(ErrMsg))
1970  return Error(getTok().getLoc(), ErrMsg);
1971  else if (SM.onInteger(Info.Offset, ErrMsg))
1972  return Error(IdentLoc, ErrMsg);
1973  SM.setTypeInfo(Info.Type);
1974 
1975  End = consumeToken();
1976  break;
1977  }
1978  }
1979  }
1980  // Operator synonymous ("not", "or" etc.)
1981  bool ParseError = false;
1982  if (ParseIntelNamedOperator(Identifier, SM, ParseError, End)) {
1983  if (ParseError)
1984  return true;
1985  break;
1986  }
1987  if (Parser.isParsingMasm() &&
1988  ParseMasmNamedOperator(Identifier, SM, ParseError, End)) {
1989  if (ParseError)
1990  return true;
1991  break;
1992  }
1993  // Symbol reference, when parsing assembly content
1995  AsmFieldInfo FieldInfo;
1996  const MCExpr *Val;
1997  if (isParsingMSInlineAsm() || Parser.isParsingMasm()) {
1998  // MS Dot Operator expression
1999  if (Identifier.count('.') &&
2000  (PrevTK == AsmToken::RBrac || PrevTK == AsmToken::RParen)) {
2001  if (ParseIntelDotOperator(SM, End))
2002  return true;
2003  break;
2004  }
2005  }
2006  if (isParsingMSInlineAsm()) {
2007  // MS InlineAsm operators (TYPE/LENGTH/SIZE)
2008  if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
2009  if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
2010  if (SM.onInteger(Val, ErrMsg))
2011  return Error(IdentLoc, ErrMsg);
2012  } else {
2013  return true;
2014  }
2015  break;
2016  }
2017  // MS InlineAsm identifier
2018  // Call parseIdentifier() to combine @ with the identifier behind it.
2019  if (TK == AsmToken::At && Parser.parseIdentifier(Identifier))
2020  return Error(IdentLoc, "expected identifier");
2021  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
2022  return true;
2023  else if (SM.onIdentifierExpr(Val, Identifier, Info, FieldInfo.Type,
2024  true, ErrMsg))
2025  return Error(IdentLoc, ErrMsg);
2026  break;
2027  }
2028  if (Parser.isParsingMasm()) {
2029  if (unsigned OpKind = IdentifyMasmOperator(Identifier)) {
2030  int64_t Val;
2031  if (ParseMasmOperator(OpKind, Val))
2032  return true;
2033  if (SM.onInteger(Val, ErrMsg))
2034  return Error(IdentLoc, ErrMsg);
2035  break;
2036  }
2037  if (!getParser().lookUpType(Identifier, FieldInfo.Type)) {
2038  // Field offset immediate; <TYPE>.<field specification>
2039  Lex(); // eat type
2040  bool EndDot = parseOptionalToken(AsmToken::Dot);
2041  while (EndDot || (getTok().is(AsmToken::Identifier) &&
2042  getTok().getString().startswith("."))) {
2043  getParser().parseIdentifier(Identifier);
2044  if (!EndDot)
2045  Identifier.consume_front(".");
2046  EndDot = Identifier.consume_back(".");
2047  if (getParser().lookUpField(FieldInfo.Type.Name, Identifier,
2048  FieldInfo)) {
2049  SMLoc IDEnd =
2050  SMLoc::getFromPointer(Identifier.data() + Identifier.size());
2051  return Error(IdentLoc, "Unable to lookup field reference!",
2052  SMRange(IdentLoc, IDEnd));
2053  }
2054  if (!EndDot)
2055  EndDot = parseOptionalToken(AsmToken::Dot);
2056  }
2057  if (SM.onInteger(FieldInfo.Offset, ErrMsg))
2058  return Error(IdentLoc, ErrMsg);
2059  break;
2060  }
2061  }
2062  if (getParser().parsePrimaryExpr(Val, End, &FieldInfo.Type)) {
2063  return Error(Tok.getLoc(), "Unexpected identifier!");
2064  } else if (SM.onIdentifierExpr(Val, Identifier, Info, FieldInfo.Type,
2065  false, ErrMsg)) {
2066  return Error(IdentLoc, ErrMsg);
2067  }
2068  break;
2069  }
2070  case AsmToken::Integer: {
2071  // Look for 'b' or 'f' following an Integer as a directional label
2072  SMLoc Loc = getTok().getLoc();
2073  int64_t IntVal = getTok().getIntVal();
2074  End = consumeToken();
2075  UpdateLocLex = false;
2076  if (getLexer().getKind() == AsmToken::Identifier) {
2077  StringRef IDVal = getTok().getString();
2078  if (IDVal == "f" || IDVal == "b") {
2079  MCSymbol *Sym =
2080  getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
2082  const MCExpr *Val =
2083  MCSymbolRefExpr::create(Sym, Variant, getContext());
2084  if (IDVal == "b" && Sym->isUndefined())
2085  return Error(Loc, "invalid reference to undefined symbol");
2086  StringRef Identifier = Sym->getName();
2088  AsmTypeInfo Type;
2089  if (SM.onIdentifierExpr(Val, Identifier, Info, Type,
2090  isParsingMSInlineAsm(), ErrMsg))
2091  return Error(Loc, ErrMsg);
2092  End = consumeToken();
2093  } else {
2094  if (SM.onInteger(IntVal, ErrMsg))
2095  return Error(Loc, ErrMsg);
2096  }
2097  } else {
2098  if (SM.onInteger(IntVal, ErrMsg))
2099  return Error(Loc, ErrMsg);
2100  }
2101  break;
2102  }
2103  case AsmToken::Plus:
2104  if (SM.onPlus(ErrMsg))
2105  return Error(getTok().getLoc(), ErrMsg);
2106  break;
2107  case AsmToken::Minus:
2108  if (SM.onMinus(ErrMsg))
2109  return Error(getTok().getLoc(), ErrMsg);
2110  break;
2111  case AsmToken::Tilde: SM.onNot(); break;
2112  case AsmToken::Star: SM.onStar(); break;
2113  case AsmToken::Slash: SM.onDivide(); break;
2114  case AsmToken::Percent: SM.onMod(); break;
2115  case AsmToken::Pipe: SM.onOr(); break;
2116  case AsmToken::Caret: SM.onXor(); break;
2117  case AsmToken::Amp: SM.onAnd(); break;
2118  case AsmToken::LessLess:
2119  SM.onLShift(); break;
2121  SM.onRShift(); break;
2122  case AsmToken::LBrac:
2123  if (SM.onLBrac())
2124  return Error(Tok.getLoc(), "unexpected bracket encountered");
2125  break;
2126  case AsmToken::RBrac:
2127  if (SM.onRBrac())
2128  return Error(Tok.getLoc(), "unexpected bracket encountered");
2129  break;
2130  case AsmToken::LParen: SM.onLParen(); break;
2131  case AsmToken::RParen: SM.onRParen(); break;
2132  }
2133  if (SM.hadError())
2134  return Error(Tok.getLoc(), "unknown token in expression");
2135 
2136  if (!Done && UpdateLocLex)
2137  End = consumeToken();
2138 
2139  PrevTK = TK;
2140  }
2141  return false;
2142 }
2143 
2144 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
2145  SMLoc Start, SMLoc End) {
2146  SMLoc Loc = Start;
2147  unsigned ExprLen = End.getPointer() - Start.getPointer();
2148  // Skip everything before a symbol displacement (if we have one)
2149  if (SM.getSym() && !SM.isOffsetOperator()) {
2150  StringRef SymName = SM.getSymName();
2151  if (unsigned Len = SymName.data() - Start.getPointer())
2152  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
2153  Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
2154  ExprLen = End.getPointer() - (SymName.data() + SymName.size());
2155  // If we have only a symbol than there's no need for complex rewrite,
2156  // simply skip everything after it
2157  if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
2158  if (ExprLen)
2159  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
2160  return;
2161  }
2162  }
2163  // Build an Intel Expression rewrite
2164  StringRef BaseRegStr;
2165  StringRef IndexRegStr;
2166  StringRef OffsetNameStr;
2167  if (SM.getBaseReg())
2168  BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
2169  if (SM.getIndexReg())
2170  IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
2171  if (SM.isOffsetOperator())
2172  OffsetNameStr = SM.getSymName();
2173  // Emit it
2174  IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), OffsetNameStr,
2175  SM.getImm(), SM.isMemExpr());
2176  InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
2177 }
2178 
2179 // Inline assembly may use variable names with namespace alias qualifiers.
2180 bool X86AsmParser::ParseIntelInlineAsmIdentifier(
2181  const MCExpr *&Val, StringRef &Identifier, InlineAsmIdentifierInfo &Info,
2182  bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator) {
2183  MCAsmParser &Parser = getParser();
2184  assert(isParsingMSInlineAsm() && "Expected to be parsing inline assembly.");
2185  Val = nullptr;
2186 
2187  StringRef LineBuf(Identifier.data());
2188  SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
2189 
2190  const AsmToken &Tok = Parser.getTok();
2191  SMLoc Loc = Tok.getLoc();
2192 
2193  // Advance the token stream until the end of the current token is
2194  // after the end of what the frontend claimed.
2195  const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
2196  do {
2197  End = Tok.getEndLoc();
2198  getLexer().Lex();
2199  } while (End.getPointer() < EndPtr);
2200  Identifier = LineBuf;
2201 
2202  // The frontend should end parsing on an assembler token boundary, unless it
2203  // failed parsing.
2204  assert((End.getPointer() == EndPtr ||
2206  "frontend claimed part of a token?");
2207 
2208  // If the identifier lookup was unsuccessful, assume that we are dealing with
2209  // a label.
2211  StringRef InternalName =
2212  SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
2213  Loc, false);
2214  assert(InternalName.size() && "We should have an internal name here.");
2215  // Push a rewrite for replacing the identifier name with the internal name,
2216  // unless we are parsing the operand of an offset operator
2217  if (!IsParsingOffsetOperator)
2218  InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
2219  InternalName);
2220  else
2221  Identifier = InternalName;
2222  } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
2223  return false;
2224  // Create the symbol reference.
2225  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
2227  Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
2228  return false;
2229 }
2230 
2231 //ParseRoundingModeOp - Parse AVX-512 rounding mode operand
2232 bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
2233  MCAsmParser &Parser = getParser();
2234  const AsmToken &Tok = Parser.getTok();
2235  // Eat "{" and mark the current place.
2236  const SMLoc consumedToken = consumeToken();
2237  if (Tok.isNot(AsmToken::Identifier))
2238  return Error(Tok.getLoc(), "Expected an identifier after {");
2239  if (Tok.getIdentifier().startswith("r")){
2240  int rndMode = StringSwitch<int>(Tok.getIdentifier())
2245  .Default(-1);
2246  if (-1 == rndMode)
2247  return Error(Tok.getLoc(), "Invalid rounding mode.");
2248  Parser.Lex(); // Eat "r*" of r*-sae
2249  if (!getLexer().is(AsmToken::Minus))
2250  return Error(Tok.getLoc(), "Expected - at this point");
2251  Parser.Lex(); // Eat "-"
2252  Parser.Lex(); // Eat the sae
2253  if (!getLexer().is(AsmToken::RCurly))
2254  return Error(Tok.getLoc(), "Expected } at this point");
2255  SMLoc End = Tok.getEndLoc();
2256  Parser.Lex(); // Eat "}"
2257  const MCExpr *RndModeOp =
2258  MCConstantExpr::create(rndMode, Parser.getContext());
2259  Operands.push_back(X86Operand::CreateImm(RndModeOp, Start, End));
2260  return false;
2261  }
2262  if(Tok.getIdentifier().equals("sae")){
2263  Parser.Lex(); // Eat the sae
2264  if (!getLexer().is(AsmToken::RCurly))
2265  return Error(Tok.getLoc(), "Expected } at this point");
2266  Parser.Lex(); // Eat "}"
2267  Operands.push_back(X86Operand::CreateToken("{sae}", consumedToken));
2268  return false;
2269  }
2270  return Error(Tok.getLoc(), "unknown token in expression");
2271 }
2272 
2273 /// Parse the '.' operator.
2274 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
2275  SMLoc &End) {
2276  const AsmToken &Tok = getTok();
2278 
2279  // Drop the optional '.'.
2280  StringRef DotDispStr = Tok.getString();
2281  if (DotDispStr.startswith("."))
2282  DotDispStr = DotDispStr.drop_front(1);
2283  StringRef TrailingDot;
2284 
2285  // .Imm gets lexed as a real.
2286  if (Tok.is(AsmToken::Real)) {
2287  APInt DotDisp;
2288  DotDispStr.getAsInteger(10, DotDisp);
2289  Info.Offset = DotDisp.getZExtValue();
2290  } else if ((isParsingMSInlineAsm() || getParser().isParsingMasm()) &&
2291  Tok.is(AsmToken::Identifier)) {
2292  if (DotDispStr.endswith(".")) {
2293  TrailingDot = DotDispStr.substr(DotDispStr.size() - 1);
2294  DotDispStr = DotDispStr.drop_back(1);
2295  }
2296  const std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
2297  const StringRef Base = BaseMember.first, Member = BaseMember.second;
2298  if (getParser().lookUpField(SM.getType(), DotDispStr, Info) &&
2299  getParser().lookUpField(SM.getSymName(), DotDispStr, Info) &&
2300  getParser().lookUpField(DotDispStr, Info) &&
2301  (!SemaCallback ||
2302  SemaCallback->LookupInlineAsmField(Base, Member, Info.Offset)))
2303  return Error(Tok.getLoc(), "Unable to lookup field reference!");
2304  } else {
2305  return Error(Tok.getLoc(), "Unexpected token type!");
2306  }
2307 
2308  // Eat the DotExpression and update End
2309  End = SMLoc::getFromPointer(DotDispStr.data());
2310  const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
2311  while (Tok.getLoc().getPointer() < DotExprEndLoc)
2312  Lex();
2313  if (!TrailingDot.empty())
2314  getLexer().UnLex(AsmToken(AsmToken::Dot, TrailingDot));
2315  SM.addImm(Info.Offset);
2316  SM.setTypeInfo(Info.Type);
2317  return false;
2318 }
2319 
2320 /// Parse the 'offset' operator.
2321 /// This operator is used to specify the location of a given operand
2322 bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
2324  SMLoc &End) {
2325  // Eat offset, mark start of identifier.
2326  SMLoc Start = Lex().getLoc();
2327  ID = getTok().getString();
2328  if (!isParsingMSInlineAsm()) {
2329  if ((getTok().isNot(AsmToken::Identifier) &&
2330  getTok().isNot(AsmToken::String)) ||
2331  getParser().parsePrimaryExpr(Val, End, nullptr))
2332  return Error(Start, "unexpected token!");
2333  } else if (ParseIntelInlineAsmIdentifier(Val, ID, Info, false, End, true)) {
2334  return Error(Start, "unable to lookup expression");
2335  } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) {
2336  return Error(Start, "offset operator cannot yet handle constants");
2337  }
2338  return false;
2339 }
2340 
2341 // Query a candidate string for being an Intel assembly operator
2342 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
2343 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
2345  .Cases("TYPE","type",IOK_TYPE)
2346  .Cases("SIZE","size",IOK_SIZE)
2347  .Cases("LENGTH","length",IOK_LENGTH)
2348  .Default(IOK_INVALID);
2349 }
2350 
2351 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
2352 /// returns the number of elements in an array. It returns the value 1 for
2353 /// non-array variables. The SIZE operator returns the size of a C or C++
2354 /// variable. A variable's size is the product of its LENGTH and TYPE. The
2355 /// TYPE operator returns the size of a C or C++ type or variable. If the
2356 /// variable is an array, TYPE returns the size of a single element.
2357 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
2358  MCAsmParser &Parser = getParser();
2359  const AsmToken &Tok = Parser.getTok();
2360  Parser.Lex(); // Eat operator.
2361 
2362  const MCExpr *Val = nullptr;
2364  SMLoc Start = Tok.getLoc(), End;
2365  StringRef Identifier = Tok.getString();
2366  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
2367  /*IsUnevaluatedOperand=*/true, End))
2368  return 0;
2369 
2370  if (!Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
2371  Error(Start, "unable to lookup expression");
2372  return 0;
2373  }
2374 
2375  unsigned CVal = 0;
2376  switch(OpKind) {
2377  default: llvm_unreachable("Unexpected operand kind!");
2378  case IOK_LENGTH: CVal = Info.Var.Length; break;
2379  case IOK_SIZE: CVal = Info.Var.Size; break;
2380  case IOK_TYPE: CVal = Info.Var.Type; break;
2381  }
2382 
2383  return CVal;
2384 }
2385 
2386 // Query a candidate string for being an Intel assembly operator
2387 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
2388 unsigned X86AsmParser::IdentifyMasmOperator(StringRef Name) {
2389  return StringSwitch<unsigned>(Name.lower())
2390  .Case("type", MOK_TYPE)
2391  .Cases("size", "sizeof", MOK_SIZEOF)
2392  .Cases("length", "lengthof", MOK_LENGTHOF)
2393  .Default(MOK_INVALID);
2394 }
2395 
2396 /// Parse the 'LENGTHOF', 'SIZEOF', and 'TYPE' operators. The LENGTHOF operator
2397 /// returns the number of elements in an array. It returns the value 1 for
2398 /// non-array variables. The SIZEOF operator returns the size of a type or
2399 /// variable in bytes. A variable's size is the product of its LENGTH and TYPE.
2400 /// The TYPE operator returns the size of a variable. If the variable is an
2401 /// array, TYPE returns the size of a single element.
2402 bool X86AsmParser::ParseMasmOperator(unsigned OpKind, int64_t &Val) {
2403  MCAsmParser &Parser = getParser();
2404  SMLoc OpLoc = Parser.getTok().getLoc();
2405  Parser.Lex(); // Eat operator.
2406 
2407  Val = 0;
2408  if (OpKind == MOK_SIZEOF || OpKind == MOK_TYPE) {
2409  // Check for SIZEOF(<type>) and TYPE(<type>).
2410  bool InParens = Parser.getTok().is(AsmToken::LParen);
2411  const AsmToken &IDTok = InParens ? getLexer().peekTok() : Parser.getTok();
2412  AsmTypeInfo Type;
2413  if (IDTok.is(AsmToken::Identifier) &&
2414  !Parser.lookUpType(IDTok.getIdentifier(), Type)) {
2415  Val = Type.Size;
2416 
2417  // Eat tokens.
2418  if (InParens)
2419  parseToken(AsmToken::LParen);
2420  parseToken(AsmToken::Identifier);
2421  if (InParens)
2422  parseToken(AsmToken::RParen);
2423  }
2424  }
2425 
2426  if (!Val) {
2427  IntelExprStateMachine SM;
2428  SMLoc End, Start = Parser.getTok().getLoc();
2429  if (ParseIntelExpression(SM, End))
2430  return true;
2431 
2432  switch (OpKind) {
2433  default:
2434  llvm_unreachable("Unexpected operand kind!");
2435  case MOK_SIZEOF:
2436  Val = SM.getSize();
2437  break;
2438  case MOK_LENGTHOF:
2439  Val = SM.getLength();
2440  break;
2441  case MOK_TYPE:
2442  Val = SM.getElementSize();
2443  break;
2444  }
2445 
2446  if (!Val)
2447  return Error(OpLoc, "expression has unknown type", SMRange(Start, End));
2448  }
2449 
2450  return false;
2451 }
2452 
2453 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
2454  Size = StringSwitch<unsigned>(getTok().getString())
2455  .Cases("BYTE", "byte", 8)
2456  .Cases("WORD", "word", 16)
2457  .Cases("DWORD", "dword", 32)
2458  .Cases("FLOAT", "float", 32)
2459  .Cases("LONG", "long", 32)
2460  .Cases("FWORD", "fword", 48)
2461  .Cases("DOUBLE", "double", 64)
2462  .Cases("QWORD", "qword", 64)
2463  .Cases("MMWORD","mmword", 64)
2464  .Cases("XWORD", "xword", 80)
2465  .Cases("TBYTE", "tbyte", 80)
2466  .Cases("XMMWORD", "xmmword", 128)
2467  .Cases("YMMWORD", "ymmword", 256)
2468  .Cases("ZMMWORD", "zmmword", 512)
2469  .Default(0);
2470  if (Size) {
2471  const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
2472  if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
2473  return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
2474  Lex(); // Eat ptr.
2475  }
2476  return false;
2477 }
2478 
2479 bool X86AsmParser::ParseIntelOperand(OperandVector &Operands) {
2480  MCAsmParser &Parser = getParser();
2481  const AsmToken &Tok = Parser.getTok();
2482  SMLoc Start, End;
2483 
2484  // Parse optional Size directive.
2485  unsigned Size;
2486  if (ParseIntelMemoryOperandSize(Size))
2487  return true;
2488  bool PtrInOperand = bool(Size);
2489 
2490  Start = Tok.getLoc();
2491 
2492  // Rounding mode operand.
2493  if (getLexer().is(AsmToken::LCurly))
2494  return ParseRoundingModeOp(Start, Operands);
2495 
2496  // Register operand.
2497  unsigned RegNo = 0;
2498  if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
2499  if (RegNo == X86::RIP)
2500  return Error(Start, "rip can only be used as a base register");
2501  // A Register followed by ':' is considered a segment override
2502  if (Tok.isNot(AsmToken::Colon)) {
2503  if (PtrInOperand)
2504  return Error(Start, "expected memory operand after 'ptr', "
2505  "found register operand instead");
2506  Operands.push_back(X86Operand::CreateReg(RegNo, Start, End));
2507  return false;
2508  }
2509  // An alleged segment override. check if we have a valid segment register
2510  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
2511  return Error(Start, "invalid segment register");
2512  // Eat ':' and update Start location
2513  Start = Lex().getLoc();
2514  }
2515 
2516  // Immediates and Memory
2517  IntelExprStateMachine SM;
2518  if (ParseIntelExpression(SM, End))
2519  return true;
2520 
2521  if (isParsingMSInlineAsm())
2522  RewriteIntelExpression(SM, Start, Tok.getLoc());
2523 
2524  int64_t Imm = SM.getImm();
2525  const MCExpr *Disp = SM.getSym();
2526  const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
2527  if (Disp && Imm)
2528  Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
2529  if (!Disp)
2530  Disp = ImmDisp;
2531 
2532  // RegNo != 0 specifies a valid segment register,
2533  // and we are parsing a segment override
2534  if (!SM.isMemExpr() && !RegNo) {
2535  if (isParsingMSInlineAsm() && SM.isOffsetOperator()) {
2536  const InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
2537  if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
2538  // Disp includes the address of a variable; make sure this is recorded
2539  // for later handling.
2540  Operands.push_back(X86Operand::CreateImm(Disp, Start, End,
2541  SM.getSymName(), Info.Var.Decl,
2542  Info.Var.IsGlobalLV));
2543  return false;
2544  }
2545  }
2546 
2547  Operands.push_back(X86Operand::CreateImm(Disp, Start, End));
2548  return false;
2549  }
2550 
2551  StringRef ErrMsg;
2552  unsigned BaseReg = SM.getBaseReg();
2553  unsigned IndexReg = SM.getIndexReg();
2554  unsigned Scale = SM.getScale();
2555  if (!PtrInOperand)
2556  Size = SM.getElementSize() << 3;
2557 
2558  if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
2559  (IndexReg == X86::ESP || IndexReg == X86::RSP))
2560  std::swap(BaseReg, IndexReg);
2561 
2562  // If BaseReg is a vector register and IndexReg is not, swap them unless
2563  // Scale was specified in which case it would be an error.
2564  if (Scale == 0 &&
2565  !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
2566  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
2567  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
2568  (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
2569  X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
2570  X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
2571  std::swap(BaseReg, IndexReg);
2572 
2573  if (Scale != 0 &&
2574  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
2575  return Error(Start, "16-bit addresses cannot have a scale");
2576 
2577  // If there was no explicit scale specified, change it to 1.
2578  if (Scale == 0)
2579  Scale = 1;
2580 
2581  // If this is a 16-bit addressing mode with the base and index in the wrong
2582  // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
2583  // shared with att syntax where order matters.
2584  if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
2585  (IndexReg == X86::BX || IndexReg == X86::BP))
2586  std::swap(BaseReg, IndexReg);
2587 
2588  if ((BaseReg || IndexReg) &&
2589  CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2590  ErrMsg))
2591  return Error(Start, ErrMsg);
2592  if (isParsingMSInlineAsm())
2593  return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale, Start,
2594  End, Size, SM.getSymName(),
2595  SM.getIdentifierInfo(), Operands);
2596 
2597  // When parsing x64 MS-style assembly, all non-absolute references to a named
2598  // variable default to RIP-relative.
2599  if (Parser.isParsingMasm() && is64BitMode() && SM.getElementSize() > 0) {
2600  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
2601  BaseReg, IndexReg, Scale, Start,
2602  End, Size,
2603  /*DefaultBaseReg=*/X86::RIP));
2604  return false;
2605  }
2606 
2607  if ((BaseReg || IndexReg || RegNo))
2608  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
2609  BaseReg, IndexReg, Scale, Start,
2610  End, Size));
2611  else
2612  Operands.push_back(
2613  X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
2614  return false;
2615 }
2616 
2617 bool X86AsmParser::ParseATTOperand(OperandVector &Operands) {
2618  MCAsmParser &Parser = getParser();
2619  switch (getLexer().getKind()) {
2620  case AsmToken::Dollar: {
2621  // $42 or $ID -> immediate.
2622  SMLoc Start = Parser.getTok().getLoc(), End;
2623  Parser.Lex();
2624  const MCExpr *Val;
2625  // This is an immediate, so we should not parse a register. Do a precheck
2626  // for '%' to supercede intra-register parse errors.
2627  SMLoc L = Parser.getTok().getLoc();
2628  if (check(getLexer().is(AsmToken::Percent), L,
2629  "expected immediate expression") ||
2630  getParser().parseExpression(Val, End) ||
2631  check(isa<X86MCExpr>(Val), L, "expected immediate expression"))
2632  return true;
2633  Operands.push_back(X86Operand::CreateImm(Val, Start, End));
2634  return false;
2635  }
2636  case AsmToken::LCurly: {
2637  SMLoc Start = Parser.getTok().getLoc();
2638  return ParseRoundingModeOp(Start, Operands);
2639  }
2640  default: {
2641  // This a memory operand or a register. We have some parsing complications
2642  // as a '(' may be part of an immediate expression or the addressing mode
2643  // block. This is complicated by the fact that an assembler-level variable
2644  // may refer either to a register or an immediate expression.
2645 
2646  SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
2647  const MCExpr *Expr = nullptr;
2648  unsigned Reg = 0;
2649  if (getLexer().isNot(AsmToken::LParen)) {
2650  // No '(' so this is either a displacement expression or a register.
2651  if (Parser.parseExpression(Expr, EndLoc))
2652  return true;
2653  if (auto *RE = dyn_cast<X86MCExpr>(Expr)) {
2654  // Segment Register. Reset Expr and copy value to register.
2655  Expr = nullptr;
2656  Reg = RE->getRegNo();
2657 
2658  // Sanity check register.
2659  if (Reg == X86::EIZ || Reg == X86::RIZ)
2660  return Error(
2661  Loc, "%eiz and %riz can only be used as index registers",
2662  SMRange(Loc, EndLoc));
2663  if (Reg == X86::RIP)
2664  return Error(Loc, "%rip can only be used as a base register",
2665  SMRange(Loc, EndLoc));
2666  // Return register that are not segment prefixes immediately.
2667  if (!Parser.parseOptionalToken(AsmToken::Colon)) {
2668  Operands.push_back(X86Operand::CreateReg(Reg, Loc, EndLoc));
2669  return false;
2670  }
2671  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
2672  return Error(Loc, "invalid segment register");
2673  // Accept a '*' absolute memory reference after the segment. Place it
2674  // before the full memory operand.
2675  if (getLexer().is(AsmToken::Star))
2676  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2677  }
2678  }
2679  // This is a Memory operand.
2680  return ParseMemOperand(Reg, Expr, Loc, EndLoc, Operands);
2681  }
2682  }
2683 }
2684 
2685 // X86::COND_INVALID if not a recognized condition code or alternate mnemonic,
2686 // otherwise the EFLAGS Condition Code enumerator.
2687 X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
2688  return StringSwitch<X86::CondCode>(CC)
2689  .Case("o", X86::COND_O) // Overflow
2690  .Case("no", X86::COND_NO) // No Overflow
2691  .Cases("b", "nae", X86::COND_B) // Below/Neither Above nor Equal
2692  .Cases("ae", "nb", X86::COND_AE) // Above or Equal/Not Below
2693  .Cases("e", "z", X86::COND_E) // Equal/Zero
2694  .Cases("ne", "nz", X86::COND_NE) // Not Equal/Not Zero
2695  .Cases("be", "na", X86::COND_BE) // Below or Equal/Not Above
2696  .Cases("a", "nbe", X86::COND_A) // Above/Neither Below nor Equal
2697  .Case("s", X86::COND_S) // Sign
2698  .Case("ns", X86::COND_NS) // No Sign
2699  .Cases("p", "pe", X86::COND_P) // Parity/Parity Even
2700  .Cases("np", "po", X86::COND_NP) // No Parity/Parity Odd
2701  .Cases("l", "nge", X86::COND_L) // Less/Neither Greater nor Equal
2702  .Cases("ge", "nl", X86::COND_GE) // Greater or Equal/Not Less
2703  .Cases("le", "ng", X86::COND_LE) // Less or Equal/Not Greater
2704  .Cases("g", "nle", X86::COND_G) // Greater/Neither Less nor Equal
2706 }
2707 
2708 // true on failure, false otherwise
2709 // If no {z} mark was found - Parser doesn't advance
2710 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2711  const SMLoc &StartLoc) {
2712  MCAsmParser &Parser = getParser();
2713  // Assuming we are just pass the '{' mark, quering the next token
2714  // Searched for {z}, but none was found. Return false, as no parsing error was
2715  // encountered
2716  if (!(getLexer().is(AsmToken::Identifier) &&
2717  (getLexer().getTok().getIdentifier() == "z")))
2718  return false;
2719  Parser.Lex(); // Eat z
2720  // Query and eat the '}' mark
2721  if (!getLexer().is(AsmToken::RCurly))
2722  return Error(getLexer().getLoc(), "Expected } at this point");
2723  Parser.Lex(); // Eat '}'
2724  // Assign Z with the {z} mark opernad
2725  Z = X86Operand::CreateToken("{z}", StartLoc);
2726  return false;
2727 }
2728 
2729 // true on failure, false otherwise
2730 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
2731  MCAsmParser &Parser = getParser();
2732  if (getLexer().is(AsmToken::LCurly)) {
2733  // Eat "{" and mark the current place.
2734  const SMLoc consumedToken = consumeToken();
2735  // Distinguish {1to<NUM>} from {%k<NUM>}.
2736  if(getLexer().is(AsmToken::Integer)) {
2737  // Parse memory broadcasting ({1to<NUM>}).
2738  if (getLexer().getTok().getIntVal() != 1)
2739  return TokError("Expected 1to<NUM> at this point");
2740  StringRef Prefix = getLexer().getTok().getString();
2741  Parser.Lex(); // Eat first token of 1to8
2742  if (!getLexer().is(AsmToken::Identifier))
2743  return TokError("Expected 1to<NUM> at this point");
2744  // Recognize only reasonable suffixes.
2745  SmallVector<char, 5> BroadcastVector;
2746  StringRef BroadcastString = (Prefix + getLexer().getTok().getIdentifier())
2747  .toStringRef(BroadcastVector);
2748  if (!BroadcastString.startswith("1to"))
2749  return TokError("Expected 1to<NUM> at this point");
2750  const char *BroadcastPrimitive =
2751  StringSwitch<const char *>(BroadcastString)
2752  .Case("1to2", "{1to2}")
2753  .Case("1to4", "{1to4}")
2754  .Case("1to8", "{1to8}")
2755  .Case("1to16", "{1to16}")
2756  .Case("1to32", "{1to32}")
2757  .Default(nullptr);
2758  if (!BroadcastPrimitive)
2759  return TokError("Invalid memory broadcast primitive.");
2760  Parser.Lex(); // Eat trailing token of 1toN
2761  if (!getLexer().is(AsmToken::RCurly))
2762  return TokError("Expected } at this point");
2763  Parser.Lex(); // Eat "}"
2764  Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
2765  consumedToken));
2766  // No AVX512 specific primitives can pass
2767  // after memory broadcasting, so return.
2768  return false;
2769  } else {
2770  // Parse either {k}{z}, {z}{k}, {k} or {z}
2771  // last one have no meaning, but GCC accepts it
2772  // Currently, we're just pass a '{' mark
2773  std::unique_ptr<X86Operand> Z;
2774  if (ParseZ(Z, consumedToken))
2775  return true;
2776  // Reaching here means that parsing of the allegadly '{z}' mark yielded
2777  // no errors.
2778  // Query for the need of further parsing for a {%k<NUM>} mark
2779  if (!Z || getLexer().is(AsmToken::LCurly)) {
2780  SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2781  // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2782  // expected
2783  unsigned RegNo;
2784  SMLoc RegLoc;
2785  if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
2786  X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
2787  if (RegNo == X86::K0)
2788  return Error(RegLoc, "Register k0 can't be used as write mask");
2789  if (!getLexer().is(AsmToken::RCurly))
2790  return Error(getLexer().getLoc(), "Expected } at this point");
2791  Operands.push_back(X86Operand::CreateToken("{", StartLoc));
2792  Operands.push_back(
2793  X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
2794  Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2795  } else
2796  return Error(getLexer().getLoc(),
2797  "Expected an op-mask register at this point");
2798  // {%k<NUM>} mark is found, inquire for {z}
2799  if (getLexer().is(AsmToken::LCurly) && !Z) {
2800  // Have we've found a parsing error, or found no (expected) {z} mark
2801  // - report an error
2802  if (ParseZ(Z, consumeToken()) || !Z)
2803  return Error(getLexer().getLoc(),
2804  "Expected a {z} mark at this point");
2805 
2806  }
2807  // '{z}' on its own is meaningless, hence should be ignored.
2808  // on the contrary - have it been accompanied by a K register,
2809  // allow it.
2810  if (Z)
2811  Operands.push_back(std::move(Z));
2812  }
2813  }
2814  }
2815  return false;
2816 }
2817 
2818 /// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
2819 /// has already been parsed if present. disp may be provided as well.
2820 bool X86AsmParser::ParseMemOperand(unsigned SegReg, const MCExpr *Disp,
2821  SMLoc StartLoc, SMLoc EndLoc,
2823  MCAsmParser &Parser = getParser();
2824  SMLoc Loc;
2825  // Based on the initial passed values, we may be in any of these cases, we are
2826  // in one of these cases (with current position (*)):
2827 
2828  // 1. seg : * disp (base-index-scale-expr)
2829  // 2. seg : *(disp) (base-index-scale-expr)
2830  // 3. seg : *(base-index-scale-expr)
2831  // 4. disp *(base-index-scale-expr)
2832  // 5. *(disp) (base-index-scale-expr)
2833  // 6. *(base-index-scale-expr)
2834  // 7. disp *
2835  // 8. *(disp)
2836 
2837  // If we do not have an displacement yet, check if we're in cases 4 or 6 by
2838  // checking if the first object after the parenthesis is a register (or an
2839  // identifier referring to a register) and parse the displacement or default
2840  // to 0 as appropriate.
2841  auto isAtMemOperand = [this]() {
2842  if (this->getLexer().isNot(AsmToken::LParen))
2843  return false;
2844  AsmToken Buf[2];
2845  StringRef Id;
2846  auto TokCount = this->getLexer().peekTokens(Buf, true);
2847  if (TokCount == 0)
2848  return false;
2849  switch (Buf[0].getKind()) {
2850  case AsmToken::Percent:
2851  case AsmToken::Comma:
2852  return true;
2853  // These lower cases are doing a peekIdentifier.
2854  case AsmToken::At:
2855  case AsmToken::Dollar:
2856  if ((TokCount > 1) &&
2857  (Buf[1].is(AsmToken::Identifier) || Buf[1].is(AsmToken::String)) &&
2858  (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
2859  Id = StringRef(Buf[0].getLoc().getPointer(),
2860  Buf[1].getIdentifier().size() + 1);
2861  break;
2862  case AsmToken::Identifier:
2863  case AsmToken::String:
2864  Id = Buf[0].getIdentifier();
2865  break;
2866  default:
2867  return false;
2868  }
2869  // We have an ID. Check if it is bound to a register.
2870  if (!Id.empty()) {
2871  MCSymbol *Sym = this->getContext().getOrCreateSymbol(Id);
2872  if (Sym->isVariable()) {
2873  auto V = Sym->getVariableValue(/*SetUsed*/ false);
2874  return isa<X86MCExpr>(V);
2875  }
2876  }
2877  return false;
2878  };
2879 
2880  if (!Disp) {
2881  // Parse immediate if we're not at a mem operand yet.
2882  if (!isAtMemOperand()) {
2883  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Disp, EndLoc))
2884  return true;
2885  assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
2886  } else {
2887  // Disp is implicitly zero if we haven't parsed it yet.
2888  Disp = MCConstantExpr::create(0, Parser.getContext());
2889  }
2890  }
2891 
2892  // We are now either at the end of the operand or at the '(' at the start of a
2893  // base-index-scale-expr.
2894 
2895  if (!parseOptionalToken(AsmToken::LParen)) {
2896  if (SegReg == 0)
2897  Operands.push_back(
2898  X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
2899  else
2900  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
2901  0, 0, 1, StartLoc, EndLoc));
2902  return false;
2903  }
2904 
2905  // If we reached here, then eat the '(' and Process
2906  // the rest of the memory operand.
2907  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2908  SMLoc BaseLoc = getLexer().getLoc();
2909  const MCExpr *E;
2910  StringRef ErrMsg;
2911 
2912  // Parse BaseReg if one is provided.
2913  if (getLexer().isNot(AsmToken::Comma) && getLexer().isNot(AsmToken::RParen)) {
2914  if (Parser.parseExpression(E, EndLoc) ||
2915  check(!isa<X86MCExpr>(E), BaseLoc, "expected register here"))
2916  return true;
2917 
2918  // Sanity check register.
2919  BaseReg = cast<X86MCExpr>(E)->getRegNo();
2920  if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
2921  return Error(BaseLoc, "eiz and riz can only be used as index registers",
2922  SMRange(BaseLoc, EndLoc));
2923  }
2924 
2925  if (parseOptionalToken(AsmToken::Comma)) {
2926  // Following the comma we should have either an index register, or a scale
2927  // value. We don't support the later form, but we want to parse it
2928  // correctly.
2929  //
2930  // Even though it would be completely consistent to support syntax like
2931  // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2932  if (getLexer().isNot(AsmToken::RParen)) {
2933  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(E, EndLoc))
2934  return true;
2935 
2936  if (!isa<X86MCExpr>(E)) {
2937  // We've parsed an unexpected Scale Value instead of an index
2938  // register. Interpret it as an absolute.
2939  int64_t ScaleVal;
2940  if (!E->evaluateAsAbsolute(ScaleVal, getStreamer().getAssemblerPtr()))
2941  return Error(Loc, "expected absolute expression");
2942  if (ScaleVal != 1)
2943  Warning(Loc, "scale factor without index register is ignored");
2944  Scale = 1;
2945  } else { // IndexReg Found.
2946  IndexReg = cast<X86MCExpr>(E)->getRegNo();
2947 
2948  if (BaseReg == X86::RIP)
2949  return Error(Loc,
2950  "%rip as base register can not have an index register");
2951  if (IndexReg == X86::RIP)
2952  return Error(Loc, "%rip is not allowed as an index register");
2953 
2954  if (parseOptionalToken(AsmToken::Comma)) {
2955  // Parse the scale amount:
2956  // ::= ',' [scale-expression]
2957 
2958  // A scale amount without an index is ignored.
2959  if (getLexer().isNot(AsmToken::RParen)) {
2960  int64_t ScaleVal;
2961  if (Parser.parseTokenLoc(Loc) ||
2962  Parser.parseAbsoluteExpression(ScaleVal))
2963  return Error(Loc, "expected scale expression");
2964  Scale = (unsigned)ScaleVal;
2965  // Validate the scale amount.
2966  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2967  Scale != 1)
2968  return Error(Loc, "scale factor in 16-bit address must be 1");
2969  if (checkScale(Scale, ErrMsg))
2970  return Error(Loc, ErrMsg);
2971  }
2972  }
2973  }
2974  }
2975  }
2976 
2977  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2978  if (parseToken(AsmToken::RParen, "unexpected token in memory operand"))
2979  return true;
2980 
2981  // This is to support otherwise illegal operand (%dx) found in various
2982  // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
2983  // be supported. Mark such DX variants separately fix only in special cases.
2984  if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
2985  isa<MCConstantExpr>(Disp) &&
2986  cast<MCConstantExpr>(Disp)->getValue() == 0) {
2987  Operands.push_back(X86Operand::CreateDXReg(BaseLoc, BaseLoc));
2988  return false;
2989  }
2990 
2991  if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2992  ErrMsg))
2993  return Error(BaseLoc, ErrMsg);
2994 
2995  if (SegReg || BaseReg || IndexReg)
2996  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
2997  BaseReg, IndexReg, Scale, StartLoc,
2998  EndLoc));
2999  else
3000  Operands.push_back(
3001  X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
3002  return false;
3003 }
3004 
3005 // Parse either a standard primary expression or a register.
3006 bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
3007  MCAsmParser &Parser = getParser();
3008  // See if this is a register first.
3009  if (getTok().is(AsmToken::Percent) ||
3010  (isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
3011  MatchRegisterName(Parser.getTok().getString()))) {
3012  SMLoc StartLoc = Parser.getTok().getLoc();
3013  unsigned RegNo;
3014  if (ParseRegister(RegNo, StartLoc, EndLoc))
3015  return true;
3016  Res = X86MCExpr::create(RegNo, Parser.getContext());
3017  return false;
3018  }
3019  return Parser.parsePrimaryExpr(Res, EndLoc, nullptr);
3020 }
3021 
3022 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
3023  SMLoc NameLoc, OperandVector &Operands) {
3024  MCAsmParser &Parser = getParser();
3025  InstInfo = &Info;
3026 
3027  // Reset the forced VEX encoding.
3028  ForcedVEXEncoding = VEXEncoding_Default;
3029  ForcedDispEncoding = DispEncoding_Default;
3030 
3031  // Parse pseudo prefixes.
3032  while (1) {
3033  if (Name == "{") {
3034  if (getLexer().isNot(AsmToken::Identifier))
3035  return Error(Parser.getTok().getLoc(), "Unexpected token after '{'");
3036  std::string Prefix = Parser.getTok().getString().lower();
3037  Parser.Lex(); // Eat identifier.
3038  if (getLexer().isNot(AsmToken::RCurly))
3039  return Error(Parser.getTok().getLoc(), "Expected '}'");
3040  Parser.Lex(); // Eat curly.
3041 
3042  if (Prefix == "vex")
3043  ForcedVEXEncoding = VEXEncoding_VEX;
3044  else if (Prefix == "vex2")
3045  ForcedVEXEncoding = VEXEncoding_VEX2;
3046  else if (Prefix == "vex3")
3047  ForcedVEXEncoding = VEXEncoding_VEX3;
3048  else if (Prefix == "evex")
3049  ForcedVEXEncoding = VEXEncoding_EVEX;
3050  else if (Prefix == "disp8")
3051  ForcedDispEncoding = DispEncoding_Disp8;
3052  else if (Prefix == "disp32")
3053  ForcedDispEncoding = DispEncoding_Disp32;
3054  else
3055  return Error(NameLoc, "unknown prefix");
3056 
3057  NameLoc = Parser.getTok().getLoc();
3058  if (getLexer().is(AsmToken::LCurly)) {
3059  Parser.Lex();
3060  Name = "{";
3061  } else {
3062  if (getLexer().isNot(AsmToken::Identifier))
3063  return Error(Parser.getTok().getLoc(), "Expected identifier");
3064  // FIXME: The mnemonic won't match correctly if its not in lower case.
3065  Name = Parser.getTok().getString();
3066  Parser.Lex();
3067  }
3068  continue;
3069  }
3070  // Parse MASM style pseudo prefixes.
3071  if (isParsingMSInlineAsm()) {
3072  if (Name.equals_insensitive("vex"))
3073  ForcedVEXEncoding = VEXEncoding_VEX;
3074  else if (Name.equals_insensitive("vex2"))
3075  ForcedVEXEncoding = VEXEncoding_VEX2;
3076  else if (Name.equals_insensitive("vex3"))
3077  ForcedVEXEncoding = VEXEncoding_VEX3;
3078  else if (Name.equals_insensitive("evex"))
3079  ForcedVEXEncoding = VEXEncoding_EVEX;
3080 
3081  if (ForcedVEXEncoding != VEXEncoding_Default) {
3082  if (getLexer().isNot(AsmToken::Identifier))
3083  return Error(Parser.getTok().getLoc(), "Expected identifier");
3084  // FIXME: The mnemonic won't match correctly if its not in lower case.
3085  Name = Parser.getTok().getString();
3086  NameLoc = Parser.getTok().getLoc();
3087  Parser.Lex();
3088  }
3089  }
3090  break;
3091  }
3092 
3093  // Support the suffix syntax for overriding displacement size as well.
3094  if (Name.consume_back(".d32")) {
3095  ForcedDispEncoding = DispEncoding_Disp32;
3096  } else if (Name.consume_back(".d8")) {
3097  ForcedDispEncoding = DispEncoding_Disp8;
3098  }
3099 
3100  StringRef PatchedName = Name;
3101 
3102  // Hack to skip "short" following Jcc.
3103  if (isParsingIntelSyntax() &&
3104  (PatchedName == "jmp" || PatchedName == "jc" || PatchedName == "jnc" ||
3105  PatchedName == "jcxz" || PatchedName == "jecxz" ||
3106  (PatchedName.startswith("j") &&
3107  ParseConditionCode(PatchedName.substr(1)) != X86::COND_INVALID))) {
3108  StringRef NextTok = Parser.getTok().getString();
3109  if (Parser.isParsingMasm() ? NextTok.equals_insensitive("short")
3110  : NextTok == "short") {
3111  SMLoc NameEndLoc =
3112  NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
3113  // Eat the short keyword.
3114  Parser.Lex();
3115  // MS and GAS ignore the short keyword; they both determine the jmp type
3116  // based on the distance of the label. (NASM does emit different code with
3117  // and without "short," though.)
3118  InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
3119  NextTok.size() + 1);
3120  }
3121  }
3122 
3123  // FIXME: Hack to recognize setneb as setne.
3124  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
3125  PatchedName != "setb" && PatchedName != "setnb")
3126  PatchedName = PatchedName.substr(0, Name.size()-1);
3127 
3128  unsigned ComparisonPredicate = ~0U;
3129 
3130  // FIXME: Hack to recognize cmp<comparison code>{sh,ss,sd,ph,ps,pd}.
3131  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
3132  (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
3133  PatchedName.endswith("sh") || PatchedName.endswith("ph") ||
3134  PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
3135  bool IsVCMP = PatchedName[0] == 'v';
3136  unsigned CCIdx = IsVCMP ? 4 : 3;
3137  unsigned CC = StringSwitch<unsigned>(
3138  PatchedName.slice(CCIdx, PatchedName.size() - 2))
3139  .Case("eq", 0x00)
3140  .Case("eq_oq", 0x00)
3141  .Case("lt", 0x01)
3142  .Case("lt_os", 0x01)
3143  .Case("le", 0x02)
3144  .Case("le_os", 0x02)
3145  .Case("unord", 0x03)
3146  .Case("unord_q", 0x03)
3147  .Case("neq", 0x04)
3148  .Case("neq_uq", 0x04)
3149  .Case("nlt", 0x05)
3150  .Case("nlt_us", 0x05)
3151  .Case("nle", 0x06)
3152  .Case("nle_us", 0x06)
3153  .Case("ord", 0x07)
3154  .Case("ord_q", 0x07)
3155  /* AVX only from here */
3156  .Case("eq_uq", 0x08)
3157  .Case("nge", 0x09)
3158  .Case("nge_us", 0x09)
3159  .Case("ngt", 0x0A)
3160  .Case("ngt_us", 0x0A)
3161  .Case("false", 0x0B)
3162  .Case("false_oq", 0x0B)
3163  .Case("neq_oq", 0x0C)
3164  .Case("ge", 0x0D)
3165  .Case("ge_os", 0x0D)
3166  .Case("gt", 0x0E)
3167  .Case("gt_os", 0x0E)
3168  .Case("true", 0x0F)
3169  .Case("true_uq", 0x0F)
3170  .Case("eq_os", 0x10)
3171  .Case("lt_oq", 0x11)
3172  .Case("le_oq", 0x12)
3173  .Case("unord_s", 0x13)
3174  .Case("neq_us", 0x14)
3175  .Case("nlt_uq", 0x15)
3176  .Case("nle_uq", 0x16)
3177  .Case("ord_s", 0x17)
3178  .Case("eq_us", 0x18)
3179  .Case("nge_uq", 0x19)
3180  .Case("ngt_uq", 0x1A)
3181  .Case("false_os", 0x1B)
3182  .Case("neq_os", 0x1C)
3183  .Case("ge_oq", 0x1D)
3184  .Case("gt_oq", 0x1E)
3185  .Case("true_us", 0x1F)
3186  .Default(~0U);
3187  if (CC != ~0U && (IsVCMP || CC < 8) &&
3188  (IsVCMP || PatchedName.back() != 'h')) {
3189  if (PatchedName.endswith("ss"))
3190  PatchedName = IsVCMP ? "vcmpss" : "cmpss";
3191  else if (PatchedName.endswith("sd"))
3192  PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
3193  else if (PatchedName.endswith("ps"))
3194  PatchedName = IsVCMP ? "vcmpps" : "cmpps";
3195  else if (PatchedName.endswith("pd"))
3196  PatchedName = IsVCMP ? "vcmppd" : "cmppd";
3197  else if (PatchedName.endswith("sh"))
3198  PatchedName = "vcmpsh";
3199  else if (PatchedName.endswith("ph"))
3200  PatchedName = "vcmpph";
3201  else
3202  llvm_unreachable("Unexpected suffix!");
3203 
3204  ComparisonPredicate = CC;
3205  }
3206  }
3207 
3208  // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3209  if (PatchedName.startswith("vpcmp") &&
3210  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3211  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3212  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3213  unsigned CC = StringSwitch<unsigned>(
3214  PatchedName.slice(5, PatchedName.size() - SuffixSize))
3215  .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
3216  .Case("lt", 0x1)
3217  .Case("le", 0x2)
3218  //.Case("false", 0x3) // Not a documented alias.
3219  .Case("neq", 0x4)
3220  .Case("nlt", 0x5)
3221  .Case("nle", 0x6)
3222  //.Case("true", 0x7) // Not a documented alias.
3223  .Default(~0U);
3224  if (CC != ~0U && (CC != 0 || SuffixSize == 2)) {
3225  switch (PatchedName.back()) {
3226  default: llvm_unreachable("Unexpected character!");
3227  case 'b': PatchedName = SuffixSize == 2 ? "vpcmpub" : "vpcmpb"; break;
3228  case 'w': PatchedName = SuffixSize == 2 ? "vpcmpuw" : "vpcmpw"; break;
3229  case 'd': PatchedName = SuffixSize == 2 ? "vpcmpud" : "vpcmpd"; break;
3230  case 'q': PatchedName = SuffixSize == 2 ? "vpcmpuq" : "vpcmpq"; break;
3231  }
3232  // Set up the immediate to push into the operands later.
3233  ComparisonPredicate = CC;
3234  }
3235  }
3236 
3237  // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3238  if (PatchedName.startswith("vpcom") &&
3239  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3240  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3241  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3242  unsigned CC = StringSwitch<unsigned>(
3243  PatchedName.slice(5, PatchedName.size() - SuffixSize))
3244  .Case("lt", 0x0)
3245  .Case("le", 0x1)
3246  .Case("gt", 0x2)
3247  .Case("ge", 0x3)
3248  .Case("eq", 0x4)
3249  .Case("neq", 0x5)
3250  .Case("false", 0x6)
3251  .Case("true", 0x7)
3252  .Default(~0U);
3253  if (CC != ~0U) {
3254  switch (PatchedName.back()) {
3255  default: llvm_unreachable("Unexpected character!");
3256  case 'b': PatchedName = SuffixSize == 2 ? "vpcomub" : "vpcomb"; break;
3257  case 'w': PatchedName = SuffixSize == 2 ? "vpcomuw" : "vpcomw"; break;
3258  case 'd': PatchedName = SuffixSize == 2 ? "vpcomud" : "vpcomd"; break;
3259  case 'q': PatchedName = SuffixSize == 2 ? "vpcomuq" : "vpcomq"; break;
3260  }
3261  // Set up the immediate to push into the operands later.
3262  ComparisonPredicate = CC;
3263  }
3264  }
3265 
3266 
3267  // Determine whether this is an instruction prefix.
3268  // FIXME:
3269  // Enhance prefixes integrity robustness. for example, following forms
3270  // are currently tolerated:
3271  // repz repnz <insn> ; GAS errors for the use of two similar prefixes
3272  // lock addq %rax, %rbx ; Destination operand must be of memory type
3273  // xacquire <insn> ; xacquire must be accompanied by 'lock'
3274  bool IsPrefix =
3276  .Cases("cs", "ds", "es", "fs", "gs", "ss", true)
3277  .Cases("rex64", "data32", "data16", "addr32", "addr16", true)
3278  .Cases("xacquire", "xrelease", true)
3279  .Cases("acquire", "release", isParsingIntelSyntax())
3280  .Default(false);
3281 
3282  auto isLockRepeatNtPrefix = [](StringRef N) {
3283  return StringSwitch<bool>(N)
3284  .Cases("lock", "rep", "repe", "repz", "repne", "repnz", "notrack", true)
3285  .Default(false);
3286  };
3287 
3288  bool CurlyAsEndOfStatement = false;
3289 
3290  unsigned Flags = X86::IP_NO_PREFIX;
3291  while (isLockRepeatNtPrefix(Name.lower())) {
3292  unsigned Prefix =
3294  .Cases("lock", "lock", X86::IP_HAS_LOCK)
3295  .Cases("rep", "repe", "repz", X86::IP_HAS_REPEAT)
3296  .Cases("repne", "repnz", X86::IP_HAS_REPEAT_NE)
3297  .Cases("notrack", "notrack", X86::IP_HAS_NOTRACK)
3298  .Default(X86::IP_NO_PREFIX); // Invalid prefix (impossible)
3299  Flags |= Prefix;
3300  if (getLexer().is(AsmToken::EndOfStatement)) {
3301  // We don't have real instr with the given prefix
3302  // let's use the prefix as the instr.
3303  // TODO: there could be several prefixes one after another
3304  Flags = X86::IP_NO_PREFIX;
3305  break;
3306  }
3307  // FIXME: The mnemonic won't match correctly if its not in lower case.
3308  Name = Parser.getTok().getString();
3309  Parser.Lex(); // eat the prefix
3310  // Hack: we could have something like "rep # some comment" or
3311  // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
3312  while (Name.startswith(";") || Name.startswith("\n") ||
3313  Name.startswith("#") || Name.startswith("\t") ||
3314  Name.startswith("/")) {
3315  // FIXME: The mnemonic won't match correctly if its not in lower case.
3316  Name = Parser.getTok().getString();
3317  Parser.Lex(); // go to next prefix or instr
3318  }
3319  }
3320 
3321  if (Flags)
3322  PatchedName = Name;
3323 
3324  // Hacks to handle 'data16' and 'data32'
3325  if (PatchedName == "data16" && is16BitMode()) {
3326  return Error(NameLoc, "redundant data16 prefix");
3327  }
3328  if (PatchedName == "data32") {
3329  if (is32BitMode())
3330  return Error(NameLoc, "redundant data32 prefix");
3331  if (is64BitMode())
3332  return Error(NameLoc, "'data32' is not supported in 64-bit mode");
3333  // Hack to 'data16' for the table lookup.
3334  PatchedName = "data16";
3335 
3336  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3337  StringRef Next = Parser.getTok().getString();
3338  getLexer().Lex();
3339  // data32 effectively changes the instruction suffix.
3340  // TODO Generalize.
3341  if (Next == "callw")
3342  Next = "calll";
3343  if (Next == "ljmpw")
3344  Next = "ljmpl";
3345 
3346  Name = Next;
3347  PatchedName = Name;
3348  ForcedDataPrefix = X86::Mode32Bit;
3349  IsPrefix = false;
3350  }
3351  }
3352 
3353  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
3354 
3355  // Push the immediate if we extracted one from the mnemonic.
3356  if (ComparisonPredicate != ~0U && !isParsingIntelSyntax()) {
3357  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
3358  getParser().getContext());
3359  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
3360  }
3361 
3362  // This does the actual operand parsing. Don't parse any more if we have a
3363  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
3364  // just want to parse the "lock" as the first instruction and the "incl" as
3365  // the next one.
3366  if (getLexer().isNot(AsmToken::EndOfStatement) && !IsPrefix) {
3367  // Parse '*' modifier.
3368  if (getLexer().is(AsmToken::Star))
3369  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
3370 
3371  // Read the operands.
3372  while(1) {
3373  if (ParseOperand(Operands))
3374  return true;
3375  if (HandleAVX512Operand(Operands))
3376  return true;
3377 
3378  // check for comma and eat it
3379  if (getLexer().is(AsmToken::Comma))
3380  Parser.Lex();
3381  else
3382  break;
3383  }
3384 
3385  // In MS inline asm curly braces mark the beginning/end of a block,
3386  // therefore they should be interepreted as end of statement
3387  CurlyAsEndOfStatement =
3388  isParsingIntelSyntax() && isParsingMSInlineAsm() &&
3389  (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
3390  if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
3391  return TokError("unexpected token in argument list");
3392  }
3393 
3394  // Push the immediate if we extracted one from the mnemonic.
3395  if (ComparisonPredicate != ~0U && isParsingIntelSyntax()) {
3396  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
3397  getParser().getContext());
3398  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
3399  }
3400 
3401  // Consume the EndOfStatement or the prefix separator Slash
3402  if (getLexer().is(AsmToken::EndOfStatement) ||
3403  (IsPrefix && getLexer().is(AsmToken::Slash)))
3404  Parser.Lex();
3405  else if (CurlyAsEndOfStatement)
3406  // Add an actual EndOfStatement before the curly brace
3407  Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
3408  getLexer().getTok().getLoc(), 0);
3409 
3410  // This is for gas compatibility and cannot be done in td.
3411  // Adding "p" for some floating point with no argument.
3412  // For example: fsub --> fsubp
3413  bool IsFp =
3414  Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
3415  if (IsFp && Operands.size() == 1) {
3416  const char *Repl = StringSwitch<const char *>(Name)
3417  .Case("fsub", "fsubp")
3418  .Case("fdiv", "fdivp")
3419  .Case("fsubr", "fsubrp")
3420  .Case("fdivr", "fdivrp");
3421  static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
3422  }
3423 
3424  if ((Name == "mov" || Name == "movw" || Name == "movl") &&
3425  (Operands.size() == 3)) {
3426  X86Operand &Op1 = (X86Operand &)*Operands[1];
3427  X86Operand &Op2 = (X86Operand &)*Operands[2];
3428  SMLoc Loc = Op1.getEndLoc();
3429  // Moving a 32 or 16 bit value into a segment register has the same
3430  // behavior. Modify such instructions to always take shorter form.
3431  if (Op1.isReg() && Op2.isReg() &&
3432  X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
3433  Op2.getReg()) &&
3434  (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
3435  X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
3436  // Change instruction name to match new instruction.
3437  if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
3438  Name = is16BitMode() ? "movw" : "movl";
3439  Operands[0] = X86Operand::CreateToken(Name, NameLoc);
3440  }
3441  // Select the correct equivalent 16-/32-bit source register.
3442  unsigned Reg =
3443  getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
3444  Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
3445  }
3446  }
3447 
3448  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
3449  // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
3450  // documented form in various unofficial manuals, so a lot of code uses it.
3451  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
3452  Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
3453  Operands.size() == 3) {
3454  X86Operand &Op = (X86Operand &)*Operands.back();
3455  if (Op.isDXReg())
3456  Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3457  Op.getEndLoc());
3458  }
3459  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
3460  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
3461  Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
3462  Operands.size() == 3) {
3463  X86Operand &Op = (X86Operand &)*Operands[1];
3464  if (Op.isDXReg())
3465  Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3466  Op.getEndLoc());
3467  }
3468 
3470  bool HadVerifyError = false;
3471 
3472  // Append default arguments to "ins[bwld]"
3473  if (Name.startswith("ins") &&
3474  (Operands.size() == 1 || Operands.size() == 3) &&
3475  (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
3476  Name == "ins")) {
3477 
3478  AddDefaultSrcDestOperands(TmpOperands,
3479  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
3480  DefaultMemDIOperand(NameLoc));
3481  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3482  }
3483 
3484  // Append default arguments to "outs[bwld]"
3485  if (Name.startswith("outs") &&
3486  (Operands.size() == 1 || Operands.size() == 3) &&
3487  (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
3488  Name == "outsd" || Name == "outs")) {
3489  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
3490  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
3491  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3492  }
3493 
3494  // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
3495  // values of $SIREG according to the mode. It would be nice if this
3496  // could be achieved with InstAlias in the tables.
3497  if (Name.startswith("lods") &&
3498  (Operands.size() == 1 || Operands.size() == 2) &&
3499  (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
3500  Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
3501  TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
3502  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3503  }
3504 
3505  // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
3506  // values of $DIREG according to the mode. It would be nice if this
3507  // could be achieved with InstAlias in the tables.
3508  if (Name.startswith("stos") &&
3509  (Operands.size() == 1 || Operands.size() == 2) &&
3510  (Name == "stos" || Name == "stosb" || Name == "stosw" ||
3511  Name == "stosl" || Name == "stosd" || Name == "stosq")) {
3512  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
3513  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3514  }
3515 
3516  // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
3517  // values of $DIREG according to the mode. It would be nice if this
3518  // could be achieved with InstAlias in the tables.
3519  if (Name.startswith("scas") &&
3520  (Operands.size() == 1 || Operands.size() == 2) &&
3521  (Name == "scas" || Name == "scasb" || Name == "scasw" ||
3522  Name == "scasl" || Name == "scasd" || Name == "scasq")) {
3523  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
3524  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3525  }
3526 
3527  // Add default SI and DI operands to "cmps[bwlq]".
3528  if (Name.startswith("cmps") &&
3529  (Operands.size() == 1 || Operands.size() == 3) &&
3530  (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
3531  Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
3532  AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
3533  DefaultMemSIOperand(NameLoc));
3534  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3535  }
3536 
3537  // Add default SI and DI operands to "movs[bwlq]".
3538  if (((Name.startswith("movs") &&
3539  (Name == "movs" || Name == "movsb" || Name == "movsw" ||
3540  Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
3541  (Name.startswith("smov") &&
3542  (Name == "smov" || Name == "smovb" || Name == "smovw" ||
3543  Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
3544  (Operands.size() == 1 || Operands.size() == 3)) {
3545  if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
3546  Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
3547  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
3548  DefaultMemDIOperand(NameLoc));
3549  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3550  }
3551 
3552  // Check if we encountered an error for one the string insturctions
3553  if (HadVerifyError) {
3554  return HadVerifyError;
3555  }
3556 
3557  // Transforms "xlat mem8" into "xlatb"
3558  if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
3559  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
3560  if (Op1.isMem8()) {
3561  Warning(Op1.getStartLoc(), "memory operand is only for determining the "
3562  "size, (R|E)BX will be used for the location");
3563  Operands.pop_back();
3564  static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
3565  }
3566  }
3567 
3568  if (Flags)
3569  Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
3570  return false;
3571 }
3572 
3573 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
3574  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3575 
3576  switch (Inst.getOpcode()) {
3577  default: return false;
3578  case X86::JMP_1:
3579  // {disp32} forces a larger displacement as if the instruction was relaxed.
3580  // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3581  // This matches GNU assembler.
3582  if (ForcedDispEncoding == DispEncoding_Disp32) {
3583  Inst.setOpcode(is16BitMode() ? X86::JMP_2 : X86::JMP_4);
3584  return true;
3585  }
3586 
3587  return false;
3588  case X86::JCC_1:
3589  // {disp32} forces a larger displacement as if the instruction was relaxed.
3590  // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3591  // This matches GNU assembler.
3592  if (ForcedDispEncoding == DispEncoding_Disp32) {
3593  Inst.setOpcode(is16BitMode() ? X86::JCC_2 : X86::JCC_4);
3594  return true;
3595  }
3596 
3597  return false;
3598  case X86::VMOVZPQILo2PQIrr:
3599  case X86::VMOVAPDrr:
3600  case X86::VMOVAPDYrr:
3601  case X86::VMOVAPSrr:
3602  case X86::VMOVAPSYrr:
3603  case X86::VMOVDQArr:
3604  case X86::VMOVDQAYrr:
3605  case X86::VMOVDQUrr:
3606  case X86::VMOVDQUYrr:
3607  case X86::VMOVUPDrr:
3608  case X86::VMOVUPDYrr:
3609  case X86::VMOVUPSrr:
3610  case X86::VMOVUPSYrr: {
3611  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3612  // the registers is extended, but other isn't.
3613  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
3614  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
3615  MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8)
3616  return false;
3617 
3618  unsigned NewOpc;
3619  switch (Inst.getOpcode()) {
3620  default: llvm_unreachable("Invalid opcode");
3621  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
3622  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
3623  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
3624  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
3625  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
3626  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
3627  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
3628  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
3629  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
3630  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
3631  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
3632  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
3633  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
3634  }
3635  Inst.setOpcode(NewOpc);
3636  return true;
3637  }
3638  case X86::VMOVSDrr:
3639  case X86::VMOVSSrr: {
3640  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3641  // the registers is extended, but other isn't.
3642  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
3643  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
3644  MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8)
3645  return false;
3646 
3647  unsigned NewOpc;
3648  switch (Inst.getOpcode()) {
3649  default: llvm_unreachable("Invalid opcode");
3650  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
3651  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
3652  }
3653  Inst.setOpcode(NewOpc);
3654  return true;
3655  }
3656  case X86::RCR8ri: case X86::RCR16ri: case X86::RCR32ri: case X86::RCR64ri:
3657  case X86::RCL8ri: case X86::RCL16ri: case X86::RCL32ri: case X86::RCL64ri:
3658  case X86::ROR8ri: case X86::ROR16ri: case X86::ROR32ri: case X86::ROR64ri:
3659  case X86::ROL8ri: case X86::ROL16ri: case X86::ROL32ri: case X86::ROL64ri:
3660  case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri: case X86::SAR64ri:
3661  case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri: case X86::SHR64ri:
3662  case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri: case X86::SHL64ri: {
3663  // Optimize s{hr,ar,hl} $1, <op> to "shift <op>". Similar for rotate.
3664  // FIXME: It would be great if we could just do this with an InstAlias.
3665  if (!Inst.getOperand(2).isImm() || Inst.getOperand(2).getImm() != 1)
3666  return false;
3667 
3668  unsigned NewOpc;
3669  switch (Inst.getOpcode()) {
3670  default: llvm_unreachable("Invalid opcode");
3671  case X86::RCR8ri: NewOpc = X86::RCR8r1; break;
3672  case X86::RCR16ri: NewOpc = X86::RCR16r1; break;
3673  case X86::RCR32ri: NewOpc = X86::RCR32r1; break;
3674  case X86::RCR64ri: NewOpc = X86::RCR64r1; break;
3675  case X86::RCL8ri: NewOpc = X86::RCL8r1; break;
3676  case X86::RCL16ri: NewOpc = X86::RCL16r1; break;
3677  case X86::RCL32ri: NewOpc = X86::RCL32r1; break;
3678  case X86::RCL64ri: NewOpc = X86::RCL64r1; break;
3679  case X86::ROR8ri: NewOpc = X86::ROR8r1; break;
3680  case X86::ROR16ri: NewOpc = X86::ROR16r1; break;
3681  case X86::ROR32ri: NewOpc = X86::ROR32r1; break;
3682  case X86::ROR64ri: NewOpc = X86::ROR64r1; break;
3683  case X86::ROL8ri: NewOpc = X86::ROL8r1; break;
3684  case X86::ROL16ri: NewOpc = X86::ROL16r1; break;
3685  case X86::ROL32ri: NewOpc = X86::ROL32r1; break;
3686  case X86::ROL64ri: NewOpc = X86::ROL64r1; break;
3687  case X86::SAR8ri: NewOpc = X86::SAR8r1; break;
3688  case X86::SAR16ri: NewOpc = X86::SAR16r1; break;
3689  case X86::SAR32ri: NewOpc = X86::SAR32r1; break;
3690  case X86::SAR64ri: NewOpc = X86::SAR64r1; break;
3691  case X86::SHR8ri: NewOpc = X86::SHR8r1; break;
3692  case X86::SHR16ri: NewOpc = X86::SHR16r1; break;
3693  case X86::SHR32ri: NewOpc = X86::SHR32r1; break;
3694  case X86::SHR64ri: NewOpc = X86::SHR64r1; break;
3695  case X86::SHL8ri: NewOpc = X86::SHL8r1; break;
3696  case X86::SHL16ri: NewOpc = X86::SHL16r1; break;
3697  case X86::SHL32ri: NewOpc = X86::SHL32r1; break;
3698  case X86::SHL64ri: NewOpc = X86::SHL64r1; break;
3699  }
3700 
3701  MCInst TmpInst;
3702  TmpInst.setOpcode(NewOpc);
3703  TmpInst.addOperand(Inst.getOperand(0));
3704  TmpInst.addOperand(Inst.getOperand(1));
3705  Inst = TmpInst;
3706  return true;
3707  }
3708  case X86::RCR8mi: case X86::RCR16mi: case X86::RCR32mi: case X86::RCR64mi:
3709  case X86::RCL8mi: case X86::RCL16mi: case X86::RCL32mi: case X86::RCL64mi:
3710  case X86::ROR8mi: case X86::ROR16mi: case X86::ROR32mi: case X86::ROR64mi:
3711  case X86::ROL8mi: case X86::ROL16mi: case X86::ROL32mi: case X86::ROL64mi:
3712  case X86::SAR8mi: case X86::SAR16mi: case X86::SAR32mi: case X86::SAR64mi:
3713  case X86::SHR8mi: case X86::SHR16mi: case X86::SHR32mi: case X86::SHR64mi:
3714  case X86::SHL8mi: case X86::SHL16mi: case X86::SHL32mi: case X86::SHL64mi: {
3715  // Optimize s{hr,ar,hl} $1, <op> to "shift <op>". Similar for rotate.
3716  // FIXME: It would be great if we could just do this with an InstAlias.
3717  if (!Inst.getOperand(X86::AddrNumOperands).isImm() ||
3718  Inst.getOperand(X86::AddrNumOperands).getImm() != 1)
3719  return false;
3720 
3721  unsigned NewOpc;
3722  switch (Inst.getOpcode()) {
3723  default: llvm_unreachable("Invalid opcode");
3724  case X86::RCR8mi: NewOpc = X86::RCR8m1; break;
3725  case X86::RCR16mi: NewOpc = X86::RCR16m1; break;
3726  case X86::RCR32mi: NewOpc = X86::RCR32m1; break;
3727  case X86::RCR64mi: NewOpc = X86::RCR64m1; break;
3728  case X86::RCL8mi: NewOpc = X86::RCL8m1; break;
3729  case X86::RCL16mi: NewOpc = X86::RCL16m1; break;
3730  case X86::RCL32mi: NewOpc = X86::RCL32m1; break;
3731  case X86::RCL64mi: NewOpc = X86::RCL64m1; break;
3732  case X86::ROR8mi: NewOpc = X86::ROR8m1; break;
3733  case X86::ROR16mi: NewOpc = X86::ROR16m1; break;
3734  case X86::ROR32mi: NewOpc = X86::ROR32m1; break;
3735  case X86::ROR64mi: NewOpc = X86::ROR64m1; break;
3736  case X86::ROL8mi: NewOpc = X86::ROL8m1; break;
3737  case X86::ROL16mi: NewOpc = X86::ROL16m1; break;
3738  case X86::ROL32mi: NewOpc = X86::ROL32m1; break;
3739  case X86::ROL64mi: NewOpc = X86::ROL64m1; break;
3740  case X86::SAR8mi: NewOpc = X86::SAR8m1; break;
3741  case X86::SAR16mi: NewOpc = X86::SAR16m1; break;
3742  case X86::SAR32mi: NewOpc = X86::SAR32m1; break;
3743  case X86::SAR64mi: NewOpc = X86::SAR64m1; break;
3744  case X86::SHR8mi: NewOpc = X86::SHR8m1; break;
3745  case X86::SHR16mi: NewOpc = X86::SHR16m1; break;
3746  case X86::SHR32mi: NewOpc = X86::SHR32m1; break;
3747  case X86::SHR64mi: NewOpc = X86::SHR64m1; break;
3748  case X86::SHL8mi: NewOpc = X86::SHL8m1; break;
3749  case X86::SHL16mi: NewOpc = X86::SHL16m1; break;
3750  case X86::SHL32mi: NewOpc = X86::SHL32m1; break;
3751  case X86::SHL64mi: NewOpc = X86::SHL64m1; break;
3752  }
3753 
3754  MCInst TmpInst;
3755  TmpInst.setOpcode(NewOpc);
3756  for (int i = 0; i != X86::AddrNumOperands; ++i)
3757  TmpInst.addOperand(Inst.getOperand(i));
3758  Inst = TmpInst;
3759  return true;
3760  }
3761  case X86::INT: {
3762  // Transforms "int $3" into "int3" as a size optimization. We can't write an
3763  // instalias with an immediate operand yet.
3764  if (!Inst.getOperand(0).isImm() || Inst.getOperand(0).getImm() != 3)
3765  return false;
3766 
3767  MCInst TmpInst;
3768  TmpInst.setOpcode(X86::INT3);
3769  Inst = TmpInst;
3770  return true;
3771  }
3772  }
3773 }
3774 
3775 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
3776  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3777 
3778  switch (Inst.getOpcode()) {
3779  case X86::VGATHERDPDYrm:
3780  case X86::VGATHERDPDrm:
3781  case X86::VGATHERDPSYrm:
3782  case X86::VGATHERDPSrm:
3783  case X86::VGATHERQPDYrm:
3784  case X86::VGATHERQPDrm:
3785  case X86::VGATHERQPSYrm:
3786  case X86::VGATHERQPSrm:
3787  case X86::VPGATHERDDYrm:
3788  case X86::VPGATHERDDrm:
3789  case X86::VPGATHERDQYrm:
3790  case X86::VPGATHERDQrm:
3791  case X86::VPGATHERQDYrm:
3792  case X86::VPGATHERQDrm:
3793  case X86::VPGATHERQQYrm:
3794  case X86::VPGATHERQQrm: {
3795  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
3796  unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
3797  unsigned Index =
3798  MRI->getEncodingValue(Inst.getOperand(3 + X86::AddrIndexReg).getReg());
3799  if (Dest == Mask || Dest == Index || Mask == Index)
3800  return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
3801  "registers should be distinct");
3802  break;
3803  }
3804  case X86::VGATHERDPDZ128rm:
3805  case X86::VGATHERDPDZ256rm:
3806  case X86::VGATHERDPDZrm:
3807  case X86::VGATHERDPSZ128rm:
3808  case X86::VGATHERDPSZ256rm:
3809  case X86::VGATHERDPSZrm:
3810  case X86::VGATHERQPDZ128rm:
3811  case X86::VGATHERQPDZ256rm:
3812  case X86::VGATHERQPDZrm:
3813  case X86::VGATHERQPSZ128rm:
3814  case X86::VGATHERQPSZ256rm:
3815  case X86::VGATHERQPSZrm:
3816  case X86::VPGATHERDDZ128rm:
3817  case X86::VPGATHERDDZ256rm:
3818  case X86::VPGATHERDDZrm:
3819  case X86::VPGATHERDQZ128rm:
3820  case X86::VPGATHERDQZ256rm:
3821  case X86::VPGATHERDQZrm:
3822  case X86::VPGATHERQDZ128rm:
3823  case X86::VPGATHERQDZ256rm:
3824  case X86::VPGATHERQDZrm:
3825  case X86::VPGATHERQQZ128rm:
3826  case X86::VPGATHERQQZ256rm:
3827  case X86::VPGATHERQQZrm: {
3828  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
3829  unsigned Index =
3830  MRI->getEncodingValue(Inst.getOperand(4 + X86::AddrIndexReg).getReg());
3831  if (Dest == Index)
3832  return Warning(Ops[0]->getStartLoc(), "index and destination registers "
3833  "should be distinct");
3834  break;
3835  }
3836  case X86::V4FMADDPSrm:
3837  case X86::V4FMADDPSrmk:
3838  case X86::V4FMADDPSrmkz:
3839  case X86::V4FMADDSSrm:
3840  case X86::V4FMADDSSrmk:
3841  case X86::V4FMADDSSrmkz:
3842  case X86::V4FNMADDPSrm:
3843  case X86::V4FNMADDPSrmk:
3844  case X86::V4FNMADDPSrmkz:
3845  case X86::V4FNMADDSSrm:
3846  case X86::V4FNMADDSSrmk:
3847  case X86::V4FNMADDSSrmkz:
3848  case X86::VP4DPWSSDSrm:
3849  case X86::VP4DPWSSDSrmk:
3850  case X86::VP4DPWSSDSrmkz:
3851  case X86::VP4DPWSSDrm:
3852  case X86::VP4DPWSSDrmk:
3853  case X86::VP4DPWSSDrmkz: {
3854  unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
3856  unsigned Src2Enc = MRI->getEncodingValue(Src2);
3857  if (Src2Enc % 4 != 0) {
3859  unsigned GroupStart = (Src2Enc / 4) * 4;
3860  unsigned GroupEnd = GroupStart + 3;
3861  return Warning(Ops[0]->getStartLoc(),
3862  "source register '" + RegName + "' implicitly denotes '" +
3863  RegName.take_front(3) + Twine(GroupStart) + "' to '" +
3864  RegName.take_front(3) + Twine(GroupEnd) +
3865  "' source group");
3866  }
3867  break;
3868  }
3869  case X86::VFCMADDCPHZ128m:
3870  case X86::VFCMADDCPHZ256m:
3871  case X86::VFCMADDCPHZm:
3872  case X86::VFCMADDCPHZ128mb:
3873  case X86::VFCMADDCPHZ256mb:
3874  case X86::VFCMADDCPHZmb:
3875  case X86::VFCMADDCPHZ128mbk:
3876  case X86::VFCMADDCPHZ256mbk:
3877  case X86::VFCMADDCPHZmbk:
3878  case X86::VFCMADDCPHZ128mbkz:
3879  case X86::VFCMADDCPHZ256mbkz:
3880  case X86::VFCMADDCPHZmbkz:
3881  case X86::VFCMADDCPHZ128mk:
3882  case X86::VFCMADDCPHZ256mk:
3883  case X86::VFCMADDCPHZmk:
3884  case X86::VFCMADDCPHZ128mkz:
3885  case X86::VFCMADDCPHZ256mkz:
3886  case X86::VFCMADDCPHZmkz:
3887  case X86::VFCMADDCPHZ128r:
3888  case X86::VFCMADDCPHZ256r:
3889  case X86::VFCMADDCPHZr:
3890  case X86::VFCMADDCPHZ128rk:
3891  case X86::VFCMADDCPHZ256rk:
3892  case X86::VFCMADDCPHZrk:
3893  case X86::VFCMADDCPHZ128rkz:
3894  case X86::VFCMADDCPHZ256rkz:
3895  case X86::VFCMADDCPHZrkz:
3896  case X86::VFCMADDCPHZrb:
3897  case X86::VFCMADDCPHZrbk:
3898  case X86::VFCMADDCPHZrbkz:
3899  case X86::VFCMADDCSHZm:
3900  case X86::VFCMADDCSHZmk:
3901  case X86::VFCMADDCSHZmkz:
3902  case X86::VFCMADDCSHZr:
3903  case X86::VFCMADDCSHZrb:
3904  case X86::VFCMADDCSHZrbk:
3905  case X86::VFCMADDCSHZrbkz:
3906  case X86::VFCMADDCSHZrk:
3907  case X86::VFCMADDCSHZrkz:
3908  case X86::VFMADDCPHZ128m:
3909  case X86::VFMADDCPHZ256m:
3910  case X86::VFMADDCPHZm:
3911  case X86::VFMADDCPHZ128mb:
3912  case X86::VFMADDCPHZ256mb:
3913  case X86::VFMADDCPHZmb:
3914  case X86::VFMADDCPHZ128mbk:
3915  case X86::VFMADDCPHZ256mbk:
3916  case X86::VFMADDCPHZmbk:
3917  case X86::VFMADDCPHZ128mbkz:
3918  case X86::VFMADDCPHZ256mbkz:
3919  case X86::VFMADDCPHZmbkz:
3920  case X86::VFMADDCPHZ128mk:
3921  case X86::VFMADDCPHZ256mk:
3922  case X86::VFMADDCPHZmk:
3923  case X86::VFMADDCPHZ128mkz:
3924  case X86::VFMADDCPHZ256mkz:
3925  case X86::VFMADDCPHZmkz:
3926  case X86::VFMADDCPHZ128r:
3927  case X86::VFMADDCPHZ256r:
3928  case X86::VFMADDCPHZr:
3929  case X86::VFMADDCPHZ128rk:
3930  case X86::VFMADDCPHZ256rk:
3931  case X86::VFMADDCPHZrk:
3932  case X86::VFMADDCPHZ128rkz:
3933  case X86::VFMADDCPHZ256rkz:
3934  case X86::VFMADDCPHZrkz:
3935  case X86::VFMADDCPHZrb:
3936  case X86::VFMADDCPHZrbk:
3937  case X86::VFMADDCPHZrbkz:
3938  case X86::VFMADDCSHZm:
3939  case X86::VFMADDCSHZmk:
3940  case X86::VFMADDCSHZmkz:
3941  case X86::VFMADDCSHZr:
3942  case X86::VFMADDCSHZrb:
3943  case X86::VFMADDCSHZrbk:
3944  case X86::VFMADDCSHZrbkz:
3945  case X86::VFMADDCSHZrk:
3946  case X86::VFMADDCSHZrkz: {
3947  unsigned Dest = Inst.getOperand(0).getReg();
3948  for (unsigned i = 2; i < Inst.getNumOperands(); i++)
3949  if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
3950  return Warning(Ops[0]->getStartLoc(), "Destination register should be "
3951  "distinct from source registers");
3952  break;
3953  }
3954  case X86::VFCMULCPHZ128rm:
3955  case X86::VFCMULCPHZ256rm:
3956  case X86::VFCMULCPHZrm:
3957  case X86::VFCMULCPHZ128rmb:
3958  case X86::VFCMULCPHZ256rmb:
3959  case X86::VFCMULCPHZrmb:
3960  case X86::VFCMULCPHZ128rmbk:
3961  case X86::VFCMULCPHZ256rmbk:
3962  case X86::VFCMULCPHZrmbk:
3963  case X86::VFCMULCPHZ128rmbkz:
3964  case X86::VFCMULCPHZ256rmbkz:
3965  case X86::VFCMULCPHZrmbkz:
3966  case X86::VFCMULCPHZ128rmk:
3967  case X86::VFCMULCPHZ256rmk:
3968  case X86::VFCMULCPHZrmk:
3969  case X86::VFCMULCPHZ128rmkz:
3970  case X86::VFCMULCPHZ256rmkz:
3971  case X86::VFCMULCPHZrmkz:
3972  case X86::VFCMULCPHZ128rr:
3973  case X86::VFCMULCPHZ256rr:
3974  case X86::VFCMULCPHZrr:
3975  case X86::VFCMULCPHZ128rrk:
3976  case X86::VFCMULCPHZ256rrk:
3977  case X86::VFCMULCPHZrrk:
3978  case X86::VFCMULCPHZ128rrkz:
3979  case X86::VFCMULCPHZ256rrkz:
3980  case X86::VFCMULCPHZrrkz:
3981  case X86::VFCMULCPHZrrb:
3982  case X86::VFCMULCPHZrrbk:
3983  case X86::VFCMULCPHZrrbkz:
3984  case X86::VFCMULCSHZrm:
3985  case X86::VFCMULCSHZrmk:
3986  case X86::VFCMULCSHZrmkz:
3987  case X86::VFCMULCSHZrr:
3988  case X86::VFCMULCSHZrrb:
3989  case X86::VFCMULCSHZrrbk:
3990  case X86::VFCMULCSHZrrbkz:
3991  case X86::VFCMULCSHZrrk:
3992  case X86::VFCMULCSHZrrkz:
3993  case X86::VFMULCPHZ128rm:
3994  case X86::VFMULCPHZ256rm:
3995  case X86::VFMULCPHZrm:
3996  case X86::VFMULCPHZ128rmb:
3997  case X86::VFMULCPHZ256rmb:
3998  case X86::VFMULCPHZrmb:
3999  case X86::VFMULCPHZ128rmbk:
4000  case X86::VFMULCPHZ256rmbk:
4001  case X86::VFMULCPHZrmbk:
4002  case X86::VFMULCPHZ128rmbkz:
4003  case X86::VFMULCPHZ256rmbkz:
4004  case X86::VFMULCPHZrmbkz:
4005  case X86::VFMULCPHZ128rmk:
4006  case X86::VFMULCPHZ256rmk:
4007  case X86::VFMULCPHZrmk:
4008  case X86::VFMULCPHZ128rmkz:
4009  case X86::VFMULCPHZ256rmkz:
4010  case X86::VFMULCPHZrmkz:
4011  case X86::VFMULCPHZ128rr:
4012  case X86::VFMULCPHZ256rr:
4013  case X86::VFMULCPHZrr:
4014  case X86::VFMULCPHZ128rrk:
4015  case X86::VFMULCPHZ256rrk:
4016  case X86::VFMULCPHZrrk:
4017  case X86::VFMULCPHZ128rrkz:
4018  case X86::VFMULCPHZ256rrkz:
4019  case X86::VFMULCPHZrrkz:
4020  case X86::VFMULCPHZrrb:
4021  case X86::VFMULCPHZrrbk:
4022  case X86::VFMULCPHZrrbkz:
4023  case X86::VFMULCSHZrm:
4024  case X86::VFMULCSHZrmk:
4025  case X86::VFMULCSHZrmkz:
4026  case X86::VFMULCSHZrr:
4027  case X86::VFMULCSHZrrb:
4028  case X86::VFMULCSHZrrbk:
4029  case X86::VFMULCSHZrrbkz:
4030  case X86::VFMULCSHZrrk:
4031  case X86::VFMULCSHZrrkz: {
4032  unsigned Dest = Inst.getOperand(0).getReg();
4033  for (unsigned i = 1; i < Inst.getNumOperands(); i++)
4034  if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
4035  return Warning(Ops[0]->getStartLoc(), "Destination register should be "
4036  "distinct from source registers");
4037  break;
4038  }
4039  }
4040 
4041  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
4042  // Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to
4043  // check this with the legacy encoding, VEX/EVEX/XOP don't use REX.
4044  if ((MCID.TSFlags & X86II::EncodingMask) == 0) {
4045  MCPhysReg HReg = X86::NoRegister;
4046  bool UsesRex = MCID.TSFlags & X86II::REX_W;
4047  unsigned NumOps = Inst.getNumOperands();
4048  for (unsigned i = 0; i != NumOps; ++i) {
4049  const MCOperand &MO = Inst.getOperand(i);
4050  if (!MO.isReg())
4051  continue;
4052  unsigned Reg = MO.getReg();
4053  if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
4054  HReg = Reg;
4057  UsesRex = true;
4058  }
4059 
4060  if (UsesRex && HReg != X86::NoRegister) {
4062  return Error(Ops[0]->getStartLoc(),
4063  "can't encode '" + RegName + "' in an instruction requiring "
4064  "REX prefix");
4065  }
4066  }
4067 
4068  return false;
4069 }
4070 
4071 static const char *getSubtargetFeatureName(uint64_t Val);
4072 
4073 void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) {
4074  Warning(Loc, "Instruction may be vulnerable to LVI and "
4075  "requires manual mitigation");
4076  Note(SMLoc(), "See https://software.intel.com/"
4077  "security-software-guidance/insights/"
4078  "deep-dive-load-value-injection#specialinstructions"
4079  " for more information");
4080 }
4081 
4082 /// RET instructions and also instructions that indirect calls/jumps from memory
4083 /// combine a load and a branch within a single instruction. To mitigate these
4084 /// instructions against LVI, they must be decomposed into separate load and
4085 /// branch instructions, with an LFENCE in between. For more details, see:
4086 /// - X86LoadValueInjectionRetHardening.cpp
4087 /// - X86LoadValueInjectionIndirectThunks.cpp
4088 /// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4089 ///
4090 /// Returns `true` if a mitigation was applied or warning was emitted.
4091 void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
4092  // Information on control-flow instructions that require manual mitigation can
4093  // be found here:
4094  // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4095  switch (Inst.getOpcode()) {
4096  case X86::RETW:
4097  case X86::RETL:
4098  case X86::RETQ:
4099  case X86::RETIL:
4100  case X86::RETIQ:
4101  case X86::RETIW: {
4102  MCInst ShlInst, FenceInst;
4103  bool Parse32 = is32BitMode() || Code16GCC;
4104  unsigned Basereg =
4105  is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP);
4106  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
4107  auto ShlMemOp = X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
4108  /*BaseReg=*/Basereg, /*IndexReg=*/0,
4109  /*Scale=*/1, SMLoc{}, SMLoc{}, 0);
4110  ShlInst.setOpcode(X86::SHL64mi);
4111  ShlMemOp->addMemOperands(ShlInst, 5);
4112  ShlInst.addOperand(MCOperand::createImm(0));
4113  FenceInst.setOpcode(X86::LFENCE);
4114  Out.emitInstruction(ShlInst, getSTI());
4115  Out.emitInstruction(FenceInst, getSTI());
4116  return;
4117  }
4118  case X86::JMP16m:
4119  case X86::JMP32m:
4120  case X86::JMP64m:
4121  case X86::CALL16m:
4122  case X86::CALL32m:
4123  case X86::CALL64m:
4124  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4125  return;
4126  }
4127 }
4128 
4129 /// To mitigate LVI, every instruction that performs a load can be followed by
4130 /// an LFENCE instruction to squash any potential mis-speculation. There are
4131 /// some instructions that require additional considerations, and may requre
4132 /// manual mitigation. For more details, see:
4133 /// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4134 ///
4135 /// Returns `true` if a mitigation was applied or warning was emitted.
4136 void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
4137  MCStreamer &Out) {
4138  auto Opcode = Inst.getOpcode();
4139  auto Flags = Inst.getFlags();
4140  if ((Flags & X86::IP_HAS_REPEAT) || (Flags & X86::IP_HAS_REPEAT_NE)) {
4141  // Information on REP string instructions that require manual mitigation can
4142  // be found here:
4143  // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4144  switch (Opcode) {
4145  case X86::CMPSB:
4146  case X86::CMPSW:
4147  case X86::CMPSL:
4148  case X86::CMPSQ:
4149  case X86::SCASB:
4150  case X86::SCASW:
4151  case X86::SCASL:
4152  case X86::SCASQ:
4153  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4154  return;
4155  }
4156  } else if (Opcode == X86::REP_PREFIX || Opcode == X86::REPNE_PREFIX) {
4157  // If a REP instruction is found on its own line, it may or may not be
4158  // followed by a vulnerable instruction. Emit a warning just in case.
4159  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4160  return;
4161  }
4162 
4163  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
4164 
4165  // Can't mitigate after terminators or calls. A control flow change may have
4166  // already occurred.
4167  if (MCID.isTerminator() || MCID.isCall())
4168  return;
4169 
4170  // LFENCE has the mayLoad property, don't double fence.
4171  if (MCID.mayLoad() && Inst.getOpcode() != X86::LFENCE) {
4172  MCInst FenceInst;
4173  FenceInst.setOpcode(X86::LFENCE);
4174  Out.emitInstruction(FenceInst, getSTI());
4175  }
4176 }
4177 
4178 void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
4179  MCStreamer &Out) {
4180  if (LVIInlineAsmHardening &&
4181  getSTI().getFeatureBits()[X86::FeatureLVIControlFlowIntegrity])
4182  applyLVICFIMitigation(Inst, Out);
4183 
4184  Out.emitInstruction(Inst, getSTI());
4185 
4186  if (LVIInlineAsmHardening &&
4187  getSTI().getFeatureBits()[X86::FeatureLVILoadHardening])
4188  applyLVILoadHardeningMitigation(Inst, Out);
4189 }
4190 
4191 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4193  MCStreamer &Out, uint64_t &ErrorInfo,
4194  bool MatchingInlineAsm) {
4195  if (isParsingIntelSyntax())
4196  return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
4197  MatchingInlineAsm);
4198  return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
4199  MatchingInlineAsm);
4200 }
4201 
4202 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
4204  bool MatchingInlineAsm) {
4205  // FIXME: This should be replaced with a real .td file alias mechanism.
4206  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
4207  // call.
4208  const char *Repl = StringSwitch<const char *>(Op.getToken())
4209  .Case("finit", "fninit")
4210  .Case("fsave", "fnsave")
4211  .Case("fstcw", "fnstcw")
4212  .Case("fstcww", "fnstcw")
4213  .Case("fstenv", "fnstenv")
4214  .Case("fstsw", "fnstsw")
4215  .Case("fstsww", "fnstsw")
4216  .Case("fclex", "fnclex")
4217  .Default(nullptr);
4218  if (Repl) {
4219  MCInst Inst;
4220  Inst.setOpcode(X86::WAIT);
4221  Inst.setLoc(IDLoc);
4222  if (!MatchingInlineAsm)
4223  emitInstruction(Inst, Operands, Out);
4224  Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
4225  }
4226 }
4227 
4228 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
4229  const FeatureBitset &MissingFeatures,
4230  bool MatchingInlineAsm) {
4231  assert(MissingFeatures.any() && "Unknown missing feature!");
4232  SmallString<126> Msg;
4233  raw_svector_ostream OS(Msg);
4234  OS << "instruction requires:";
4235  for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
4236  if (MissingFeatures[i])
4237  OS << ' ' << getSubtargetFeatureName(i);
4238  }
4239  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
4240 }
4241 
4243  unsigned Result = 0;
4244  X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
4245  if (Prefix.isPrefix()) {
4246  Result = Prefix.getPrefix();
4247  Operands.pop_back();
4248  }
4249  return Result;
4250 }
4251 
4252 unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4253  unsigned Opc = Inst.getOpcode();
4254  const MCInstrDesc &MCID = MII.get(Opc);
4255 
4256  if (ForcedVEXEncoding == VEXEncoding_EVEX &&
4258  return Match_Unsupported;
4259 
4260  if ((ForcedVEXEncoding == VEXEncoding_VEX ||
4261  ForcedVEXEncoding == VEXEncoding_VEX2 ||
4262  ForcedVEXEncoding == VEXEncoding_VEX3) &&
4264  return Match_Unsupported;
4265 
4266  // These instructions are only available with {vex}, {vex2} or {vex3} prefix
4267  if (MCID.TSFlags & X86II::ExplicitVEXPrefix &&
4268  (ForcedVEXEncoding != VEXEncoding_VEX &&
4269  ForcedVEXEncoding != VEXEncoding_VEX2 &&
4270  ForcedVEXEncoding != VEXEncoding_VEX3))
4271  return Match_Unsupported;
4272 
4273  // These instructions match ambiguously with their VEX encoded counterparts
4274  // and appear first in the matching table. Reject them unless we're forcing
4275  // EVEX encoding.
4276  // FIXME: We really need a way to break the ambiguity.
4277  switch (Opc) {
4278  case X86::VCVTSD2SIZrm_Int:
4279  case X86::VCVTSD2SI64Zrm_Int:
4280  case X86::VCVTSS2SIZrm_Int:
4281  case X86::VCVTSS2SI64Zrm_Int:
4282  case X86::VCVTTSD2SIZrm: case X86::VCVTTSD2SIZrm_Int:
4283  case X86::VCVTTSD2SI64Zrm: case X86::VCVTTSD2SI64Zrm_Int:
4284  case X86::VCVTTSS2SIZrm: case X86::VCVTTSS2SIZrm_Int:
4285  case X86::VCVTTSS2SI64Zrm: case X86::VCVTTSS2SI64Zrm_Int:
4286  if (ForcedVEXEncoding != VEXEncoding_EVEX)
4287  return Match_Unsupported;
4288  break;
4289  }
4290 
4291  return Match_Success;
4292 }
4293 
4294 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
4296  MCStreamer &Out,
4298  bool MatchingInlineAsm) {
4299  assert(!Operands.empty() && "Unexpect empty operand list!");
4300  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4301  SMRange EmptyRange = None;
4302 
4303  // First, handle aliases that expand to multiple instructions.
4304  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands,
4305  Out, MatchingInlineAsm);
4306  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4307  unsigned Prefixes = getPrefixes(Operands);
4308 
4309  MCInst Inst;
4310 
4311  // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
4312  // encoder and printer.
4313  if (ForcedVEXEncoding == VEXEncoding_VEX)
4314  Prefixes |= X86::IP_USE_VEX;
4315  else if (ForcedVEXEncoding == VEXEncoding_VEX2)
4316  Prefixes |= X86::IP_USE_VEX2;
4317  else if (ForcedVEXEncoding == VEXEncoding_VEX3)
4318  Prefixes |= X86::IP_USE_VEX3;
4319  else if (ForcedVEXEncoding == VEXEncoding_EVEX)
4320  Prefixes |= X86::IP_USE_EVEX;
4321 
4322  // Set encoded flags for {disp8} and {disp32}.
4323  if (ForcedDispEncoding == DispEncoding_Disp8)
4324  Prefixes |= X86::IP_USE_DISP8;
4325  else if (ForcedDispEncoding == DispEncoding_Disp32)
4326  Prefixes |= X86::IP_USE_DISP32;
4327 
4328  if (Prefixes)
4329  Inst.setFlags(Prefixes);
4330 
4331  // In 16-bit mode, if data32 is specified, temporarily switch to 32-bit mode
4332  // when matching the instruction.
4333  if (ForcedDataPrefix == X86::Mode32Bit)
4334  SwitchMode(X86::Mode32Bit);
4335  // First, try a direct match.
4336  FeatureBitset MissingFeatures;
4337  unsigned OriginalError = MatchInstruction(Operands, Inst, ErrorInfo,
4338  MissingFeatures, MatchingInlineAsm,
4339  isParsingIntelSyntax());
4340  if (ForcedDataPrefix == X86::Mode32Bit) {
4341  SwitchMode(X86::Mode16Bit);
4342  ForcedDataPrefix = 0;
4343  }
4344  switch (OriginalError) {
4345  default: llvm_unreachable("Unexpected match result!");
4346  case Match_Success:
4347  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4348  return true;
4349  // Some instructions need post-processing to, for example, tweak which
4350  // encoding is selected. Loop on it while changes happen so the
4351  // individual transformations can chain off each other.
4352  if (!MatchingInlineAsm)
4353  while (processInstruction(Inst, Operands))
4354  ;
4355 
4356  Inst.setLoc(IDLoc);
4357  if (!MatchingInlineAsm)
4358  emitInstruction(Inst, Operands, Out);
4359  Opcode = Inst.getOpcode();
4360  return false;
4361  case Match_InvalidImmUnsignedi4: {
4362  SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4363  if (ErrorLoc == SMLoc())
4364  ErrorLoc = IDLoc;
4365  return Error(ErrorLoc, "immediate must be an integer in range [0, 15]",
4366  EmptyRange, MatchingInlineAsm);
4367  }
4368  case Match_MissingFeature:
4369  return ErrorMissingFeature(IDLoc, MissingFeatures, MatchingInlineAsm);
4370  case Match_InvalidOperand:
4371  case Match_MnemonicFail:
4372  case Match_Unsupported:
4373  break;
4374  }
4375  if (Op.getToken().empty()) {
4376  Error(IDLoc, "instruction must have size higher than 0", EmptyRange,
4377  MatchingInlineAsm);
4378  return true;
4379  }
4380 
4381  // FIXME: Ideally, we would only attempt suffix matches for things which are
4382  // valid prefixes, and we could just infer the right unambiguous
4383  // type. However, that requires substantially more matcher support than the
4384  // following hack.
4385 
4386  // Change the operand to point to a temporary token.
4387  StringRef Base = Op.getToken();
4388  SmallString<16> Tmp;
4389  Tmp += Base;
4390  Tmp += ' ';
4391  Op.setTokenValue(Tmp);
4392 
4393  // If this instruction starts with an 'f', then it is a floating point stack
4394  // instruction. These come in up to three forms for 32-bit, 64-bit, and
4395  // 80-bit floating point, which use the suffixes s,l,t respectively.
4396  //
4397  // Otherwise, we assume that this may be an integer instruction, which comes
4398  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
4399  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
4400  // MemSize corresponding to Suffixes. { 8, 16, 32, 64 } { 32, 64, 80, 0 }
4401  const char *MemSize = Base[0] != 'f' ? "\x08\x10\x20\x40" : "\x20\x40\x50\0";
4402 
4403  // Check for the various suffix matches.
4404  uint64_t ErrorInfoIgnore;
4405  FeatureBitset ErrorInfoMissingFeatures; // Init suppresses compiler warnings.
4406  unsigned Match[4];
4407 
4408  // Some instruction like VPMULDQ is NOT the variant of VPMULD but a new one.
4409  // So we should make sure the suffix matcher only works for memory variant
4410  // that has the same size with the suffix.
4411  // FIXME: This flag is a workaround for legacy instructions that didn't
4412  // declare non suffix variant assembly.
4413  bool HasVectorReg = false;
4414  X86Operand *MemOp = nullptr;
4415  for (const auto &Op : Operands) {
4416  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4417  if (X86Op->isVectorReg())
4418  HasVectorReg = true;
4419  else if (X86Op->isMem()) {
4420  MemOp = X86Op;
4421  assert(MemOp->Mem.Size == 0 && "Memory size always 0 under ATT syntax");
4422  // Have we found an unqualified memory operand,
4423  // break. IA allows only one memory operand.
4424  break;
4425  }
4426  }
4427 
4428  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
4429  Tmp.back() = Suffixes[I];
4430  if (MemOp && HasVectorReg)
4431  MemOp->Mem.Size = MemSize[I];
4432  Match[I] = Match_MnemonicFail;
4433  if (MemOp || !HasVectorReg) {
4434  Match[I] =
4435  MatchInstruction(Operands, Inst, ErrorInfoIgnore, MissingFeatures,
4436  MatchingInlineAsm, isParsingIntelSyntax());
4437  // If this returned as a missing feature failure, remember that.
4438  if (Match[I] == Match_MissingFeature)
4439  ErrorInfoMissingFeatures = MissingFeatures;
4440  }
4441  }
4442 
4443  // Restore the old token.
4444  Op.setTokenValue(Base);
4445 
4446  // If exactly one matched, then we treat that as a successful match (and the
4447  // instruction will already have been filled in correctly, since the failing
4448  // matches won't have modified it).
4449  unsigned NumSuccessfulMatches =
4450  std::count(std::begin(Match), std::end(Match), Match_Success);
4451  if (NumSuccessfulMatches == 1) {
4452  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4453  return true;
4454  // Some instructions need post-processing to, for example, tweak which
4455  // encoding is selected. Loop on it while changes happen so the
4456  // individual transformations can chain off each other.
4457  if (!MatchingInlineAsm)
4458  while (processInstruction(Inst, Operands))
4459  ;
4460 
4461  Inst.setLoc(IDLoc);
4462  if (!MatchingInlineAsm)
4463  emitInstruction(Inst, Operands, Out);
4464  Opcode = Inst.getOpcode();
4465  return false;
4466  }
4467 
4468  // Otherwise, the match failed, try to produce a decent error message.
4469 
4470  // If we had multiple suffix matches, then identify this as an ambiguous
4471  // match.
4472  if (NumSuccessfulMatches > 1) {
4473  char MatchChars[4];
4474  unsigned NumMatches = 0;
4475  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
4476  if (Match[I] == Match_Success)
4477  MatchChars[NumMatches++] = Suffixes[I];
4478 
4479  SmallString<126> Msg;
4480  raw_svector_ostream OS(Msg);
4481  OS << "ambiguous instructions require an explicit suffix (could be ";
4482  for (unsigned i = 0; i != NumMatches; ++i) {
4483  if (i != 0)
4484  OS << ", ";
4485  if (i + 1 == NumMatches)
4486  OS << "or ";
4487  OS << "'" << Base << MatchChars[i] << "'";
4488  }
4489  OS << ")";
4490  Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
4491  return true;
4492  }
4493 
4494  // Okay, we know that none of the variants matched successfully.
4495 
4496  // If all of the instructions reported an invalid mnemonic, then the original
4497  // mnemonic was invalid.
4498  if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
4499  if (OriginalError == Match_MnemonicFail)
4500  return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
4501  Op.getLocRange(), MatchingInlineAsm);
4502 
4503  if (OriginalError == Match_Unsupported)
4504  return Error(IDLoc, "unsupported instruction", EmptyRange,
4505  MatchingInlineAsm);
4506 
4507  assert(OriginalError == Match_InvalidOperand && "Unexpected error");
4508  // Recover location info for the operand if we know which was the problem.
4509  if (ErrorInfo != ~0ULL) {
4510  if (ErrorInfo >= Operands.size())
4511  return Error(IDLoc, "too few operands for instruction", EmptyRange,
4512  MatchingInlineAsm);
4513 
4514  X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
4515  if (Operand.getStartLoc().isValid()) {
4516  SMRange OperandRange = Operand.getLocRange();
4517  return Error(Operand.getStartLoc(), "invalid operand for instruction",
4518  OperandRange, MatchingInlineAsm);
4519  }
4520  }
4521 
4522  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4523  MatchingInlineAsm);
4524  }
4525 
4526  // If one instruction matched as unsupported, report this as unsupported.
4527  if (std::count(std::begin(Match), std::end(Match),
4528  Match_Unsupported) == 1) {
4529  return Error(IDLoc, "unsupported instruction", EmptyRange,
4530  MatchingInlineAsm);
4531  }
4532 
4533  // If one instruction matched with a missing feature, report this as a
4534  // missing feature.
4535  if (std::count(std::begin(Match), std::end(Match),
4536  Match_MissingFeature) == 1) {
4537  ErrorInfo = Match_MissingFeature;
4538  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
4539  MatchingInlineAsm);
4540  }
4541 
4542  // If one instruction matched with an invalid operand, report this as an
4543  // operand failure.
4544  if (std::count(std::begin(Match), std::end(Match),
4545  Match_InvalidOperand) == 1) {
4546  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4547  MatchingInlineAsm);
4548  }
4549 
4550  // If all of these were an outright failure, report it in a useless way.
4551  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
4552  EmptyRange, MatchingInlineAsm);
4553  return true;
4554 }
4555 
4556 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
4558  MCStreamer &Out,
4560  bool MatchingInlineAsm) {
4561  assert(!Operands.empty() && "Unexpect empty operand list!");
4562  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4563  StringRef Mnemonic = (static_cast<X86Operand &>(*Operands[0])).getToken();
4564  SMRange EmptyRange = None;
4565  StringRef Base = (static_cast<X86Operand &>(*Operands[0])).getToken();
4566  unsigned Prefixes = getPrefixes(Operands);
4567 
4568  // First, handle aliases that expand to multiple instructions.
4569  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands, Out, MatchingInlineAsm);
4570  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4571 
4572  MCInst Inst;
4573 
4574  // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
4575  // encoder and printer.
4576  if (ForcedVEXEncoding == VEXEncoding_VEX)
4577  Prefixes |= X86::IP_USE_VEX;
4578  else if (ForcedVEXEncoding == VEXEncoding_VEX2)
4579  Prefixes |= X86::IP_USE_VEX2;
4580  else if (ForcedVEXEncoding == VEXEncoding_VEX3)
4581  Prefixes |= X86::IP_USE_VEX3;
4582  else if (ForcedVEXEncoding == VEXEncoding_EVEX)
4583  Prefixes |= X86::IP_USE_EVEX;
4584 
4585  // Set encoded flags for {disp8} and {disp32}.
4586  if (ForcedDispEncoding == DispEncoding_Disp8)
4587  Prefixes |= X86::IP_USE_DISP8;
4588  else if (ForcedDispEncoding == DispEncoding_Disp32)
4589  Prefixes |= X86::IP_USE_DISP32;
4590 
4591  if (Prefixes)
4592  Inst.setFlags(Prefixes);
4593 
4594  // Find one unsized memory operand, if present.
4595  X86Operand *UnsizedMemOp = nullptr;
4596  for (const auto &Op : Operands) {
4597  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4598  if (X86Op->isMemUnsized()) {
4599  UnsizedMemOp = X86Op;
4600  // Have we found an unqualified memory operand,
4601  // break. IA allows only one memory operand.
4602  break;
4603  }
4604  }
4605 
4606  // Allow some instructions to have implicitly pointer-sized operands. This is
4607  // compatible with gas.
4608  if (UnsizedMemOp) {
4609  static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
4610  for (const char *Instr : PtrSizedInstrs) {
4611  if (Mnemonic == Instr) {
4612  UnsizedMemOp->Mem.Size = getPointerWidth();
4613  break;
4614  }
4615  }
4616  }
4617 
4619  FeatureBitset ErrorInfoMissingFeatures;
4620  FeatureBitset MissingFeatures;
4621 
4622  // If unsized push has immediate operand we should default the default pointer
4623  // size for the size.
4624  if (Mnemonic == "push" && Operands.size() == 2) {
4625  auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
4626  if (X86Op->isImm()) {
4627  // If it's not a constant fall through and let remainder take care of it.
4628  const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
4629  unsigned Size = getPointerWidth();
4630  if (CE &&
4631  (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
4632  SmallString<16> Tmp;
4633  Tmp += Base;
4634  Tmp += (is64BitMode())
4635  ? "q"
4636  : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
4637  Op.setTokenValue(Tmp);
4638  // Do match in ATT mode to allow explicit suffix usage.
4639  Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
4640  MissingFeatures, MatchingInlineAsm,
4641  false /*isParsingIntelSyntax()*/));
4642  Op.setTokenValue(Base);
4643  }
4644  }
4645  }
4646 
4647  // If an unsized memory operand is present, try to match with each memory
4648  // operand size. In Intel assembly, the size is not part of the instruction
4649  // mnemonic.
4650  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
4651  static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
4652  for (unsigned Size : MopSizes) {
4653  UnsizedMemOp->Mem.Size = Size;
4654  uint64_t ErrorInfoIgnore;
4655  unsigned LastOpcode = Inst.getOpcode();
4656  unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
4657  MissingFeatures, MatchingInlineAsm,
4658  isParsingIntelSyntax());
4659  if (Match.empty() || LastOpcode != Inst.getOpcode())
4660  Match.push_back(M);
4661 
4662  // If this returned as a missing feature failure, remember that.
4663  if (Match.back() == Match_MissingFeature)
4664  ErrorInfoMissingFeatures = MissingFeatures;
4665  }
4666 
4667  // Restore the size of the unsized memory operand if we modified it.
4668  UnsizedMemOp->Mem.Size = 0;
4669  }
4670 
4671  // If we haven't matched anything yet, this is not a basic integer or FPU
4672  // operation. There shouldn't be any ambiguity in our mnemonic table, so try
4673  // matching with the unsized operand.
4674  if (Match.empty()) {
4675  Match.push_back(MatchInstruction(
4676  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
4677  isParsingIntelSyntax()));
4678  // If this returned as a missing feature failure, remember that.
4679  if (Match.back() == Match_MissingFeature)
4680  ErrorInfoMissingFeatures = MissingFeatures;
4681  }
4682 
4683  // Restore the size of the unsized memory operand if we modified it.
4684  if (UnsizedMemOp)
4685  UnsizedMemOp->Mem.Size = 0;
4686 
4687  // If it's a bad mnemonic, all results will be the same.
4688  if (Match.back() == Match_MnemonicFail) {
4689  return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
4690  Op.getLocRange(), MatchingInlineAsm);
4691  }
4692 
4693  unsigned NumSuccessfulMatches =
4694  std::count(std::begin(Match), std::end(Match), Match_Success);
4695 
4696  // If matching was ambiguous and we had size information from the frontend,
4697  // try again with that. This handles cases like "movxz eax, m8/m16".
4698  if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
4699  UnsizedMemOp->getMemFrontendSize()) {
4700  UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
4701  unsigned M = MatchInstruction(
4702  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
4703  isParsingIntelSyntax());
4704  if (M == Match_Success)
4705  NumSuccessfulMatches = 1;
4706 
4707  // Add a rewrite that encodes the size information we used from the
4708  // frontend.
4709  InstInfo->AsmRewrites->emplace_back(
4710  AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
4711  /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
4712  }
4713 
4714  // If exactly one matched, then we treat that as a successful match (and the
4715  // instruction will already have been filled in correctly, since the failing
4716  // matches won't have modified it).
4717  if (NumSuccessfulMatches == 1) {
4718  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4719  return true;
4720  // Some instructions need post-processing to, for example, tweak which
4721  // encoding is selected. Loop on it while changes happen so the individual
4722  // transformations can chain off each other.
4723  if (!MatchingInlineAsm)
4724  while (processInstruction(Inst, Operands))
4725  ;
4726  Inst.setLoc(IDLoc);
4727  if (!MatchingInlineAsm)
4728  emitInstruction(Inst, Operands, Out);
4729  Opcode = Inst.getOpcode();
4730  return false;
4731  } else if (NumSuccessfulMatches > 1) {
4732  assert(UnsizedMemOp &&
4733  "multiple matches only possible with unsized memory operands");
4734  return Error(UnsizedMemOp->getStartLoc(),
4735  "ambiguous operand size for instruction '" + Mnemonic + "\'",
4736  UnsizedMemOp->getLocRange());
4737  }
4738 
4739  // If one instruction matched as unsupported, report this as unsupported.
4740  if (std::count(std::begin(Match), std::end(Match),
4741  Match_Unsupported) == 1) {
4742  return Error(IDLoc, "unsupported instruction", EmptyRange,
4743  MatchingInlineAsm);
4744  }
4745 
4746  // If one instruction matched with a missing feature, report this as a
4747  // missing feature.
4748  if (std::count(std::begin(Match), std::end(Match),
4749  Match_MissingFeature) == 1) {
4750  ErrorInfo = Match_MissingFeature;
4751  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
4752  MatchingInlineAsm);
4753  }
4754 
4755  // If one instruction matched with an invalid operand, report this as an
4756  // operand failure.
4757  if (std::count(std::begin(Match), std::end(Match),
4758  Match_InvalidOperand) == 1) {
4759  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4760  MatchingInlineAsm);
4761  }
4762 
4763  if (std::count(std::begin(Match), std::end(Match),
4764  Match_InvalidImmUnsignedi4) == 1) {
4765  SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4766  if (ErrorLoc == SMLoc())
4767  ErrorLoc = IDLoc;
4768  return Error(ErrorLoc, "immediate must be an integer in range [0, 15]",
4769  EmptyRange, MatchingInlineAsm);
4770  }
4771 
4772  // If all of these were an outright failure, report it in a useless way.
4773  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
4774  MatchingInlineAsm);
4775 }
4776 
4777 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
4778  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
4779 }
4780 
4781 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
4782  MCAsmParser &Parser = getParser();
4783  StringRef IDVal = DirectiveID.getIdentifier();
4784  if (IDVal.startswith(".arch"))
4785  return parseDirectiveArch();
4786  if (IDVal.startswith(".code"))
4787  return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
4788  else if (IDVal.startswith(".att_syntax")) {
4789  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4790  if (Parser.getTok().getString() == "prefix")
4791  Parser.Lex();
4792  else if (Parser.getTok().getString() == "noprefix")
4793  return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
4794  "supported: registers must have a "
4795  "'%' prefix in .att_syntax");
4796  }
4797  getParser().setAssemblerDialect(0);
4798  return false;
4799  } else if (IDVal.startswith(".intel_syntax")) {
4800  getParser().setAssemblerDialect(1);
4801  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4802  if (Parser.getTok().getString() == "noprefix")
4803  Parser.Lex();
4804  else if (Parser.getTok().getString() == "prefix")
4805  return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
4806  "supported: registers must not have "
4807  "a '%' prefix in .intel_syntax");
4808  }
4809  return false;
4810  } else if (IDVal == ".nops")
4811  return parseDirectiveNops(DirectiveID.getLoc());
4812  else if (IDVal == ".even")
4813  return parseDirectiveEven(DirectiveID.getLoc());
4814  else if (IDVal == ".cv_fpo_proc")
4815  return parseDirectiveFPOProc(DirectiveID.getLoc());
4816  else if (IDVal == ".cv_fpo_setframe")
4817  return parseDirectiveFPOSetFrame(DirectiveID.getLoc());
4818  else if (IDVal == ".cv_fpo_pushreg")
4819  return parseDirectiveFPOPushReg(DirectiveID.getLoc());
4820  else if (IDVal == ".cv_fpo_stackalloc")
4821  return parseDirectiveFPOStackAlloc(DirectiveID.getLoc());
4822  else if (IDVal == ".cv_fpo_stackalign")
4823  return parseDirectiveFPOStackAlign(DirectiveID.getLoc());
4824  else if (IDVal == ".cv_fpo_endprologue")
4825  return parseDirectiveFPOEndPrologue(DirectiveID.getLoc());
4826  else if (IDVal == ".cv_fpo_endproc")
4827  return parseDirectiveFPOEndProc(DirectiveID.getLoc());
4828  else if (IDVal == ".seh_pushreg" ||
4829  (Parser.isParsingMasm() && IDVal.equals_insensitive(".pushreg")))
4830  return parseDirectiveSEHPushReg(DirectiveID.getLoc());
4831  else if (IDVal == ".seh_setframe" ||
4832  (Parser.isParsingMasm() && IDVal.equals_insensitive(".setframe")))
4833  return parseDirectiveSEHSetFrame(DirectiveID.getLoc());
4834  else if (IDVal == ".seh_savereg" ||
4835  (Parser.isParsingMasm() && IDVal.equals_insensitive(".savereg")))
4836  return parseDirectiveSEHSaveReg(DirectiveID.getLoc());
4837  else if (IDVal == ".seh_savexmm" ||
4838  (Parser.isParsingMasm() && IDVal.equals_insensitive(".savexmm128")))
4839  return parseDirectiveSEHSaveXMM(DirectiveID.getLoc());
4840  else if (IDVal == ".seh_pushframe" ||
4841  (Parser.isParsingMasm() && IDVal.equals_insensitive(".pushframe")))
4842  return parseDirectiveSEHPushFrame(DirectiveID.getLoc());
4843 
4844  return true;
4845 }
4846 
4847 bool X86AsmParser::parseDirectiveArch() {
4848  // Ignore .arch for now.
4849  getParser().parseStringToEndOfStatement();
4850  return false;
4851 }
4852 
4853 /// parseDirectiveNops
4854 /// ::= .nops size[, control]
4855 bool X86AsmParser::parseDirectiveNops(SMLoc L) {
4856  int64_t NumBytes = 0, Control = 0;
4857  SMLoc NumBytesLoc, ControlLoc;
4858  const MCSubtargetInfo& STI = getSTI();
4859  NumBytesLoc = getTok().getLoc();
4860  if (getParser().checkForValidSection() ||
4861  getParser().parseAbsoluteExpression(NumBytes))
4862  return true;
4863 
4864  if (parseOptionalToken(AsmToken::Comma)) {
4865  ControlLoc = getTok().getLoc();
4866  if (getParser().parseAbsoluteExpression(Control))
4867  return true;
4868  }
4869  if (getParser().parseToken(AsmToken::EndOfStatement,
4870  "unexpected token in '.nops' directive"))
4871  return true;
4872 
4873  if (NumBytes <= 0) {
4874  Error(NumBytesLoc, "'.nops' directive with non-positive size");
4875  return false;
4876  }
4877 
4878  if (Control < 0) {
4879  Error(ControlLoc, "'.nops' directive with negative NOP size");
4880  return false;
4881  }
4882 
4883  /// Emit nops
4884  getParser().getStreamer().emitNops(NumBytes, Control, L, STI);
4885 
4886  return false;
4887 }
4888 
4889 /// parseDirectiveEven
4890 /// ::= .even
4891 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
4892  if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
4893  return false;
4894 
4895  const MCSection *Section = getStreamer().getCurrentSectionOnly();
4896  if (!Section) {
4897  getStreamer().initSections(false, getSTI());
4898  Section = getStreamer().getCurrentSectionOnly();
4899  }
4900  if (Section->UseCodeAlign())
4901  getStreamer().emitCodeAlignment(2, &getSTI(), 0);
4902  else
4903  getStreamer().emitValueToAlignment(2, 0, 1, 0);
4904  return false;
4905 }
4906 
4907 /// ParseDirectiveCode
4908 /// ::= .code16 | .code32 | .code64
4909 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
4910  MCAsmParser &Parser = getParser();
4911  Code16GCC = false;
4912  if (IDVal == ".code16") {
4913  Parser.Lex();
4914  if (!is16BitMode()) {
4915  SwitchMode(X86::Mode16Bit);
4916  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
4917  }
4918  } else if (IDVal == ".code16gcc") {
4919  // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
4920  Parser.Lex();
4921  Code16GCC = true;
4922  if (!is16BitMode()) {
4923  SwitchMode(X86::Mode16Bit);
4924  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
4925  }
4926  } else if (IDVal == ".code32") {
4927  Parser.Lex();
4928  if (!is32BitMode()) {
4929  SwitchMode(X86::Mode32Bit);
4930  getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
4931  }
4932  } else if (IDVal == ".code64") {
4933  Parser.Lex();
4934  if (!is64BitMode()) {
4935  SwitchMode(X86::Mode64Bit);
4936  getParser().getStreamer().emitAssemblerFlag(MCAF_Code64);
4937  }
4938  } else {
4939  Error(L, "unknown directive " + IDVal);
4940  return false;
4941  }
4942 
4943  return false;
4944 }
4945 
4946 // .cv_fpo_proc foo
4947 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
4948  MCAsmParser &Parser = getParser();
4949  StringRef ProcName;
4950  int64_t ParamsSize;
4951  if (Parser.parseIdentifier(ProcName))
4952  return Parser.TokError("expected symbol name");
4953  if (Parser.parseIntToken(ParamsSize, "expected parameter byte count"))
4954  return true;
4955  if (!isUIntN(32, ParamsSize))
4956  return Parser.TokError("parameters size out of range");
4957  if (parseEOL())
4958  return true;
4959  MCSymbol *ProcSym = getContext().getOrCreateSymbol(ProcName);
4960  return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
4961 }
4962 
4963 // .cv_fpo_setframe ebp
4964 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
4965  unsigned Reg;
4966  SMLoc DummyLoc;
4967  if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
4968  return true;
4969  return getTargetStreamer().emitFPOSetFrame(Reg, L);
4970 }
4971 
4972 // .cv_fpo_pushreg ebx
4973 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
4974  unsigned Reg;
4975  SMLoc DummyLoc;
4976  if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
4977  return true;
4978  return getTargetStreamer().emitFPOPushReg(Reg, L);
4979 }
4980 
4981 // .cv_fpo_stackalloc 20
4982 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
4983  MCAsmParser &Parser = getParser();
4984  int64_t Offset;
4985  if (Parser.parseIntToken(Offset, "expected offset") || parseEOL())
4986  return true;
4987  return getTargetStreamer().emitFPOStackAlloc(Offset, L);
4988 }
4989 
4990 // .cv_fpo_stackalign 8
4991 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
4992  MCAsmParser &Parser = getParser();
4993  int64_t Offset;
4994  if (Parser.parseIntToken(Offset, "expected offset") || parseEOL())
4995  return true;
4996  return getTargetStreamer().emitFPOStackAlign(Offset, L);
4997 }
4998 
4999 // .cv_fpo_endprologue
5000 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
5001  MCAsmParser &Parser = getParser();
5002  if (Parser.parseEOL())
5003  return true;
5004  return getTargetStreamer().emitFPOEndPrologue(L);
5005 }
5006 
5007 // .cv_fpo_endproc
5008 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
5009  MCAsmParser &Parser = getParser();
5010  if (Parser.parseEOL())
5011  return true;
5012  return getTargetStreamer().emitFPOEndProc(L);
5013 }
5014 
5015 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
5016  unsigned &RegNo) {
5017  SMLoc startLoc = getLexer().getLoc();
5018  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
5019 
5020  // Try parsing the argument as a register first.
5021  if (getLexer().getTok().isNot(AsmToken::Integer)) {
5022  SMLoc endLoc;
5023  if (ParseRegister(RegNo, startLoc, endLoc))
5024  return true;
5025 
5026  if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) {
5027  return Error(startLoc,
5028  "register is not supported for use with this directive");
5029  }
5030  } else {
5031  // Otherwise, an integer number matching the encoding of the desired
5032  // register may appear.
5033  int64_t EncodedReg;
5034  if (getParser().parseAbsoluteExpression(EncodedReg))
5035  return true;
5036 
5037  // The SEH register number is the same as the encoding register number. Map
5038  // from the encoding back to the LLVM register number.
5039  RegNo = 0;
5040  for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
5041  if (MRI->getEncodingValue(Reg) == EncodedReg) {
5042  RegNo = Reg;
5043  break;
5044  }
5045  }
5046  if (RegNo == 0) {
5047  return Error(startLoc,
5048  "incorrect register number for use with this directive");
5049  }
5050  }
5051 
5052  return false;
5053 }
5054 
5055 bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
5056  unsigned Reg = 0;
5057  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5058  return true;
5059 
5060  if (getLexer().isNot(AsmToken::EndOfStatement))
5061  return TokError("unexpected token in directive");
5062 
5063  getParser().Lex();
5064  getStreamer().EmitWinCFIPushReg(Reg, Loc);
5065  return false;
5066 }
5067 
5068 bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
5069  unsigned Reg = 0;
5070  int64_t Off;
5071  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5072  return true;
5073  if (getLexer().isNot(AsmToken::Comma))
5074  return TokError("you must specify a stack pointer offset");
5075 
5076  getParser().Lex();
5077  if (getParser().parseAbsoluteExpression(Off))
5078  return true;
5079 
5080  if (getLexer().isNot(AsmToken::EndOfStatement))
5081  return TokError("unexpected token in directive");
5082 
5083  getParser().Lex();
5084  getStreamer().EmitWinCFISetFrame(Reg, Off, Loc);
5085  return false;
5086 }
5087 
5088 bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
5089  unsigned Reg = 0;
5090  int64_t Off;
5091  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5092  return true;
5093  if (getLexer().isNot(AsmToken::Comma))
5094  return TokError("you must specify an offset on the stack");
5095 
5096  getParser().Lex();
5097  if (getParser().parseAbsoluteExpression(Off))
5098  return true;
5099 
5100  if (getLexer().isNot(AsmToken::EndOfStatement))
5101  return TokError("unexpected token in directive");
5102 
5103  getParser().Lex();
5104  getStreamer().EmitWinCFISaveReg(Reg, Off, Loc);
5105  return false;
5106 }
5107 
5108 bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) {
5109  unsigned Reg = 0;
5110  int64_t Off;
5111  if (parseSEHRegisterNumber(X86::VR128XRegClassID, Reg))
5112  return true;
5113  if (getLexer().isNot(AsmToken::Comma))
5114  return TokError("you must specify an offset on the stack");
5115 
5116  getParser().Lex();
5117  if (getParser().parseAbsoluteExpression(Off))
5118  return true;
5119 
5120  if (getLexer().isNot(AsmToken::EndOfStatement))
5121  return TokError("unexpected token in directive");
5122 
5123  getParser().Lex();
5124  getStreamer().EmitWinCFISaveXMM(Reg, Off, Loc);
5125  return false;
5126 }
5127 
5128 bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) {
5129  bool Code = false;
5130  StringRef CodeID;
5131  if (getLexer().is(AsmToken::At)) {
5132  SMLoc startLoc = getLexer().getLoc();
5133  getParser().Lex();
5134  if (!getParser().parseIdentifier(CodeID)) {
5135  if (CodeID != "code")
5136  return Error(startLoc, "expected @code");
5137  Code = true;
5138  }
5139  }
5140 
5141  if (getLexer().isNot(AsmToken::EndOfStatement))
5142  return TokError("unexpected token in directive");
5143 
5144  getParser().Lex();
5145  getStreamer().EmitWinCFIPushFrame(Code, Loc);
5146  return false;
5147 }
5148 
5149 // Force static initialization.
5153 }
5154 
5155 #define GET_REGISTER_MATCHER
5156 #define GET_MATCHER_IMPLEMENTATION
5157 #define GET_SUBTARGET_FEATURE_NAME
5158 #include "X86GenAsmMatcher.inc"
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::MCTargetStreamer::getStreamer
MCStreamer & getStreamer()
Definition: MCStreamer.h:99
checkScale
static bool checkScale(unsigned Scale, StringRef &ErrMsg)
Definition: X86AsmParser.cpp:49
i
i
Definition: README.txt:29
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
llvm::StringRef::back
LLVM_NODISCARD char back() const
back - Get the last character in the string.
Definition: StringRef.h:168
llvm::AsmFieldInfo::Offset
unsigned Offset
Definition: MCAsmParser.h:105
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:286
llvm::MCAsmParser::Error
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:99
getSubtargetFeatureName
static const char * getSubtargetFeatureName(uint64_t Val)
llvm::X86II::REX_W
@ REX_W
Definition: X86BaseInfo.h:833
llvm::X86Operand::getEndLoc
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:91
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::AsmToken::is
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::N86::ESP
@ ESP
Definition: X86MCTargetDesc.h:51
llvm::X86Operand::Mem
struct MemOp Mem
Definition: X86Operand.h:76
llvm::MCAsmLexer
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:39
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:164
llvm::pdb::PDB_DataKind::Member
@ Member
llvm::StringRef::endswith
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:297
llvm::X86::TO_POS_INF
@ TO_POS_INF
Definition: X86BaseInfo.h:49
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::AsmToken::LBrac
@ LBrac
Definition: MCAsmMacro.h:48
Note
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles Note
Definition: README.txt:239
llvm::AsmToken::Dot
@ Dot
Definition: MCAsmMacro.h:49
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
llvm::AsmToken::EndOfStatement
@ EndOfStatement
Definition: MCAsmMacro.h:42
llvm::X86Operand::isMem8
bool isMem8() const
Definition: X86Operand.h:295
llvm::MCAsmParser::parseEOL
bool parseEOL()
Definition: MCAsmParser.cpp:47
llvm::AsmToken::getIntVal
int64_t getIntVal() const
Definition: MCAsmMacro.h:115
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:60
llvm::X86::COND_BE
@ COND_BE
Definition: X86BaseInfo.h:87
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::tgtok::Code
@ Code
Definition: TGLexer.h:50
MCParsedAsmOperand.h
llvm::MCAsmParser::parseIdentifier
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents.
CH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference CH
Definition: README-X86-64.txt:44
llvm::X86::COND_P
@ COND_P
Definition: X86BaseInfo.h:91
llvm::X86::COND_GE
@ COND_GE
Definition: X86BaseInfo.h:94
llvm::MCSymbol::isUndefined
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:252
llvm::pdb::PDB_BuiltinType::Variant
@ Variant
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MemOp
Definition: TargetLowering.h:112
llvm::X86::COND_L
@ COND_L
Definition: X86BaseInfo.h:93
llvm::X86::IP_HAS_LOCK
@ IP_HAS_LOCK
Definition: X86BaseInfo.h:62
startswith
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:30
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::X86::IP_USE_DISP8
@ IP_USE_DISP8
Definition: X86BaseInfo.h:68
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::AsmToken::Integer
@ Integer
Definition: MCAsmMacro.h:32
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::MCAsmParser::parseOptionalToken
bool parseOptionalToken(AsmToken::TokenKind T)
Attempt to parse and consume token, returning true on success.
Definition: MCAsmParser.cpp:78
llvm::AsmTypeInfo::Name
StringRef Name
Definition: MCAsmParser.h:97
llvm::FenceInst
An instruction for ordering other memory operations.
Definition: Instructions.h:444
llvm::X86Operand::isMem
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:291
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::InlineAsmIdentifierInfo
Definition: MCAsmParser.h:37
STLExtras.h
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:635
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86::CondCode
CondCode
Definition: X86BaseInfo.h:80
llvm::InlineAsmIdentifierInfo::IK_EnumVal
@ IK_EnumVal
Definition: MCAsmParser.h:41
llvm::StringRef::slice
LLVM_NODISCARD StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:732
llvm::X86::COND_INVALID
@ COND_INVALID
Definition: X86BaseInfo.h:107
llvm::getX86SubSuperRegisterOrZero
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:613
getSym
static ModuleSymbolTable::Symbol getSym(DataRefImpl &Symb)
Definition: IRObjectFile.cpp:37
MCAsmParser.h
llvm::X86::COND_S
@ COND_S
Definition: X86BaseInfo.h:89
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
MCTargetAsmParser.h
llvm::X86::IP_HAS_NOTRACK
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:63
llvm::X86Operand::isReg
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:461
llvm::X86II::VEX
@ VEX
Definition: X86BaseInfo.h:903
llvm::MCAsmParser::parseAbsoluteExpression
virtual bool parseAbsoluteExpression(int64_t &Res)=0
Parse an expression which must evaluate to an absolute value.
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
llvm::HighlightColor::Warning
@ Warning
llvm::X86::COND_O
@ COND_O
Definition: X86BaseInfo.h:81
llvm::X86Operand::CreatePrefix
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:643
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::AsmToken::Minus
@ Minus
Definition: MCAsmMacro.h:45
llvm::ARMBuildAttrs::Section
@ Section
Legacy Tags.
Definition: ARMBuildAttributes.h:78
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:611
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
CommandLine.h
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::AsmToken::Dollar
@ Dollar
Definition: MCAsmMacro.h:49
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1335
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::MCAsmParser::parseExpression
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1317
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:122
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
SmallString.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:749
getPrefixes
static unsigned getPrefixes(OperandVector &Operands)
Definition: X86AsmParser.cpp:4242
llvm::AsmToken::GreaterGreater
@ GreaterGreater
Definition: MCAsmMacro.h:54
llvm::AsmTypeInfo::Size
unsigned Size
Definition: MCAsmParser.h:98
Twine.h
llvm::MCAsmParser::parseIntToken
bool parseIntToken(int64_t &V, const Twine &ErrMsg)
Definition: MCAsmParser.cpp:70
llvm::X86::IP_USE_EVEX
@ IP_USE_EVEX
Definition: X86BaseInfo.h:67
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::AsmTypeInfo
Definition: MCAsmParser.h:96
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::X86II::isX86_64ExtendedReg
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1180
llvm::MCAF_Code16
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:53
MCInst.h
false
Definition: StackSlotColoring.cpp:142
llvm::MCInstrDesc::isTerminator
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:292
llvm::MCSymbol::getVariableValue
const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
Definition: MCSymbol.h:298
llvm::dwarf::toStringRef
StringRef toStringRef(const Optional< DWARFFormValue > &V, StringRef Default={})
Take an optional DWARFFormValue and try to extract a string value from it.
Definition: DWARFFormValue.h:186
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::isUIntN
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:455
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::AsmToken::Star
@ Star
Definition: MCAsmMacro.h:49
llvm::MCAsmParser::getContext
virtual MCContext & getContext()=0
llvm::ParseInstructionInfo::AsmRewrites
SmallVectorImpl< AsmRewrite > * AsmRewrites
Definition: MCTargetAsmParser.h:114
llvm::MCAsmParser::isParsingMasm
virtual bool isParsingMasm() const
Definition: MCAsmParser.h:188