LLVM  16.0.0git
X86ExpandPseudo.cpp
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1 //===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling, if-conversion, other late
11 // optimizations, or simply the encoding of the instructions.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86.h"
16 #include "X86FrameLowering.h"
17 #include "X86InstrBuilder.h"
18 #include "X86InstrInfo.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
25 #include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
26 #include "llvm/IR/GlobalValue.h"
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "x86-pseudo"
31 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
32 
33 namespace {
34 class X86ExpandPseudo : public MachineFunctionPass {
35 public:
36  static char ID;
37  X86ExpandPseudo() : MachineFunctionPass(ID) {}
38 
39  void getAnalysisUsage(AnalysisUsage &AU) const override {
40  AU.setPreservesCFG();
44  }
45 
46  const X86Subtarget *STI = nullptr;
47  const X86InstrInfo *TII = nullptr;
48  const X86RegisterInfo *TRI = nullptr;
49  const X86MachineFunctionInfo *X86FI = nullptr;
50  const X86FrameLowering *X86FL = nullptr;
51 
52  bool runOnMachineFunction(MachineFunction &Fn) override;
53 
54  MachineFunctionProperties getRequiredProperties() const override {
57  }
58 
59  StringRef getPassName() const override {
60  return "X86 pseudo instruction expansion pass";
61  }
62 
63 private:
64  void ExpandICallBranchFunnel(MachineBasicBlock *MBB,
66  void expandCALL_RVMARKER(MachineBasicBlock &MBB,
69  bool ExpandMBB(MachineBasicBlock &MBB);
70 
71  /// This function expands pseudos which affects control flow.
72  /// It is done in separate pass to simplify blocks navigation in main
73  /// pass(calling ExpandMBB).
74  bool ExpandPseudosWhichAffectControlFlow(MachineFunction &MF);
75 
76  /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
77  /// placed into separate block guarded by check for al register(for SystemV
78  /// abi).
79  void ExpandVastartSaveXmmRegs(
81  MachineBasicBlock::iterator VAStartPseudoInstr) const;
82 };
83 char X86ExpandPseudo::ID = 0;
84 
85 } // End anonymous namespace.
86 
88  false)
89 
90 void X86ExpandPseudo::ExpandICallBranchFunnel(
92  MachineBasicBlock *JTMBB = MBB;
93  MachineInstr *JTInst = &*MBBI;
94  MachineFunction *MF = MBB->getParent();
95  const BasicBlock *BB = MBB->getBasicBlock();
96  auto InsPt = MachineFunction::iterator(MBB);
97  ++InsPt;
98 
99  std::vector<std::pair<MachineBasicBlock *, unsigned>> TargetMBBs;
100  const DebugLoc &DL = JTInst->getDebugLoc();
101  MachineOperand Selector = JTInst->getOperand(0);
102  const GlobalValue *CombinedGlobal = JTInst->getOperand(1).getGlobal();
103 
104  auto CmpTarget = [&](unsigned Target) {
105  if (Selector.isReg())
106  MBB->addLiveIn(Selector.getReg());
107  BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
108  .addReg(X86::RIP)
109  .addImm(1)
110  .addReg(0)
111  .addGlobalAddress(CombinedGlobal,
112  JTInst->getOperand(2 + 2 * Target).getImm())
113  .addReg(0);
114  BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
115  .add(Selector)
116  .addReg(X86::R11);
117  };
118 
119  auto CreateMBB = [&]() {
120  auto *NewMBB = MF->CreateMachineBasicBlock(BB);
121  MBB->addSuccessor(NewMBB);
122  if (!MBB->isLiveIn(X86::EFLAGS))
123  MBB->addLiveIn(X86::EFLAGS);
124  return NewMBB;
125  };
126 
127  auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
128  BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
129 
130  auto *ElseMBB = CreateMBB();
131  MF->insert(InsPt, ElseMBB);
132  MBB = ElseMBB;
133  MBBI = MBB->end();
134  };
135 
136  auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
137  auto *ThenMBB = CreateMBB();
138  TargetMBBs.push_back({ThenMBB, Target});
139  EmitCondJump(CC, ThenMBB);
140  };
141 
142  auto EmitTailCall = [&](unsigned Target) {
143  BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64))
144  .add(JTInst->getOperand(3 + 2 * Target));
145  };
146 
147  std::function<void(unsigned, unsigned)> EmitBranchFunnel =
148  [&](unsigned FirstTarget, unsigned NumTargets) {
149  if (NumTargets == 1) {
150  EmitTailCall(FirstTarget);
151  return;
152  }
153 
154  if (NumTargets == 2) {
155  CmpTarget(FirstTarget + 1);
156  EmitCondJumpTarget(X86::COND_B, FirstTarget);
157  EmitTailCall(FirstTarget + 1);
158  return;
159  }
160 
161  if (NumTargets < 6) {
162  CmpTarget(FirstTarget + 1);
163  EmitCondJumpTarget(X86::COND_B, FirstTarget);
164  EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
165  EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
166  return;
167  }
168 
169  auto *ThenMBB = CreateMBB();
170  CmpTarget(FirstTarget + (NumTargets / 2));
171  EmitCondJump(X86::COND_B, ThenMBB);
172  EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
173  EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
174  NumTargets - (NumTargets / 2) - 1);
175 
176  MF->insert(InsPt, ThenMBB);
177  MBB = ThenMBB;
178  MBBI = MBB->end();
179  EmitBranchFunnel(FirstTarget, NumTargets / 2);
180  };
181 
182  EmitBranchFunnel(0, (JTInst->getNumOperands() - 2) / 2);
183  for (auto P : TargetMBBs) {
184  MF->insert(InsPt, P.first);
185  BuildMI(P.first, DL, TII->get(X86::TAILJMPd64))
186  .add(JTInst->getOperand(3 + 2 * P.second));
187  }
188  JTMBB->erase(JTInst);
189 }
190 
191 void X86ExpandPseudo::expandCALL_RVMARKER(MachineBasicBlock &MBB,
193  // Expand CALL_RVMARKER pseudo to call instruction, followed by the special
194  //"movq %rax, %rdi" marker.
195  MachineInstr &MI = *MBBI;
196 
197  MachineInstr *OriginalCall;
198  assert((MI.getOperand(1).isGlobal() || MI.getOperand(1).isReg()) &&
199  "invalid operand for regular call");
200  unsigned Opc = -1;
201  if (MI.getOpcode() == X86::CALL64m_RVMARKER)
202  Opc = X86::CALL64m;
203  else if (MI.getOpcode() == X86::CALL64r_RVMARKER)
204  Opc = X86::CALL64r;
205  else if (MI.getOpcode() == X86::CALL64pcrel32_RVMARKER)
206  Opc = X86::CALL64pcrel32;
207  else
208  llvm_unreachable("unexpected opcode");
209 
210  OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr();
211  bool RAXImplicitDead = false;
212  for (MachineOperand &Op : llvm::drop_begin(MI.operands())) {
213  // RAX may be 'implicit dead', if there are no other users of the return
214  // value. We introduce a new use, so change it to 'implicit def'.
215  if (Op.isReg() && Op.isImplicit() && Op.isDead() &&
216  TRI->regsOverlap(Op.getReg(), X86::RAX)) {
217  Op.setIsDead(false);
218  Op.setIsDef(true);
219  RAXImplicitDead = true;
220  }
221  OriginalCall->addOperand(Op);
222  }
223 
224  // Emit marker "movq %rax, %rdi". %rdi is not callee-saved, so it cannot be
225  // live across the earlier call. The call to the ObjC runtime function returns
226  // the first argument, so the value of %rax is unchanged after the ObjC
227  // runtime call. On Windows targets, the runtime call follows the regular
228  // x64 calling convention and expects the first argument in %rcx.
229  auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI;
230  auto *Marker = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::MOV64rr))
231  .addReg(TargetReg, RegState::Define)
232  .addReg(X86::RAX)
233  .getInstr();
234  if (MI.shouldUpdateCallSiteInfo())
235  MBB.getParent()->moveCallSiteInfo(&MI, Marker);
236 
237  // Emit call to ObjC runtime.
238  const uint32_t *RegMask =
240  MachineInstr *RtCall =
241  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::CALL64pcrel32))
242  .addGlobalAddress(MI.getOperand(0).getGlobal(), 0, 0)
243  .addRegMask(RegMask)
244  .addReg(X86::RAX,
246  (RAXImplicitDead ? (RegState::Dead | RegState::Define)
247  : RegState::Define))
248  .getInstr();
249  MI.eraseFromParent();
250 
251  auto &TM = MBB.getParent()->getTarget();
252  // On Darwin platforms, wrap the expanded sequence in a bundle to prevent
253  // later optimizations from breaking up the sequence.
254  if (TM.getTargetTriple().isOSDarwin())
255  finalizeBundle(MBB, OriginalCall->getIterator(),
256  std::next(RtCall->getIterator()));
257 }
258 
259 /// If \p MBBI is a pseudo instruction, this method expands
260 /// it to the corresponding (sequence of) actual instruction(s).
261 /// \returns true if \p MBBI has been expanded.
262 bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
264  MachineInstr &MI = *MBBI;
265  unsigned Opcode = MI.getOpcode();
266  const DebugLoc &DL = MBBI->getDebugLoc();
267  switch (Opcode) {
268  default:
269  return false;
270  case X86::TCRETURNdi:
271  case X86::TCRETURNdicc:
272  case X86::TCRETURNri:
273  case X86::TCRETURNmi:
274  case X86::TCRETURNdi64:
275  case X86::TCRETURNdi64cc:
276  case X86::TCRETURNri64:
277  case X86::TCRETURNmi64: {
278  bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
279  MachineOperand &JumpTarget = MBBI->getOperand(0);
280  MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands
281  : 1);
282  assert(StackAdjust.isImm() && "Expecting immediate value.");
283 
284  // Adjust stack pointer.
285  int StackAdj = StackAdjust.getImm();
286  int MaxTCDelta = X86FI->getTCReturnAddrDelta();
287  int Offset = 0;
288  assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
289 
290  // Incoporate the retaddr area.
291  Offset = StackAdj - MaxTCDelta;
292  assert(Offset >= 0 && "Offset should never be negative");
293 
294  if (Opcode == X86::TCRETURNdicc || Opcode == X86::TCRETURNdi64cc) {
295  assert(Offset == 0 && "Conditional tail call cannot adjust the stack.");
296  }
297 
298  if (Offset) {
299  // Check for possible merge with preceding ADD instruction.
300  Offset += X86FL->mergeSPUpdates(MBB, MBBI, true);
301  X86FL->emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue=*/true);
302  }
303 
304  // Jump to label or value in register.
305  bool IsWin64 = STI->isTargetWin64();
306  if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdicc ||
307  Opcode == X86::TCRETURNdi64 || Opcode == X86::TCRETURNdi64cc) {
308  unsigned Op;
309  switch (Opcode) {
310  case X86::TCRETURNdi:
311  Op = X86::TAILJMPd;
312  break;
313  case X86::TCRETURNdicc:
314  Op = X86::TAILJMPd_CC;
315  break;
316  case X86::TCRETURNdi64cc:
317  assert(!MBB.getParent()->hasWinCFI() &&
318  "Conditional tail calls confuse "
319  "the Win64 unwinder.");
320  Op = X86::TAILJMPd64_CC;
321  break;
322  default:
323  // Note: Win64 uses REX prefixes indirect jumps out of functions, but
324  // not direct ones.
325  Op = X86::TAILJMPd64;
326  break;
327  }
328  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
329  if (JumpTarget.isGlobal()) {
330  MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
331  JumpTarget.getTargetFlags());
332  } else {
333  assert(JumpTarget.isSymbol());
334  MIB.addExternalSymbol(JumpTarget.getSymbolName(),
335  JumpTarget.getTargetFlags());
336  }
337  if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) {
338  MIB.addImm(MBBI->getOperand(2).getImm());
339  }
340 
341  } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
342  unsigned Op = (Opcode == X86::TCRETURNmi)
343  ? X86::TAILJMPm
344  : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
345  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
346  for (unsigned i = 0; i != X86::AddrNumOperands; ++i)
347  MIB.add(MBBI->getOperand(i));
348  } else if (Opcode == X86::TCRETURNri64) {
349  JumpTarget.setIsKill();
350  BuildMI(MBB, MBBI, DL,
351  TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
352  .add(JumpTarget);
353  } else {
354  JumpTarget.setIsKill();
355  BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
356  .add(JumpTarget);
357  }
358 
359  MachineInstr &NewMI = *std::prev(MBBI);
360  NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
361  NewMI.setCFIType(*MBB.getParent(), MI.getCFIType());
362 
363  // Update the call site info.
364  if (MBBI->isCandidateForCallSiteEntry())
365  MBB.getParent()->moveCallSiteInfo(&*MBBI, &NewMI);
366 
367  // Delete the pseudo instruction TCRETURN.
368  MBB.erase(MBBI);
369 
370  return true;
371  }
372  case X86::EH_RETURN:
373  case X86::EH_RETURN64: {
374  MachineOperand &DestAddr = MBBI->getOperand(0);
375  assert(DestAddr.isReg() && "Offset should be in register!");
376  const bool Uses64BitFramePtr =
377  STI->isTarget64BitLP64() || STI->isTargetNaCl64();
378  Register StackPtr = TRI->getStackRegister();
379  BuildMI(MBB, MBBI, DL,
380  TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
381  .addReg(DestAddr.getReg());
382  // The EH_RETURN pseudo is really removed during the MC Lowering.
383  return true;
384  }
385  case X86::IRET: {
386  // Adjust stack to erase error code
387  int64_t StackAdj = MBBI->getOperand(0).getImm();
388  X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true);
389  // Replace pseudo with machine iret
390  unsigned RetOp = STI->is64Bit() ? X86::IRET64 : X86::IRET32;
391  // Use UIRET if UINTR is present (except for building kernel)
392  if (STI->is64Bit() && STI->hasUINTR() &&
394  RetOp = X86::UIRET;
395  BuildMI(MBB, MBBI, DL, TII->get(RetOp));
396  MBB.erase(MBBI);
397  return true;
398  }
399  case X86::RET: {
400  // Adjust stack to erase error code
401  int64_t StackAdj = MBBI->getOperand(0).getImm();
403  if (StackAdj == 0) {
404  MIB = BuildMI(MBB, MBBI, DL,
405  TII->get(STI->is64Bit() ? X86::RET64 : X86::RET32));
406  } else if (isUInt<16>(StackAdj)) {
407  MIB = BuildMI(MBB, MBBI, DL,
408  TII->get(STI->is64Bit() ? X86::RETI64 : X86::RETI32))
409  .addImm(StackAdj);
410  } else {
411  assert(!STI->is64Bit() &&
412  "shouldn't need to do this for x86_64 targets!");
413  // A ret can only handle immediates as big as 2**16-1. If we need to pop
414  // off bytes before the return address, we must do it manually.
415  BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
416  X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true);
417  BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
418  MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RET32));
419  }
420  for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
421  MIB.add(MBBI->getOperand(I));
422  MBB.erase(MBBI);
423  return true;
424  }
425  case X86::LCMPXCHG16B_SAVE_RBX: {
426  // Perform the following transformation.
427  // SaveRbx = pseudocmpxchg Addr, <4 opds for the address>, InArg, SaveRbx
428  // =>
429  // RBX = InArg
430  // actualcmpxchg Addr
431  // RBX = SaveRbx
432  const MachineOperand &InArg = MBBI->getOperand(6);
433  Register SaveRbx = MBBI->getOperand(7).getReg();
434 
435  // Copy the input argument of the pseudo into the argument of the
436  // actual instruction.
437  // NOTE: We don't copy the kill flag since the input might be the same reg
438  // as one of the other operands of LCMPXCHG16B.
439  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, InArg.getReg(), false);
440  // Create the actual instruction.
441  MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(X86::LCMPXCHG16B));
442  // Copy the operands related to the address.
443  for (unsigned Idx = 1; Idx < 6; ++Idx)
444  NewInstr->addOperand(MBBI->getOperand(Idx));
445  // Finally, restore the value of RBX.
446  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx,
447  /*SrcIsKill*/ true);
448 
449  // Delete the pseudo.
451  return true;
452  }
453  // Loading/storing mask pairs requires two kmov operations. The second one of
454  // these needs a 2 byte displacement relative to the specified address (with
455  // 32 bit spill size). The pairs of 1bit masks up to 16 bit masks all use the
456  // same spill size, they all are stored using MASKPAIR16STORE, loaded using
457  // MASKPAIR16LOAD.
458  //
459  // The displacement value might wrap around in theory, thus the asserts in
460  // both cases.
461  case X86::MASKPAIR16LOAD: {
462  int64_t Disp = MBBI->getOperand(1 + X86::AddrDisp).getImm();
463  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
464  Register Reg = MBBI->getOperand(0).getReg();
465  bool DstIsDead = MBBI->getOperand(0).isDead();
466  Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
467  Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
468 
469  auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
470  .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead));
471  auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
472  .addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead));
473 
474  for (int i = 0; i < X86::AddrNumOperands; ++i) {
475  MIBLo.add(MBBI->getOperand(1 + i));
476  if (i == X86::AddrDisp)
477  MIBHi.addImm(Disp + 2);
478  else
479  MIBHi.add(MBBI->getOperand(1 + i));
480  }
481 
482  // Split the memory operand, adjusting the offset and size for the halves.
483  MachineMemOperand *OldMMO = MBBI->memoperands().front();
484  MachineFunction *MF = MBB.getParent();
485  MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
486  MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
487 
488  MIBLo.setMemRefs(MMOLo);
489  MIBHi.setMemRefs(MMOHi);
490 
491  // Delete the pseudo.
492  MBB.erase(MBBI);
493  return true;
494  }
495  case X86::MASKPAIR16STORE: {
496  int64_t Disp = MBBI->getOperand(X86::AddrDisp).getImm();
497  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
498  Register Reg = MBBI->getOperand(X86::AddrNumOperands).getReg();
499  bool SrcIsKill = MBBI->getOperand(X86::AddrNumOperands).isKill();
500  Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
501  Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
502 
503  auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
504  auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
505 
506  for (int i = 0; i < X86::AddrNumOperands; ++i) {
507  MIBLo.add(MBBI->getOperand(i));
508  if (i == X86::AddrDisp)
509  MIBHi.addImm(Disp + 2);
510  else
511  MIBHi.add(MBBI->getOperand(i));
512  }
513  MIBLo.addReg(Reg0, getKillRegState(SrcIsKill));
514  MIBHi.addReg(Reg1, getKillRegState(SrcIsKill));
515 
516  // Split the memory operand, adjusting the offset and size for the halves.
517  MachineMemOperand *OldMMO = MBBI->memoperands().front();
518  MachineFunction *MF = MBB.getParent();
519  MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
520  MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
521 
522  MIBLo.setMemRefs(MMOLo);
523  MIBHi.setMemRefs(MMOHi);
524 
525  // Delete the pseudo.
526  MBB.erase(MBBI);
527  return true;
528  }
529  case X86::MWAITX_SAVE_RBX: {
530  // Perform the following transformation.
531  // SaveRbx = pseudomwaitx InArg, SaveRbx
532  // =>
533  // [E|R]BX = InArg
534  // actualmwaitx
535  // [E|R]BX = SaveRbx
536  const MachineOperand &InArg = MBBI->getOperand(1);
537  // Copy the input argument of the pseudo into the argument of the
538  // actual instruction.
539  TII->copyPhysReg(MBB, MBBI, DL, X86::EBX, InArg.getReg(), InArg.isKill());
540  // Create the actual instruction.
541  BuildMI(MBB, MBBI, DL, TII->get(X86::MWAITXrrr));
542  // Finally, restore the value of RBX.
543  Register SaveRbx = MBBI->getOperand(2).getReg();
544  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, /*SrcIsKill*/ true);
545  // Delete the pseudo.
547  return true;
548  }
549  case TargetOpcode::ICALL_BRANCH_FUNNEL:
550  ExpandICallBranchFunnel(&MBB, MBBI);
551  return true;
552  case X86::PLDTILECFGV: {
553  MI.setDesc(TII->get(X86::LDTILECFG));
554  return true;
555  }
556  case X86::PTILELOADDV:
557  case X86::PTILELOADDT1V: {
558  for (unsigned i = 2; i > 0; --i)
559  MI.removeOperand(i);
560  unsigned Opc =
561  Opcode == X86::PTILELOADDV ? X86::TILELOADD : X86::TILELOADDT1;
562  MI.setDesc(TII->get(Opc));
563  return true;
564  }
565  case X86::PTDPBSSDV:
566  case X86::PTDPBSUDV:
567  case X86::PTDPBUSDV:
568  case X86::PTDPBUUDV:
569  case X86::PTDPBF16PSV:
570  case X86::PTDPFP16PSV: {
571  MI.untieRegOperand(4);
572  for (unsigned i = 3; i > 0; --i)
573  MI.removeOperand(i);
574  unsigned Opc;
575  switch (Opcode) {
576  case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break;
577  case X86::PTDPBSUDV: Opc = X86::TDPBSUD; break;
578  case X86::PTDPBUSDV: Opc = X86::TDPBUSD; break;
579  case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break;
580  case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break;
581  case X86::PTDPFP16PSV: Opc = X86::TDPFP16PS; break;
582  default: llvm_unreachable("Impossible Opcode!");
583  }
584  MI.setDesc(TII->get(Opc));
585  MI.tieOperands(0, 1);
586  return true;
587  }
588  case X86::PTILESTOREDV: {
589  for (int i = 1; i >= 0; --i)
590  MI.removeOperand(i);
591  MI.setDesc(TII->get(X86::TILESTORED));
592  return true;
593  }
594  case X86::PTILEZEROV: {
595  for (int i = 2; i > 0; --i) // Remove row, col
596  MI.removeOperand(i);
597  MI.setDesc(TII->get(X86::TILEZERO));
598  return true;
599  }
600  case X86::CALL64pcrel32_RVMARKER:
601  case X86::CALL64r_RVMARKER:
602  case X86::CALL64m_RVMARKER:
603  expandCALL_RVMARKER(MBB, MBBI);
604  return true;
605  }
606  llvm_unreachable("Previous switch has a fallthrough?");
607 }
608 
609 // This function creates additional block for storing varargs guarded
610 // registers. It adds check for %al into entry block, to skip
611 // GuardedRegsBlk if xmm registers should not be stored.
612 //
613 // EntryBlk[VAStartPseudoInstr] EntryBlk
614 // | | .
615 // | | .
616 // | | GuardedRegsBlk
617 // | => | .
618 // | | .
619 // | TailBlk
620 // | |
621 // | |
622 //
623 void X86ExpandPseudo::ExpandVastartSaveXmmRegs(
624  MachineBasicBlock *EntryBlk,
625  MachineBasicBlock::iterator VAStartPseudoInstr) const {
626  assert(VAStartPseudoInstr->getOpcode() == X86::VASTART_SAVE_XMM_REGS);
627 
628  MachineFunction *Func = EntryBlk->getParent();
629  const TargetInstrInfo *TII = STI->getInstrInfo();
630  const DebugLoc &DL = VAStartPseudoInstr->getDebugLoc();
631  Register CountReg = VAStartPseudoInstr->getOperand(0).getReg();
632 
633  // Calculate liveins for newly created blocks.
634  LivePhysRegs LiveRegs(*STI->getRegisterInfo());
636 
637  LiveRegs.addLiveIns(*EntryBlk);
638  for (MachineInstr &MI : EntryBlk->instrs()) {
639  if (MI.getOpcode() == VAStartPseudoInstr->getOpcode())
640  break;
641 
642  LiveRegs.stepForward(MI, Clobbers);
643  }
644 
645  // Create the new basic blocks. One block contains all the XMM stores,
646  // and another block is the final destination regardless of whether any
647  // stores were performed.
648  const BasicBlock *LLVMBlk = EntryBlk->getBasicBlock();
649  MachineFunction::iterator EntryBlkIter = ++EntryBlk->getIterator();
650  MachineBasicBlock *GuardedRegsBlk = Func->CreateMachineBasicBlock(LLVMBlk);
651  MachineBasicBlock *TailBlk = Func->CreateMachineBasicBlock(LLVMBlk);
652  Func->insert(EntryBlkIter, GuardedRegsBlk);
653  Func->insert(EntryBlkIter, TailBlk);
654 
655  // Transfer the remainder of EntryBlk and its successor edges to TailBlk.
656  TailBlk->splice(TailBlk->begin(), EntryBlk,
657  std::next(MachineBasicBlock::iterator(VAStartPseudoInstr)),
658  EntryBlk->end());
659  TailBlk->transferSuccessorsAndUpdatePHIs(EntryBlk);
660 
661  uint64_t FrameOffset = VAStartPseudoInstr->getOperand(4).getImm();
662  uint64_t VarArgsRegsOffset = VAStartPseudoInstr->getOperand(6).getImm();
663 
664  // TODO: add support for YMM and ZMM here.
665  unsigned MOVOpc = STI->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
666 
667  // In the XMM save block, save all the XMM argument registers.
668  for (int64_t OpndIdx = 7, RegIdx = 0;
669  OpndIdx < VAStartPseudoInstr->getNumOperands() - 1;
670  OpndIdx++, RegIdx++) {
671  auto NewMI = BuildMI(GuardedRegsBlk, DL, TII->get(MOVOpc));
672  for (int i = 0; i < X86::AddrNumOperands; ++i) {
673  if (i == X86::AddrDisp)
674  NewMI.addImm(FrameOffset + VarArgsRegsOffset + RegIdx * 16);
675  else
676  NewMI.add(VAStartPseudoInstr->getOperand(i + 1));
677  }
678  NewMI.addReg(VAStartPseudoInstr->getOperand(OpndIdx).getReg());
680  VAStartPseudoInstr->getOperand(OpndIdx).getReg()));
681  }
682 
683  // The original block will now fall through to the GuardedRegsBlk.
684  EntryBlk->addSuccessor(GuardedRegsBlk);
685  // The GuardedRegsBlk will fall through to the TailBlk.
686  GuardedRegsBlk->addSuccessor(TailBlk);
687 
688  if (!STI->isCallingConvWin64(Func->getFunction().getCallingConv())) {
689  // If %al is 0, branch around the XMM save block.
690  BuildMI(EntryBlk, DL, TII->get(X86::TEST8rr))
691  .addReg(CountReg)
692  .addReg(CountReg);
693  BuildMI(EntryBlk, DL, TII->get(X86::JCC_1))
694  .addMBB(TailBlk)
696  EntryBlk->addSuccessor(TailBlk);
697  }
698 
699  // Add liveins to the created block.
700  addLiveIns(*GuardedRegsBlk, LiveRegs);
701  addLiveIns(*TailBlk, LiveRegs);
702 
703  // Delete the pseudo.
704  VAStartPseudoInstr->eraseFromParent();
705 }
706 
707 /// Expand all pseudo instructions contained in \p MBB.
708 /// \returns true if any expansion occurred for \p MBB.
709 bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
710  bool Modified = false;
711 
712  // MBBI may be invalidated by the expansion.
714  while (MBBI != E) {
715  MachineBasicBlock::iterator NMBBI = std::next(MBBI);
716  Modified |= ExpandMI(MBB, MBBI);
717  MBBI = NMBBI;
718  }
719 
720  return Modified;
721 }
722 
723 bool X86ExpandPseudo::ExpandPseudosWhichAffectControlFlow(MachineFunction &MF) {
724  // Currently pseudo which affects control flow is only
725  // X86::VASTART_SAVE_XMM_REGS which is located in Entry block.
726  // So we do not need to evaluate other blocks.
727  for (MachineInstr &Instr : MF.front().instrs()) {
728  if (Instr.getOpcode() == X86::VASTART_SAVE_XMM_REGS) {
729  ExpandVastartSaveXmmRegs(&(MF.front()), Instr);
730  return true;
731  }
732  }
733 
734  return false;
735 }
736 
737 bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
738  STI = &MF.getSubtarget<X86Subtarget>();
739  TII = STI->getInstrInfo();
740  TRI = STI->getRegisterInfo();
741  X86FI = MF.getInfo<X86MachineFunctionInfo>();
742  X86FL = STI->getFrameLowering();
743 
744  bool Modified = ExpandPseudosWhichAffectControlFlow(MF);
745 
746  for (MachineBasicBlock &MBB : MF)
747  Modified |= ExpandMBB(MBB);
748  return Modified;
749 }
750 
751 /// Returns an instance of the pseudo instruction expansion pass.
753  return new X86ExpandPseudo();
754 }
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:739
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:387
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:591
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
X86Subtarget.h
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
X86InstrBuilder.h
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:300
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:150
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::MachineFunction::moveCallSiteInfo
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
Definition: MachineFunction.cpp:954
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:340
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
EHPersonalities.h
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:873
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:549
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:127
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::addLiveIns
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs)
Adds registers contained in LiveRegs to the block live-in list of MBB.
Definition: LivePhysRegs.cpp:259
llvm::X86ISD::VASTART_SAVE_XMM_REGS
@ VASTART_SAVE_XMM_REGS
Definition: X86ISelLowering.h:894
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:609
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:836
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
X86FrameLowering.h
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::finalizeBundle
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
Definition: MachineInstrBundle.cpp:124
X86MachineFunctionInfo.h
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
X86.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
GlobalValue.h
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1476
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1347
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
INITIALIZE_PASS
INITIALIZE_PASS(X86ExpandPseudo, DEBUG_TYPE, X86_EXPAND_PSEUDO_NAME, false, false) void X86ExpandPseudo
Definition: X86ExpandPseudo.cpp:87
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:196
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
LoopDeletionResult::Modified
@ Modified
llvm::X86ISD::IRET
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
Definition: X86ISelLowering.h:134
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:43
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:421
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:419
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::X86FrameLowering
Definition: X86FrameLowering.h:28
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86::COND_B
@ COND_B
Definition: X86BaseInfo.h:83
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::createX86ExpandPseudoPass
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
Definition: X86ExpandPseudo.cpp:752
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineFunction
Definition: MachineFunction.h:257
FirstTarget
static Target * FirstTarget
Definition: TargetRegistry.cpp:18
llvm::X86InstrInfo
Definition: X86InstrInfo.h:138
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:265
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
uint32_t
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ifs::IFSSymbolType::Func
@ Func
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86ExpandPseudo.cpp:30
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:284
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
X86_EXPAND_PSEUDO_NAME
#define X86_EXPAND_PSEUDO_NAME
Definition: X86ExpandPseudo.cpp:31
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:617
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:192
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:131
llvm::MachineInstr::setCFIType
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
Definition: MachineInstr.cpp:510
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:901
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1141
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.h:224
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
X86InstrInfo.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::X86::COND_E
@ COND_E
Definition: X86BaseInfo.h:85
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:855
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:482
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:338
LivePhysRegs.h