LLVM  13.0.0git
X86ExpandPseudo.cpp
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1 //===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling, if-conversion, other late
11 // optimizations, or simply the encoding of the instructions.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86.h"
16 #include "X86FrameLowering.h"
17 #include "X86InstrBuilder.h"
18 #include "X86InstrInfo.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
24 #include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
25 #include "llvm/IR/GlobalValue.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "x86-pseudo"
29 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
30 
31 namespace {
32 class X86ExpandPseudo : public MachineFunctionPass {
33 public:
34  static char ID;
35  X86ExpandPseudo() : MachineFunctionPass(ID) {}
36 
37  void getAnalysisUsage(AnalysisUsage &AU) const override {
38  AU.setPreservesCFG();
42  }
43 
44  const X86Subtarget *STI = nullptr;
45  const X86InstrInfo *TII = nullptr;
46  const X86RegisterInfo *TRI = nullptr;
47  const X86MachineFunctionInfo *X86FI = nullptr;
48  const X86FrameLowering *X86FL = nullptr;
49 
50  bool runOnMachineFunction(MachineFunction &Fn) override;
51 
52  MachineFunctionProperties getRequiredProperties() const override {
55  }
56 
57  StringRef getPassName() const override {
58  return "X86 pseudo instruction expansion pass";
59  }
60 
61 private:
62  void ExpandICallBranchFunnel(MachineBasicBlock *MBB,
64 
66  bool ExpandMBB(MachineBasicBlock &MBB);
67 
68  /// This function expands pseudos which affects control flow.
69  /// It is done in separate pass to simplify blocks navigation in main
70  /// pass(calling ExpandMBB).
71  bool ExpandPseudosWhichAffectControlFlow(MachineFunction &MF);
72 
73  /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
74  /// placed into separate block guarded by check for al register(for SystemV
75  /// abi).
76  void ExpandVastartSaveXmmRegs(
78  MachineBasicBlock::iterator VAStartPseudoInstr) const;
79 };
80 char X86ExpandPseudo::ID = 0;
81 
82 } // End anonymous namespace.
83 
85  false)
86 
87 void X86ExpandPseudo::ExpandICallBranchFunnel(
89  MachineBasicBlock *JTMBB = MBB;
90  MachineInstr *JTInst = &*MBBI;
91  MachineFunction *MF = MBB->getParent();
92  const BasicBlock *BB = MBB->getBasicBlock();
93  auto InsPt = MachineFunction::iterator(MBB);
94  ++InsPt;
95 
96  std::vector<std::pair<MachineBasicBlock *, unsigned>> TargetMBBs;
97  DebugLoc DL = JTInst->getDebugLoc();
98  MachineOperand Selector = JTInst->getOperand(0);
99  const GlobalValue *CombinedGlobal = JTInst->getOperand(1).getGlobal();
100 
101  auto CmpTarget = [&](unsigned Target) {
102  if (Selector.isReg())
103  MBB->addLiveIn(Selector.getReg());
104  BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
105  .addReg(X86::RIP)
106  .addImm(1)
107  .addReg(0)
108  .addGlobalAddress(CombinedGlobal,
109  JTInst->getOperand(2 + 2 * Target).getImm())
110  .addReg(0);
111  BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
112  .add(Selector)
113  .addReg(X86::R11);
114  };
115 
116  auto CreateMBB = [&]() {
117  auto *NewMBB = MF->CreateMachineBasicBlock(BB);
118  MBB->addSuccessor(NewMBB);
119  if (!MBB->isLiveIn(X86::EFLAGS))
120  MBB->addLiveIn(X86::EFLAGS);
121  return NewMBB;
122  };
123 
124  auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
125  BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
126 
127  auto *ElseMBB = CreateMBB();
128  MF->insert(InsPt, ElseMBB);
129  MBB = ElseMBB;
130  MBBI = MBB->end();
131  };
132 
133  auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
134  auto *ThenMBB = CreateMBB();
135  TargetMBBs.push_back({ThenMBB, Target});
136  EmitCondJump(CC, ThenMBB);
137  };
138 
139  auto EmitTailCall = [&](unsigned Target) {
140  BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64))
141  .add(JTInst->getOperand(3 + 2 * Target));
142  };
143 
144  std::function<void(unsigned, unsigned)> EmitBranchFunnel =
145  [&](unsigned FirstTarget, unsigned NumTargets) {
146  if (NumTargets == 1) {
147  EmitTailCall(FirstTarget);
148  return;
149  }
150 
151  if (NumTargets == 2) {
152  CmpTarget(FirstTarget + 1);
153  EmitCondJumpTarget(X86::COND_B, FirstTarget);
154  EmitTailCall(FirstTarget + 1);
155  return;
156  }
157 
158  if (NumTargets < 6) {
159  CmpTarget(FirstTarget + 1);
160  EmitCondJumpTarget(X86::COND_B, FirstTarget);
161  EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
162  EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
163  return;
164  }
165 
166  auto *ThenMBB = CreateMBB();
167  CmpTarget(FirstTarget + (NumTargets / 2));
168  EmitCondJump(X86::COND_B, ThenMBB);
169  EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
170  EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
171  NumTargets - (NumTargets / 2) - 1);
172 
173  MF->insert(InsPt, ThenMBB);
174  MBB = ThenMBB;
175  MBBI = MBB->end();
176  EmitBranchFunnel(FirstTarget, NumTargets / 2);
177  };
178 
179  EmitBranchFunnel(0, (JTInst->getNumOperands() - 2) / 2);
180  for (auto P : TargetMBBs) {
181  MF->insert(InsPt, P.first);
182  BuildMI(P.first, DL, TII->get(X86::TAILJMPd64))
183  .add(JTInst->getOperand(3 + 2 * P.second));
184  }
185  JTMBB->erase(JTInst);
186 }
187 
188 /// If \p MBBI is a pseudo instruction, this method expands
189 /// it to the corresponding (sequence of) actual instruction(s).
190 /// \returns true if \p MBBI has been expanded.
191 bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
193  MachineInstr &MI = *MBBI;
194  unsigned Opcode = MI.getOpcode();
195  DebugLoc DL = MBBI->getDebugLoc();
196  switch (Opcode) {
197  default:
198  return false;
199  case X86::TCRETURNdi:
200  case X86::TCRETURNdicc:
201  case X86::TCRETURNri:
202  case X86::TCRETURNmi:
203  case X86::TCRETURNdi64:
204  case X86::TCRETURNdi64cc:
205  case X86::TCRETURNri64:
206  case X86::TCRETURNmi64: {
207  bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
208  MachineOperand &JumpTarget = MBBI->getOperand(0);
209  MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands
210  : 1);
211  assert(StackAdjust.isImm() && "Expecting immediate value.");
212 
213  // Adjust stack pointer.
214  int StackAdj = StackAdjust.getImm();
215  int MaxTCDelta = X86FI->getTCReturnAddrDelta();
216  int Offset = 0;
217  assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
218 
219  // Incoporate the retaddr area.
220  Offset = StackAdj - MaxTCDelta;
221  assert(Offset >= 0 && "Offset should never be negative");
222 
223  if (Opcode == X86::TCRETURNdicc || Opcode == X86::TCRETURNdi64cc) {
224  assert(Offset == 0 && "Conditional tail call cannot adjust the stack.");
225  }
226 
227  if (Offset) {
228  // Check for possible merge with preceding ADD instruction.
229  Offset += X86FL->mergeSPUpdates(MBB, MBBI, true);
230  X86FL->emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue=*/true);
231  }
232 
233  // Jump to label or value in register.
234  bool IsWin64 = STI->isTargetWin64();
235  if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdicc ||
236  Opcode == X86::TCRETURNdi64 || Opcode == X86::TCRETURNdi64cc) {
237  unsigned Op;
238  switch (Opcode) {
239  case X86::TCRETURNdi:
240  Op = X86::TAILJMPd;
241  break;
242  case X86::TCRETURNdicc:
243  Op = X86::TAILJMPd_CC;
244  break;
245  case X86::TCRETURNdi64cc:
246  assert(!MBB.getParent()->hasWinCFI() &&
247  "Conditional tail calls confuse "
248  "the Win64 unwinder.");
249  Op = X86::TAILJMPd64_CC;
250  break;
251  default:
252  // Note: Win64 uses REX prefixes indirect jumps out of functions, but
253  // not direct ones.
254  Op = X86::TAILJMPd64;
255  break;
256  }
257  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
258  if (JumpTarget.isGlobal()) {
259  MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
260  JumpTarget.getTargetFlags());
261  } else {
262  assert(JumpTarget.isSymbol());
263  MIB.addExternalSymbol(JumpTarget.getSymbolName(),
264  JumpTarget.getTargetFlags());
265  }
266  if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) {
267  MIB.addImm(MBBI->getOperand(2).getImm());
268  }
269 
270  } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
271  unsigned Op = (Opcode == X86::TCRETURNmi)
272  ? X86::TAILJMPm
273  : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
274  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
275  for (unsigned i = 0; i != X86::AddrNumOperands; ++i)
276  MIB.add(MBBI->getOperand(i));
277  } else if (Opcode == X86::TCRETURNri64) {
278  JumpTarget.setIsKill();
279  BuildMI(MBB, MBBI, DL,
280  TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
281  .add(JumpTarget);
282  } else {
283  JumpTarget.setIsKill();
284  BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
285  .add(JumpTarget);
286  }
287 
288  MachineInstr &NewMI = *std::prev(MBBI);
289  NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
290 
291  // Update the call site info.
292  if (MBBI->isCandidateForCallSiteEntry())
293  MBB.getParent()->moveCallSiteInfo(&*MBBI, &NewMI);
294 
295  // Delete the pseudo instruction TCRETURN.
296  MBB.erase(MBBI);
297 
298  return true;
299  }
300  case X86::EH_RETURN:
301  case X86::EH_RETURN64: {
302  MachineOperand &DestAddr = MBBI->getOperand(0);
303  assert(DestAddr.isReg() && "Offset should be in register!");
304  const bool Uses64BitFramePtr =
305  STI->isTarget64BitLP64() || STI->isTargetNaCl64();
306  Register StackPtr = TRI->getStackRegister();
307  BuildMI(MBB, MBBI, DL,
308  TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
309  .addReg(DestAddr.getReg());
310  // The EH_RETURN pseudo is really removed during the MC Lowering.
311  return true;
312  }
313  case X86::IRET: {
314  // Adjust stack to erase error code
315  int64_t StackAdj = MBBI->getOperand(0).getImm();
316  X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true);
317  // Replace pseudo with machine iret
318  BuildMI(MBB, MBBI, DL,
319  TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));
320  MBB.erase(MBBI);
321  return true;
322  }
323  case X86::RET: {
324  // Adjust stack to erase error code
325  int64_t StackAdj = MBBI->getOperand(0).getImm();
327  if (StackAdj == 0) {
328  MIB = BuildMI(MBB, MBBI, DL,
329  TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL));
330  } else if (isUInt<16>(StackAdj)) {
331  MIB = BuildMI(MBB, MBBI, DL,
332  TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL))
333  .addImm(StackAdj);
334  } else {
335  assert(!STI->is64Bit() &&
336  "shouldn't need to do this for x86_64 targets!");
337  // A ret can only handle immediates as big as 2**16-1. If we need to pop
338  // off bytes before the return address, we must do it manually.
339  BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
340  X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true);
341  BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
342  MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
343  }
344  for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
345  MIB.add(MBBI->getOperand(I));
346  MBB.erase(MBBI);
347  return true;
348  }
349  case X86::LCMPXCHG16B_SAVE_RBX: {
350  // Perform the following transformation.
351  // SaveRbx = pseudocmpxchg Addr, <4 opds for the address>, InArg, SaveRbx
352  // =>
353  // RBX = InArg
354  // actualcmpxchg Addr
355  // RBX = SaveRbx
356  const MachineOperand &InArg = MBBI->getOperand(6);
357  Register SaveRbx = MBBI->getOperand(7).getReg();
358 
359  // Copy the input argument of the pseudo into the argument of the
360  // actual instruction.
361  // NOTE: We don't copy the kill flag since the input might be the same reg
362  // as one of the other operands of LCMPXCHG16B.
363  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, InArg.getReg(), false);
364  // Create the actual instruction.
365  MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(X86::LCMPXCHG16B));
366  // Copy the operands related to the address.
367  for (unsigned Idx = 1; Idx < 6; ++Idx)
368  NewInstr->addOperand(MBBI->getOperand(Idx));
369  // Finally, restore the value of RBX.
370  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx,
371  /*SrcIsKill*/ true);
372 
373  // Delete the pseudo.
375  return true;
376  }
377  // Loading/storing mask pairs requires two kmov operations. The second one of
378  // these needs a 2 byte displacement relative to the specified address (with
379  // 32 bit spill size). The pairs of 1bit masks up to 16 bit masks all use the
380  // same spill size, they all are stored using MASKPAIR16STORE, loaded using
381  // MASKPAIR16LOAD.
382  //
383  // The displacement value might wrap around in theory, thus the asserts in
384  // both cases.
385  case X86::MASKPAIR16LOAD: {
386  int64_t Disp = MBBI->getOperand(1 + X86::AddrDisp).getImm();
387  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
388  Register Reg = MBBI->getOperand(0).getReg();
389  bool DstIsDead = MBBI->getOperand(0).isDead();
390  Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
391  Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
392 
393  auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
394  .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead));
395  auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
396  .addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead));
397 
398  for (int i = 0; i < X86::AddrNumOperands; ++i) {
399  MIBLo.add(MBBI->getOperand(1 + i));
400  if (i == X86::AddrDisp)
401  MIBHi.addImm(Disp + 2);
402  else
403  MIBHi.add(MBBI->getOperand(1 + i));
404  }
405 
406  // Split the memory operand, adjusting the offset and size for the halves.
407  MachineMemOperand *OldMMO = MBBI->memoperands().front();
408  MachineFunction *MF = MBB.getParent();
409  MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
410  MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
411 
412  MIBLo.setMemRefs(MMOLo);
413  MIBHi.setMemRefs(MMOHi);
414 
415  // Delete the pseudo.
416  MBB.erase(MBBI);
417  return true;
418  }
419  case X86::MASKPAIR16STORE: {
420  int64_t Disp = MBBI->getOperand(X86::AddrDisp).getImm();
421  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
422  Register Reg = MBBI->getOperand(X86::AddrNumOperands).getReg();
423  bool SrcIsKill = MBBI->getOperand(X86::AddrNumOperands).isKill();
424  Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
425  Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
426 
427  auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
428  auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
429 
430  for (int i = 0; i < X86::AddrNumOperands; ++i) {
431  MIBLo.add(MBBI->getOperand(i));
432  if (i == X86::AddrDisp)
433  MIBHi.addImm(Disp + 2);
434  else
435  MIBHi.add(MBBI->getOperand(i));
436  }
437  MIBLo.addReg(Reg0, getKillRegState(SrcIsKill));
438  MIBHi.addReg(Reg1, getKillRegState(SrcIsKill));
439 
440  // Split the memory operand, adjusting the offset and size for the halves.
441  MachineMemOperand *OldMMO = MBBI->memoperands().front();
442  MachineFunction *MF = MBB.getParent();
443  MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
444  MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
445 
446  MIBLo.setMemRefs(MMOLo);
447  MIBHi.setMemRefs(MMOHi);
448 
449  // Delete the pseudo.
450  MBB.erase(MBBI);
451  return true;
452  }
453  case X86::MWAITX_SAVE_RBX: {
454  // Perform the following transformation.
455  // SaveRbx = pseudomwaitx InArg, SaveRbx
456  // =>
457  // [E|R]BX = InArg
458  // actualmwaitx
459  // [E|R]BX = SaveRbx
460  const MachineOperand &InArg = MBBI->getOperand(1);
461  // Copy the input argument of the pseudo into the argument of the
462  // actual instruction.
463  TII->copyPhysReg(MBB, MBBI, DL, X86::EBX, InArg.getReg(), InArg.isKill());
464  // Create the actual instruction.
465  BuildMI(MBB, MBBI, DL, TII->get(X86::MWAITXrrr));
466  // Finally, restore the value of RBX.
467  Register SaveRbx = MBBI->getOperand(2).getReg();
468  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, /*SrcIsKill*/ true);
469  // Delete the pseudo.
471  return true;
472  }
473  case TargetOpcode::ICALL_BRANCH_FUNNEL:
474  ExpandICallBranchFunnel(&MBB, MBBI);
475  return true;
476  case X86::PTILELOADDV: {
477  for (unsigned i = 2; i > 0; --i)
478  MI.RemoveOperand(i);
479  MI.setDesc(TII->get(X86::TILELOADD));
480  return true;
481  }
482  case X86::PTDPBSSDV:
483  case X86::PTDPBSUDV:
484  case X86::PTDPBUSDV:
485  case X86::PTDPBUUDV:
486  case X86::PTDPBF16PSV: {
487  MI.untieRegOperand(4);
488  for (unsigned i = 3; i > 0; --i)
489  MI.RemoveOperand(i);
490  unsigned Opc;
491  switch (Opcode) {
492  case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break;
493  case X86::PTDPBSUDV: Opc = X86::TDPBSUD; break;
494  case X86::PTDPBUSDV: Opc = X86::TDPBUSD; break;
495  case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break;
496  case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break;
497  default: llvm_unreachable("Impossible Opcode!");
498  }
499  MI.setDesc(TII->get(Opc));
500  MI.tieOperands(0, 1);
501  return true;
502  }
503  case X86::PTILESTOREDV: {
504  for (int i = 1; i >= 0; --i)
505  MI.RemoveOperand(i);
506  MI.setDesc(TII->get(X86::TILESTORED));
507  return true;
508  }
509  case X86::PTILEZEROV: {
510  for (int i = 2; i > 0; --i) // Remove row, col
511  MI.RemoveOperand(i);
512  MI.setDesc(TII->get(X86::TILEZERO));
513  return true;
514  }
515  }
516  llvm_unreachable("Previous switch has a fallthrough?");
517 }
518 
519 // This function creates additional block for storing varargs guarded
520 // registers. It adds check for %al into entry block, to skip
521 // GuardedRegsBlk if xmm registers should not be stored.
522 //
523 // EntryBlk[VAStartPseudoInstr] EntryBlk
524 // | | .
525 // | | .
526 // | | GuardedRegsBlk
527 // | => | .
528 // | | .
529 // | TailBlk
530 // | |
531 // | |
532 //
533 void X86ExpandPseudo::ExpandVastartSaveXmmRegs(
534  MachineBasicBlock *EntryBlk,
535  MachineBasicBlock::iterator VAStartPseudoInstr) const {
536  assert(VAStartPseudoInstr->getOpcode() == X86::VASTART_SAVE_XMM_REGS);
537 
538  MachineFunction *Func = EntryBlk->getParent();
539  const TargetInstrInfo *TII = STI->getInstrInfo();
540  DebugLoc DL = VAStartPseudoInstr->getDebugLoc();
541  Register CountReg = VAStartPseudoInstr->getOperand(0).getReg();
542 
543  // Calculate liveins for newly created blocks.
544  LivePhysRegs LiveRegs(*STI->getRegisterInfo());
546 
547  LiveRegs.addLiveIns(*EntryBlk);
548  for (MachineInstr &MI : EntryBlk->instrs()) {
549  if (MI.getOpcode() == VAStartPseudoInstr->getOpcode())
550  break;
551 
552  LiveRegs.stepForward(MI, Clobbers);
553  }
554 
555  // Create the new basic blocks. One block contains all the XMM stores,
556  // and another block is the final destination regardless of whether any
557  // stores were performed.
558  const BasicBlock *LLVMBlk = EntryBlk->getBasicBlock();
559  MachineFunction::iterator EntryBlkIter = ++EntryBlk->getIterator();
560  MachineBasicBlock *GuardedRegsBlk = Func->CreateMachineBasicBlock(LLVMBlk);
561  MachineBasicBlock *TailBlk = Func->CreateMachineBasicBlock(LLVMBlk);
562  Func->insert(EntryBlkIter, GuardedRegsBlk);
563  Func->insert(EntryBlkIter, TailBlk);
564 
565  // Transfer the remainder of EntryBlk and its successor edges to TailBlk.
566  TailBlk->splice(TailBlk->begin(), EntryBlk,
567  std::next(MachineBasicBlock::iterator(VAStartPseudoInstr)),
568  EntryBlk->end());
569  TailBlk->transferSuccessorsAndUpdatePHIs(EntryBlk);
570 
571  int64_t FrameIndex = VAStartPseudoInstr->getOperand(1).getImm();
572  Register BaseReg;
573  uint64_t FrameOffset =
574  X86FL->getFrameIndexReference(*Func, FrameIndex, BaseReg).getFixed();
575  uint64_t VarArgsRegsOffset = VAStartPseudoInstr->getOperand(2).getImm();
576 
577  // TODO: add support for YMM and ZMM here.
578  unsigned MOVOpc = STI->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
579 
580  // In the XMM save block, save all the XMM argument registers.
581  for (int64_t OpndIdx = 3, RegIdx = 0;
582  OpndIdx < VAStartPseudoInstr->getNumOperands() - 1;
583  OpndIdx++, RegIdx++) {
584 
585  int64_t Offset = FrameOffset + VarArgsRegsOffset + RegIdx * 16;
586 
587  MachineMemOperand *MMO = Func->getMachineMemOperand(
590  /*Size=*/16, Align(16));
591 
592  BuildMI(GuardedRegsBlk, DL, TII->get(MOVOpc))
593  .addReg(BaseReg)
594  .addImm(/*Scale=*/1)
595  .addReg(/*IndexReg=*/0)
596  .addImm(/*Disp=*/Offset)
597  .addReg(/*Segment=*/0)
598  .addReg(VAStartPseudoInstr->getOperand(OpndIdx).getReg())
599  .addMemOperand(MMO);
601  VAStartPseudoInstr->getOperand(OpndIdx).getReg()));
602  }
603 
604  // The original block will now fall through to the GuardedRegsBlk.
605  EntryBlk->addSuccessor(GuardedRegsBlk);
606  // The GuardedRegsBlk will fall through to the TailBlk.
607  GuardedRegsBlk->addSuccessor(TailBlk);
608 
609  if (!STI->isCallingConvWin64(Func->getFunction().getCallingConv())) {
610  // If %al is 0, branch around the XMM save block.
611  BuildMI(EntryBlk, DL, TII->get(X86::TEST8rr))
612  .addReg(CountReg)
613  .addReg(CountReg);
614  BuildMI(EntryBlk, DL, TII->get(X86::JCC_1))
615  .addMBB(TailBlk)
617  EntryBlk->addSuccessor(TailBlk);
618  }
619 
620  // Add liveins to the created block.
621  addLiveIns(*GuardedRegsBlk, LiveRegs);
622  addLiveIns(*TailBlk, LiveRegs);
623 
624  // Delete the pseudo.
625  VAStartPseudoInstr->eraseFromParent();
626 }
627 
628 /// Expand all pseudo instructions contained in \p MBB.
629 /// \returns true if any expansion occurred for \p MBB.
630 bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
631  bool Modified = false;
632 
633  // MBBI may be invalidated by the expansion.
635  while (MBBI != E) {
636  MachineBasicBlock::iterator NMBBI = std::next(MBBI);
637  Modified |= ExpandMI(MBB, MBBI);
638  MBBI = NMBBI;
639  }
640 
641  return Modified;
642 }
643 
644 bool X86ExpandPseudo::ExpandPseudosWhichAffectControlFlow(MachineFunction &MF) {
645  // Currently pseudo which affects control flow is only
646  // X86::VASTART_SAVE_XMM_REGS which is located in Entry block.
647  // So we do not need to evaluate other blocks.
648  for (MachineInstr &Instr : MF.front().instrs()) {
649  if (Instr.getOpcode() == X86::VASTART_SAVE_XMM_REGS) {
650  ExpandVastartSaveXmmRegs(&(MF.front()), Instr);
651  return true;
652  }
653  }
654 
655  return false;
656 }
657 
658 bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
659  STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
660  TII = STI->getInstrInfo();
661  TRI = STI->getRegisterInfo();
662  X86FI = MF.getInfo<X86MachineFunctionInfo>();
663  X86FL = STI->getFrameLowering();
664 
665  bool Modified = ExpandPseudosWhichAffectControlFlow(MF);
666 
667  for (MachineBasicBlock &MBB : MF)
668  Modified |= ExpandMBB(MBB);
669  return Modified;
670 }
671 
672 /// Returns an instance of the pseudo instruction expansion pass.
674  return new X86ExpandPseudo();
675 }
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:637
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:572
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
X86Subtarget.h
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:560
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
X86InstrBuilder.h
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:263
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:497
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::MachineFunction::moveCallSiteInfo
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
Definition: MachineFunction.cpp:929
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:338
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
EHPersonalities.h
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:756
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:512
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::addLiveIns
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs)
Adds registers contained in LiveRegs to the block live-in list of MBB.
Definition: LivePhysRegs.cpp:253
llvm::X86ISD::VASTART_SAVE_XMM_REGS
@ VASTART_SAVE_XMM_REGS
Definition: X86ISelLowering.h:628
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:597
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:719
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1322
X86FrameLowering.h
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:743
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:387
X86MachineFunctionInfo.h
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:749
X86.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
GlobalValue.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:147
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1488
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1355
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
INITIALIZE_PASS
INITIALIZE_PASS(X86ExpandPseudo, DEBUG_TYPE, X86_EXPAND_PSEUDO_NAME, false, false) void X86ExpandPseudo
Definition: X86ExpandPseudo.cpp:84
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:166
LoopDeletionResult::Modified
@ Modified
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:45
llvm::X86ISD::IRET
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
Definition: X86ISelLowering.h:129
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:185
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:43
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:218
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::X86FrameLowering
Definition: X86FrameLowering.h:27
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:414
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::elfabi::ELFSymbolType::Func
@ Func
llvm::X86::COND_B
@ COND_B
Definition: X86BaseInfo.h:83
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:203
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::createX86ExpandPseudoPass
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
Definition: X86ExpandPseudo.cpp:673
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::MachineFunction
Definition: MachineFunction.h:227
FirstTarget
static Target * FirstTarget
Definition: TargetRegistry.cpp:18
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:859
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86ExpandPseudo.cpp:28
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:128
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:178
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:509
X86_EXPAND_PSEUDO_NAME
#define X86_EXPAND_PSEUDO_NAME
Definition: X86ExpandPseudo.cpp:29
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:605
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:481
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:123
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:882
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1078
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
X86InstrInfo.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::X86::COND_E
@ COND_E
Definition: X86BaseInfo.h:85
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:812
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:336
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38