LLVM  14.0.0git
X86ExpandPseudo.cpp
Go to the documentation of this file.
1 //===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling, if-conversion, other late
11 // optimizations, or simply the encoding of the instructions.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86.h"
16 #include "X86FrameLowering.h"
17 #include "X86InstrBuilder.h"
18 #include "X86InstrInfo.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
24 #include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
25 #include "llvm/IR/GlobalValue.h"
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "x86-pseudo"
30 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
31 
32 namespace {
33 class X86ExpandPseudo : public MachineFunctionPass {
34 public:
35  static char ID;
36  X86ExpandPseudo() : MachineFunctionPass(ID) {}
37 
38  void getAnalysisUsage(AnalysisUsage &AU) const override {
39  AU.setPreservesCFG();
43  }
44 
45  const X86Subtarget *STI = nullptr;
46  const X86InstrInfo *TII = nullptr;
47  const X86RegisterInfo *TRI = nullptr;
48  const X86MachineFunctionInfo *X86FI = nullptr;
49  const X86FrameLowering *X86FL = nullptr;
50 
51  bool runOnMachineFunction(MachineFunction &Fn) override;
52 
53  MachineFunctionProperties getRequiredProperties() const override {
56  }
57 
58  StringRef getPassName() const override {
59  return "X86 pseudo instruction expansion pass";
60  }
61 
62 private:
63  void ExpandICallBranchFunnel(MachineBasicBlock *MBB,
65  void expandCALL_RVMARKER(MachineBasicBlock &MBB,
68  bool ExpandMBB(MachineBasicBlock &MBB);
69 
70  /// This function expands pseudos which affects control flow.
71  /// It is done in separate pass to simplify blocks navigation in main
72  /// pass(calling ExpandMBB).
73  bool ExpandPseudosWhichAffectControlFlow(MachineFunction &MF);
74 
75  /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
76  /// placed into separate block guarded by check for al register(for SystemV
77  /// abi).
78  void ExpandVastartSaveXmmRegs(
80  MachineBasicBlock::iterator VAStartPseudoInstr) const;
81 };
82 char X86ExpandPseudo::ID = 0;
83 
84 } // End anonymous namespace.
85 
87  false)
88 
89 void X86ExpandPseudo::ExpandICallBranchFunnel(
91  MachineBasicBlock *JTMBB = MBB;
92  MachineInstr *JTInst = &*MBBI;
93  MachineFunction *MF = MBB->getParent();
94  const BasicBlock *BB = MBB->getBasicBlock();
95  auto InsPt = MachineFunction::iterator(MBB);
96  ++InsPt;
97 
98  std::vector<std::pair<MachineBasicBlock *, unsigned>> TargetMBBs;
99  const DebugLoc &DL = JTInst->getDebugLoc();
100  MachineOperand Selector = JTInst->getOperand(0);
101  const GlobalValue *CombinedGlobal = JTInst->getOperand(1).getGlobal();
102 
103  auto CmpTarget = [&](unsigned Target) {
104  if (Selector.isReg())
105  MBB->addLiveIn(Selector.getReg());
106  BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
107  .addReg(X86::RIP)
108  .addImm(1)
109  .addReg(0)
110  .addGlobalAddress(CombinedGlobal,
111  JTInst->getOperand(2 + 2 * Target).getImm())
112  .addReg(0);
113  BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
114  .add(Selector)
115  .addReg(X86::R11);
116  };
117 
118  auto CreateMBB = [&]() {
119  auto *NewMBB = MF->CreateMachineBasicBlock(BB);
120  MBB->addSuccessor(NewMBB);
121  if (!MBB->isLiveIn(X86::EFLAGS))
122  MBB->addLiveIn(X86::EFLAGS);
123  return NewMBB;
124  };
125 
126  auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
127  BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
128 
129  auto *ElseMBB = CreateMBB();
130  MF->insert(InsPt, ElseMBB);
131  MBB = ElseMBB;
132  MBBI = MBB->end();
133  };
134 
135  auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
136  auto *ThenMBB = CreateMBB();
137  TargetMBBs.push_back({ThenMBB, Target});
138  EmitCondJump(CC, ThenMBB);
139  };
140 
141  auto EmitTailCall = [&](unsigned Target) {
142  BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64))
143  .add(JTInst->getOperand(3 + 2 * Target));
144  };
145 
146  std::function<void(unsigned, unsigned)> EmitBranchFunnel =
147  [&](unsigned FirstTarget, unsigned NumTargets) {
148  if (NumTargets == 1) {
149  EmitTailCall(FirstTarget);
150  return;
151  }
152 
153  if (NumTargets == 2) {
154  CmpTarget(FirstTarget + 1);
155  EmitCondJumpTarget(X86::COND_B, FirstTarget);
156  EmitTailCall(FirstTarget + 1);
157  return;
158  }
159 
160  if (NumTargets < 6) {
161  CmpTarget(FirstTarget + 1);
162  EmitCondJumpTarget(X86::COND_B, FirstTarget);
163  EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
164  EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
165  return;
166  }
167 
168  auto *ThenMBB = CreateMBB();
169  CmpTarget(FirstTarget + (NumTargets / 2));
170  EmitCondJump(X86::COND_B, ThenMBB);
171  EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
172  EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
173  NumTargets - (NumTargets / 2) - 1);
174 
175  MF->insert(InsPt, ThenMBB);
176  MBB = ThenMBB;
177  MBBI = MBB->end();
178  EmitBranchFunnel(FirstTarget, NumTargets / 2);
179  };
180 
181  EmitBranchFunnel(0, (JTInst->getNumOperands() - 2) / 2);
182  for (auto P : TargetMBBs) {
183  MF->insert(InsPt, P.first);
184  BuildMI(P.first, DL, TII->get(X86::TAILJMPd64))
185  .add(JTInst->getOperand(3 + 2 * P.second));
186  }
187  JTMBB->erase(JTInst);
188 }
189 
190 void X86ExpandPseudo::expandCALL_RVMARKER(MachineBasicBlock &MBB,
192  // Expand CALL_RVMARKER pseudo to call instruction, followed by the special
193  //"movq %rax, %rdi" marker.
194  // TODO: Mark the sequence as bundle, to avoid passes moving other code
195  // in between.
196  MachineInstr &MI = *MBBI;
197 
198  MachineInstr *OriginalCall;
199  assert((MI.getOperand(1).isGlobal() || MI.getOperand(1).isReg()) &&
200  "invalid operand for regular call");
201  unsigned Opc = -1;
202  if (MI.getOpcode() == X86::CALL64m_RVMARKER)
203  Opc = X86::CALL64m;
204  else if (MI.getOpcode() == X86::CALL64r_RVMARKER)
205  Opc = X86::CALL64r;
206  else if (MI.getOpcode() == X86::CALL64pcrel32_RVMARKER)
207  Opc = X86::CALL64pcrel32;
208  else
209  llvm_unreachable("unexpected opcode");
210 
211  OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr();
212  unsigned OpStart = 1;
213  bool RAXImplicitDead = false;
214  for (; OpStart < MI.getNumOperands(); ++OpStart) {
215  MachineOperand &Op = MI.getOperand(OpStart);
216  // RAX may be 'implicit dead', if there are no other users of the return
217  // value. We introduce a new use, so change it to 'implicit def'.
218  if (Op.isReg() && Op.isImplicit() && Op.isDead() &&
219  TRI->regsOverlap(Op.getReg(), X86::RAX)) {
220  Op.setIsDead(false);
221  Op.setIsDef(true);
222  RAXImplicitDead = true;
223  }
224  OriginalCall->addOperand(Op);
225  }
226 
227  // Emit marker "movq %rax, %rdi". %rdi is not callee-saved, so it cannot be
228  // live across the earlier call. The call to the ObjC runtime function returns
229  // the first argument, so the value of %rax is unchanged after the ObjC
230  // runtime call.
231  auto *Marker = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::MOV64rr))
232  .addReg(X86::RDI, RegState::Define)
233  .addReg(X86::RAX)
234  .getInstr();
235  if (MI.shouldUpdateCallSiteInfo())
236  MBB.getParent()->moveCallSiteInfo(&MI, Marker);
237 
238  // Emit call to ObjC runtime.
239  const uint32_t *RegMask =
241  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::CALL64pcrel32))
242  .addGlobalAddress(MI.getOperand(0).getGlobal(), 0, 0)
243  .addRegMask(RegMask)
244  .addReg(X86::RAX,
246  (RAXImplicitDead ? (RegState::Dead | RegState::Define)
247  : RegState::Define))
248  .getInstr();
249  MI.eraseFromParent();
250 }
251 
252 /// If \p MBBI is a pseudo instruction, this method expands
253 /// it to the corresponding (sequence of) actual instruction(s).
254 /// \returns true if \p MBBI has been expanded.
255 bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
257  MachineInstr &MI = *MBBI;
258  unsigned Opcode = MI.getOpcode();
259  const DebugLoc &DL = MBBI->getDebugLoc();
260  switch (Opcode) {
261  default:
262  return false;
263  case X86::TCRETURNdi:
264  case X86::TCRETURNdicc:
265  case X86::TCRETURNri:
266  case X86::TCRETURNmi:
267  case X86::TCRETURNdi64:
268  case X86::TCRETURNdi64cc:
269  case X86::TCRETURNri64:
270  case X86::TCRETURNmi64: {
271  bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
272  MachineOperand &JumpTarget = MBBI->getOperand(0);
273  MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands
274  : 1);
275  assert(StackAdjust.isImm() && "Expecting immediate value.");
276 
277  // Adjust stack pointer.
278  int StackAdj = StackAdjust.getImm();
279  int MaxTCDelta = X86FI->getTCReturnAddrDelta();
280  int Offset = 0;
281  assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
282 
283  // Incoporate the retaddr area.
284  Offset = StackAdj - MaxTCDelta;
285  assert(Offset >= 0 && "Offset should never be negative");
286 
287  if (Opcode == X86::TCRETURNdicc || Opcode == X86::TCRETURNdi64cc) {
288  assert(Offset == 0 && "Conditional tail call cannot adjust the stack.");
289  }
290 
291  if (Offset) {
292  // Check for possible merge with preceding ADD instruction.
293  Offset += X86FL->mergeSPUpdates(MBB, MBBI, true);
294  X86FL->emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue=*/true);
295  }
296 
297  // Jump to label or value in register.
298  bool IsWin64 = STI->isTargetWin64();
299  if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdicc ||
300  Opcode == X86::TCRETURNdi64 || Opcode == X86::TCRETURNdi64cc) {
301  unsigned Op;
302  switch (Opcode) {
303  case X86::TCRETURNdi:
304  Op = X86::TAILJMPd;
305  break;
306  case X86::TCRETURNdicc:
307  Op = X86::TAILJMPd_CC;
308  break;
309  case X86::TCRETURNdi64cc:
310  assert(!MBB.getParent()->hasWinCFI() &&
311  "Conditional tail calls confuse "
312  "the Win64 unwinder.");
313  Op = X86::TAILJMPd64_CC;
314  break;
315  default:
316  // Note: Win64 uses REX prefixes indirect jumps out of functions, but
317  // not direct ones.
318  Op = X86::TAILJMPd64;
319  break;
320  }
321  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
322  if (JumpTarget.isGlobal()) {
323  MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
324  JumpTarget.getTargetFlags());
325  } else {
326  assert(JumpTarget.isSymbol());
327  MIB.addExternalSymbol(JumpTarget.getSymbolName(),
328  JumpTarget.getTargetFlags());
329  }
330  if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) {
331  MIB.addImm(MBBI->getOperand(2).getImm());
332  }
333 
334  } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
335  unsigned Op = (Opcode == X86::TCRETURNmi)
336  ? X86::TAILJMPm
337  : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
338  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
339  for (unsigned i = 0; i != X86::AddrNumOperands; ++i)
340  MIB.add(MBBI->getOperand(i));
341  } else if (Opcode == X86::TCRETURNri64) {
342  JumpTarget.setIsKill();
343  BuildMI(MBB, MBBI, DL,
344  TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
345  .add(JumpTarget);
346  } else {
347  JumpTarget.setIsKill();
348  BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
349  .add(JumpTarget);
350  }
351 
352  MachineInstr &NewMI = *std::prev(MBBI);
353  NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
354 
355  // Update the call site info.
356  if (MBBI->isCandidateForCallSiteEntry())
357  MBB.getParent()->moveCallSiteInfo(&*MBBI, &NewMI);
358 
359  // Delete the pseudo instruction TCRETURN.
360  MBB.erase(MBBI);
361 
362  return true;
363  }
364  case X86::EH_RETURN:
365  case X86::EH_RETURN64: {
366  MachineOperand &DestAddr = MBBI->getOperand(0);
367  assert(DestAddr.isReg() && "Offset should be in register!");
368  const bool Uses64BitFramePtr =
369  STI->isTarget64BitLP64() || STI->isTargetNaCl64();
370  Register StackPtr = TRI->getStackRegister();
371  BuildMI(MBB, MBBI, DL,
372  TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
373  .addReg(DestAddr.getReg());
374  // The EH_RETURN pseudo is really removed during the MC Lowering.
375  return true;
376  }
377  case X86::IRET: {
378  // Adjust stack to erase error code
379  int64_t StackAdj = MBBI->getOperand(0).getImm();
380  X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true);
381  // Replace pseudo with machine iret
382  unsigned RetOp = STI->is64Bit() ? X86::IRET64 : X86::IRET32;
383  // Use UIRET if UINTR is present (except for building kernel)
384  if (STI->is64Bit() && STI->hasUINTR() &&
386  RetOp = X86::UIRET;
387  BuildMI(MBB, MBBI, DL, TII->get(RetOp));
388  MBB.erase(MBBI);
389  return true;
390  }
391  case X86::RET: {
392  // Adjust stack to erase error code
393  int64_t StackAdj = MBBI->getOperand(0).getImm();
395  if (StackAdj == 0) {
396  MIB = BuildMI(MBB, MBBI, DL,
397  TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL));
398  } else if (isUInt<16>(StackAdj)) {
399  MIB = BuildMI(MBB, MBBI, DL,
400  TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL))
401  .addImm(StackAdj);
402  } else {
403  assert(!STI->is64Bit() &&
404  "shouldn't need to do this for x86_64 targets!");
405  // A ret can only handle immediates as big as 2**16-1. If we need to pop
406  // off bytes before the return address, we must do it manually.
407  BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
408  X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true);
409  BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
410  MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
411  }
412  for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
413  MIB.add(MBBI->getOperand(I));
414  MBB.erase(MBBI);
415  return true;
416  }
417  case X86::LCMPXCHG16B_SAVE_RBX: {
418  // Perform the following transformation.
419  // SaveRbx = pseudocmpxchg Addr, <4 opds for the address>, InArg, SaveRbx
420  // =>
421  // RBX = InArg
422  // actualcmpxchg Addr
423  // RBX = SaveRbx
424  const MachineOperand &InArg = MBBI->getOperand(6);
425  Register SaveRbx = MBBI->getOperand(7).getReg();
426 
427  // Copy the input argument of the pseudo into the argument of the
428  // actual instruction.
429  // NOTE: We don't copy the kill flag since the input might be the same reg
430  // as one of the other operands of LCMPXCHG16B.
431  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, InArg.getReg(), false);
432  // Create the actual instruction.
433  MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(X86::LCMPXCHG16B));
434  // Copy the operands related to the address.
435  for (unsigned Idx = 1; Idx < 6; ++Idx)
436  NewInstr->addOperand(MBBI->getOperand(Idx));
437  // Finally, restore the value of RBX.
438  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx,
439  /*SrcIsKill*/ true);
440 
441  // Delete the pseudo.
443  return true;
444  }
445  // Loading/storing mask pairs requires two kmov operations. The second one of
446  // these needs a 2 byte displacement relative to the specified address (with
447  // 32 bit spill size). The pairs of 1bit masks up to 16 bit masks all use the
448  // same spill size, they all are stored using MASKPAIR16STORE, loaded using
449  // MASKPAIR16LOAD.
450  //
451  // The displacement value might wrap around in theory, thus the asserts in
452  // both cases.
453  case X86::MASKPAIR16LOAD: {
454  int64_t Disp = MBBI->getOperand(1 + X86::AddrDisp).getImm();
455  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
456  Register Reg = MBBI->getOperand(0).getReg();
457  bool DstIsDead = MBBI->getOperand(0).isDead();
458  Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
459  Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
460 
461  auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
462  .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead));
463  auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
464  .addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead));
465 
466  for (int i = 0; i < X86::AddrNumOperands; ++i) {
467  MIBLo.add(MBBI->getOperand(1 + i));
468  if (i == X86::AddrDisp)
469  MIBHi.addImm(Disp + 2);
470  else
471  MIBHi.add(MBBI->getOperand(1 + i));
472  }
473 
474  // Split the memory operand, adjusting the offset and size for the halves.
475  MachineMemOperand *OldMMO = MBBI->memoperands().front();
476  MachineFunction *MF = MBB.getParent();
477  MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
478  MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
479 
480  MIBLo.setMemRefs(MMOLo);
481  MIBHi.setMemRefs(MMOHi);
482 
483  // Delete the pseudo.
484  MBB.erase(MBBI);
485  return true;
486  }
487  case X86::MASKPAIR16STORE: {
488  int64_t Disp = MBBI->getOperand(X86::AddrDisp).getImm();
489  assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
490  Register Reg = MBBI->getOperand(X86::AddrNumOperands).getReg();
491  bool SrcIsKill = MBBI->getOperand(X86::AddrNumOperands).isKill();
492  Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
493  Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
494 
495  auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
496  auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
497 
498  for (int i = 0; i < X86::AddrNumOperands; ++i) {
499  MIBLo.add(MBBI->getOperand(i));
500  if (i == X86::AddrDisp)
501  MIBHi.addImm(Disp + 2);
502  else
503  MIBHi.add(MBBI->getOperand(i));
504  }
505  MIBLo.addReg(Reg0, getKillRegState(SrcIsKill));
506  MIBHi.addReg(Reg1, getKillRegState(SrcIsKill));
507 
508  // Split the memory operand, adjusting the offset and size for the halves.
509  MachineMemOperand *OldMMO = MBBI->memoperands().front();
510  MachineFunction *MF = MBB.getParent();
511  MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
512  MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
513 
514  MIBLo.setMemRefs(MMOLo);
515  MIBHi.setMemRefs(MMOHi);
516 
517  // Delete the pseudo.
518  MBB.erase(MBBI);
519  return true;
520  }
521  case X86::MWAITX_SAVE_RBX: {
522  // Perform the following transformation.
523  // SaveRbx = pseudomwaitx InArg, SaveRbx
524  // =>
525  // [E|R]BX = InArg
526  // actualmwaitx
527  // [E|R]BX = SaveRbx
528  const MachineOperand &InArg = MBBI->getOperand(1);
529  // Copy the input argument of the pseudo into the argument of the
530  // actual instruction.
531  TII->copyPhysReg(MBB, MBBI, DL, X86::EBX, InArg.getReg(), InArg.isKill());
532  // Create the actual instruction.
533  BuildMI(MBB, MBBI, DL, TII->get(X86::MWAITXrrr));
534  // Finally, restore the value of RBX.
535  Register SaveRbx = MBBI->getOperand(2).getReg();
536  TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, /*SrcIsKill*/ true);
537  // Delete the pseudo.
539  return true;
540  }
541  case TargetOpcode::ICALL_BRANCH_FUNNEL:
542  ExpandICallBranchFunnel(&MBB, MBBI);
543  return true;
544  case X86::PLDTILECFGV: {
545  MI.setDesc(TII->get(X86::LDTILECFG));
546  return true;
547  }
548  case X86::PTILELOADDV:
549  case X86::PTILELOADDT1V: {
550  for (unsigned i = 2; i > 0; --i)
551  MI.RemoveOperand(i);
552  unsigned Opc =
553  Opcode == X86::PTILELOADDV ? X86::TILELOADD : X86::TILELOADDT1;
554  MI.setDesc(TII->get(Opc));
555  return true;
556  }
557  case X86::PTDPBSSDV:
558  case X86::PTDPBSUDV:
559  case X86::PTDPBUSDV:
560  case X86::PTDPBUUDV:
561  case X86::PTDPBF16PSV: {
562  MI.untieRegOperand(4);
563  for (unsigned i = 3; i > 0; --i)
564  MI.RemoveOperand(i);
565  unsigned Opc;
566  switch (Opcode) {
567  case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break;
568  case X86::PTDPBSUDV: Opc = X86::TDPBSUD; break;
569  case X86::PTDPBUSDV: Opc = X86::TDPBUSD; break;
570  case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break;
571  case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break;
572  default: llvm_unreachable("Impossible Opcode!");
573  }
574  MI.setDesc(TII->get(Opc));
575  MI.tieOperands(0, 1);
576  return true;
577  }
578  case X86::PTILESTOREDV: {
579  for (int i = 1; i >= 0; --i)
580  MI.RemoveOperand(i);
581  MI.setDesc(TII->get(X86::TILESTORED));
582  return true;
583  }
584  case X86::PTILEZEROV: {
585  for (int i = 2; i > 0; --i) // Remove row, col
586  MI.RemoveOperand(i);
587  MI.setDesc(TII->get(X86::TILEZERO));
588  return true;
589  }
590  case X86::CALL64pcrel32_RVMARKER:
591  case X86::CALL64r_RVMARKER:
592  case X86::CALL64m_RVMARKER:
593  expandCALL_RVMARKER(MBB, MBBI);
594  return true;
595  }
596  llvm_unreachable("Previous switch has a fallthrough?");
597 }
598 
599 // This function creates additional block for storing varargs guarded
600 // registers. It adds check for %al into entry block, to skip
601 // GuardedRegsBlk if xmm registers should not be stored.
602 //
603 // EntryBlk[VAStartPseudoInstr] EntryBlk
604 // | | .
605 // | | .
606 // | | GuardedRegsBlk
607 // | => | .
608 // | | .
609 // | TailBlk
610 // | |
611 // | |
612 //
613 void X86ExpandPseudo::ExpandVastartSaveXmmRegs(
614  MachineBasicBlock *EntryBlk,
615  MachineBasicBlock::iterator VAStartPseudoInstr) const {
616  assert(VAStartPseudoInstr->getOpcode() == X86::VASTART_SAVE_XMM_REGS);
617 
618  MachineFunction *Func = EntryBlk->getParent();
619  const TargetInstrInfo *TII = STI->getInstrInfo();
620  const DebugLoc &DL = VAStartPseudoInstr->getDebugLoc();
621  Register CountReg = VAStartPseudoInstr->getOperand(0).getReg();
622 
623  // Calculate liveins for newly created blocks.
624  LivePhysRegs LiveRegs(*STI->getRegisterInfo());
626 
627  LiveRegs.addLiveIns(*EntryBlk);
628  for (MachineInstr &MI : EntryBlk->instrs()) {
629  if (MI.getOpcode() == VAStartPseudoInstr->getOpcode())
630  break;
631 
632  LiveRegs.stepForward(MI, Clobbers);
633  }
634 
635  // Create the new basic blocks. One block contains all the XMM stores,
636  // and another block is the final destination regardless of whether any
637  // stores were performed.
638  const BasicBlock *LLVMBlk = EntryBlk->getBasicBlock();
639  MachineFunction::iterator EntryBlkIter = ++EntryBlk->getIterator();
640  MachineBasicBlock *GuardedRegsBlk = Func->CreateMachineBasicBlock(LLVMBlk);
641  MachineBasicBlock *TailBlk = Func->CreateMachineBasicBlock(LLVMBlk);
642  Func->insert(EntryBlkIter, GuardedRegsBlk);
643  Func->insert(EntryBlkIter, TailBlk);
644 
645  // Transfer the remainder of EntryBlk and its successor edges to TailBlk.
646  TailBlk->splice(TailBlk->begin(), EntryBlk,
647  std::next(MachineBasicBlock::iterator(VAStartPseudoInstr)),
648  EntryBlk->end());
649  TailBlk->transferSuccessorsAndUpdatePHIs(EntryBlk);
650 
651  int64_t FrameIndex = VAStartPseudoInstr->getOperand(1).getImm();
652  Register BaseReg;
653  uint64_t FrameOffset =
654  X86FL->getFrameIndexReference(*Func, FrameIndex, BaseReg).getFixed();
655  uint64_t VarArgsRegsOffset = VAStartPseudoInstr->getOperand(2).getImm();
656 
657  // TODO: add support for YMM and ZMM here.
658  unsigned MOVOpc = STI->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
659 
660  // In the XMM save block, save all the XMM argument registers.
661  for (int64_t OpndIdx = 3, RegIdx = 0;
662  OpndIdx < VAStartPseudoInstr->getNumOperands() - 1;
663  OpndIdx++, RegIdx++) {
664 
665  int64_t Offset = FrameOffset + VarArgsRegsOffset + RegIdx * 16;
666 
667  MachineMemOperand *MMO = Func->getMachineMemOperand(
670  /*Size=*/16, Align(16));
671 
672  BuildMI(GuardedRegsBlk, DL, TII->get(MOVOpc))
673  .addReg(BaseReg)
674  .addImm(/*Scale=*/1)
675  .addReg(/*IndexReg=*/0)
676  .addImm(/*Disp=*/Offset)
677  .addReg(/*Segment=*/0)
678  .addReg(VAStartPseudoInstr->getOperand(OpndIdx).getReg())
679  .addMemOperand(MMO);
681  VAStartPseudoInstr->getOperand(OpndIdx).getReg()));
682  }
683 
684  // The original block will now fall through to the GuardedRegsBlk.
685  EntryBlk->addSuccessor(GuardedRegsBlk);
686  // The GuardedRegsBlk will fall through to the TailBlk.
687  GuardedRegsBlk->addSuccessor(TailBlk);
688 
689  if (!STI->isCallingConvWin64(Func->getFunction().getCallingConv())) {
690  // If %al is 0, branch around the XMM save block.
691  BuildMI(EntryBlk, DL, TII->get(X86::TEST8rr))
692  .addReg(CountReg)
693  .addReg(CountReg);
694  BuildMI(EntryBlk, DL, TII->get(X86::JCC_1))
695  .addMBB(TailBlk)
697  EntryBlk->addSuccessor(TailBlk);
698  }
699 
700  // Add liveins to the created block.
701  addLiveIns(*GuardedRegsBlk, LiveRegs);
702  addLiveIns(*TailBlk, LiveRegs);
703 
704  // Delete the pseudo.
705  VAStartPseudoInstr->eraseFromParent();
706 }
707 
708 /// Expand all pseudo instructions contained in \p MBB.
709 /// \returns true if any expansion occurred for \p MBB.
710 bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
711  bool Modified = false;
712 
713  // MBBI may be invalidated by the expansion.
715  while (MBBI != E) {
716  MachineBasicBlock::iterator NMBBI = std::next(MBBI);
717  Modified |= ExpandMI(MBB, MBBI);
718  MBBI = NMBBI;
719  }
720 
721  return Modified;
722 }
723 
724 bool X86ExpandPseudo::ExpandPseudosWhichAffectControlFlow(MachineFunction &MF) {
725  // Currently pseudo which affects control flow is only
726  // X86::VASTART_SAVE_XMM_REGS which is located in Entry block.
727  // So we do not need to evaluate other blocks.
728  for (MachineInstr &Instr : MF.front().instrs()) {
729  if (Instr.getOpcode() == X86::VASTART_SAVE_XMM_REGS) {
730  ExpandVastartSaveXmmRegs(&(MF.front()), Instr);
731  return true;
732  }
733  }
734 
735  return false;
736 }
737 
738 bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
739  STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
740  TII = STI->getInstrInfo();
741  TRI = STI->getRegisterInfo();
742  X86FI = MF.getInfo<X86MachineFunctionInfo>();
743  X86FL = STI->getFrameLowering();
744 
745  bool Modified = ExpandPseudosWhichAffectControlFlow(MF);
746 
747  for (MachineBasicBlock &MBB : MF)
748  Modified |= ExpandMBB(MBB);
749  return Modified;
750 }
751 
752 /// Returns an instance of the pseudo instruction expansion pass.
754  return new X86ExpandPseudo();
755 }
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:708
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:575
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
X86Subtarget.h
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
X86InstrBuilder.h
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:263
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::MachineFunction::moveCallSiteInfo
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
Definition: MachineFunction.cpp:948
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:341
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
EHPersonalities.h
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:827
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:511
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:739
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::addLiveIns
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs)
Adds registers contained in LiveRegs to the block live-in list of MBB.
Definition: LivePhysRegs.cpp:257
llvm::X86ISD::VASTART_SAVE_XMM_REGS
@ VASTART_SAVE_XMM_REGS
Definition: X86ISelLowering.h:655
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:790
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
X86FrameLowering.h
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:746
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
X86MachineFunctionInfo.h
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:820
X86.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
GlobalValue.h
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1488
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1332
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
INITIALIZE_PASS
INITIALIZE_PASS(X86ExpandPseudo, DEBUG_TYPE, X86_EXPAND_PSEUDO_NAME, false, false) void X86ExpandPseudo
Definition: X86ExpandPseudo.cpp:86
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:169
LoopDeletionResult::Modified
@ Modified
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:418
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::X86ISD::IRET
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
Definition: X86ISelLowering.h:134
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:43
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::X86FrameLowering
Definition: X86FrameLowering.h:27
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:414
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86::COND_B
@ COND_B
Definition: X86BaseInfo.h:83
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::createX86ExpandPseudoPass
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
Definition: X86ExpandPseudo.cpp:753
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:230
FirstTarget
static Target * FirstTarget
Definition: TargetRegistry.cpp:18
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
uint32_t
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::ifs::IFSSymbolType::Func
@ Func
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86ExpandPseudo.cpp:29
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
X86_EXPAND_PSEUDO_NAME
#define X86_EXPAND_PSEUDO_NAME
Definition: X86ExpandPseudo.cpp:30
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:608
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:123
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:885
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
X86InstrInfo.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::X86::COND_E
@ COND_E
Definition: X86BaseInfo.h:85
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:812
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:339
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37