LLVM 19.0.0git
XtensaISelLowering.cpp
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1//===- XtensaISelLowering.cpp - Xtensa DAG Lowering Implementation --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Xtensa uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XtensaISelLowering.h"
15#include "XtensaSubtarget.h"
16#include "XtensaTargetMachine.h"
23#include "llvm/Support/Debug.h"
26
27using namespace llvm;
28
29#define DEBUG_TYPE "xtensa-lower"
30
32 const XtensaSubtarget &STI)
33 : TargetLowering(TM), Subtarget(STI) {
34 // Set up the register classes.
35 addRegisterClass(MVT::i32, &Xtensa::ARRegClass);
36
37 // Set up special registers.
39
41
43
44 // Compute derived properties from the register classes
46}
47
49 SelectionDAG &DAG) const {
50 switch (Op.getOpcode()) {
51 default:
52 report_fatal_error("Unexpected node to lower");
53 }
54}
55
56const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
57 return nullptr;
58}
const char LLVMTargetMachineRef TM
This class represents an Operation in the Expression.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
const XtensaRegisterInfo * getRegisterInfo() const override
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI)
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39