46#define DEBUG_TYPE "hexinsert"
52 cl::desc(
"Vreg# cutoff for insert generation."));
57 cl::desc(
"Vreg distance cutoff for insert "
63 cl::desc(
"Maximum size of OrderedRegisterList"));
69 cl::desc(
"Enable timing of insert generation"));
72 cl::desc(
"Enable detailed timing of insert "
98 RegisterSet &operator=(
const RegisterSet &RS) =
default;
102 unsigned find_first()
const {
109 unsigned find_next(
unsigned Prev)
const {
117 unsigned Idx = v2x(R);
122 unsigned Idx = v2x(R);
135 reference operator[](
unsigned R) {
136 unsigned Idx = v2x(R);
140 bool operator[](
unsigned R)
const {
141 unsigned Idx = v2x(R);
145 bool has(
unsigned R)
const {
146 unsigned Idx = v2x(R);
155 bool includes(
const RegisterSet &Rs)
const {
157 return !Rs.BitVector::test(*
this);
159 bool intersects(
const RegisterSet &Rs)
const {
164 void ensure(
unsigned Idx) {
166 resize(std::max(
Idx+1, 32U));
169 static inline unsigned v2x(
unsigned v) {
173 static inline unsigned x2v(
unsigned x) {
183 const PrintRegSet &
P);
192 for (
unsigned R =
P.RS.find_first(); R; R =
P.RS.find_next(R))
200 struct UnsignedMap :
public DenseMap<unsigned,unsigned> {
201 UnsignedMap() =
default;
212 struct RegisterOrdering :
public UnsignedMap {
213 RegisterOrdering() =
default;
215 unsigned operator[](
unsigned VR)
const {
223 bool operator() (
unsigned VR1,
unsigned VR2)
const {
224 return operator[](VR1) < operator[](VR2);
234 struct BitValueOrdering {
235 BitValueOrdering(
const RegisterOrdering &RB) : BaseOrd(RB) {}
240 const RegisterOrdering &BaseOrd;
250 if (V1.
is(0) ||
V2.is(0))
254 if (
V2.is(1) || V1.
is(1))
257 unsigned Ind1 = BaseOrd[V1.
RefI.
Reg], Ind2 = BaseOrd[
V2.RefI.Reg];
261 assert(V1.
RefI.
Pos !=
V2.RefI.Pos &&
"Bit values should be different");
270 struct CellMapShadow {
276 if (RInd >= CVect.size())
277 CVect.resize(std::max(RInd+16, 32U),
nullptr);
287 using CellVectType = std::vector<const BitTracker::RegisterCell *>;
294 struct RegisterCellLexCompare {
295 RegisterCellLexCompare(
const BitValueOrdering &BO, CellMapShadow &M)
296 : BitOrd(BO), CM(
M) {}
298 bool operator() (
unsigned VR1,
unsigned VR2)
const;
301 const BitValueOrdering &BitOrd;
311 struct RegisterCellBitCompareSel {
312 RegisterCellBitCompareSel(
unsigned R,
unsigned B,
unsigned N,
313 const BitValueOrdering &BO, CellMapShadow &M)
314 : SelR(
R), SelB(
B), BitN(
N), BitOrd(BO), CM(
M) {}
316 bool operator() (
unsigned VR1,
unsigned VR2)
const;
319 const unsigned SelR, SelB;
321 const BitValueOrdering &BitOrd;
327bool RegisterCellLexCompare::operator() (
unsigned VR1,
unsigned VR2)
const {
342 for (
uint16_t i = 0, w = std::min(W1, W2); i < w; ++i) {
345 return BitOrd(V1, V2);
351 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2];
354bool RegisterCellBitCompareSel::operator() (
unsigned VR1,
unsigned VR2)
const {
360 uint16_t Bit1 = (VR1 == SelR) ? SelB : BitN;
361 uint16_t Bit2 = (VR2 == SelR) ? SelB : BitN;
375 return BitOrd(V1, V2);
381 class OrderedRegisterList {
382 using ListType = std::vector<unsigned>;
383 const unsigned MaxSize;
386 OrderedRegisterList(
const RegisterOrdering &RO)
389 void insert(
unsigned VR);
392 unsigned operator[](
unsigned Idx)
const {
397 unsigned size()
const {
401 using iterator = ListType::iterator;
405 iterator
end() {
return Seq.
end(); }
410 unsigned idx(iterator It)
const {
return It-
begin(); }
414 const RegisterOrdering &Ord;
424 const OrderedRegisterList &RL;
430 OrderedRegisterList::const_iterator
B =
P.RL.begin(), E =
P.RL.end();
431 for (OrderedRegisterList::const_iterator
I =
B;
I != E; ++
I) {
442void OrderedRegisterList::insert(
unsigned VR) {
449 unsigned S = Seq.size();
452 assert(Seq.size() <= MaxSize);
455void OrderedRegisterList::remove(
unsigned VR) {
468 : SrcR(SR), InsR(
IR), Wdh(
W),
Off(
O) {}
486 unsigned SrcR =
P.IFR.SrcR, InsR =
P.IFR.InsR;
488 <<
",#" <<
P.IFR.Wdh <<
",#" <<
P.IFR.Off <<
')';
492 using IFRecordWithRegSet = std::pair<IFRecord, RegisterSet>;
514 return "Hexagon generate \"insert\" instructions";
528 void buildOrderingMF(RegisterOrdering &RO)
const;
529 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO)
const;
532 bool isSmallConstant(
unsigned VR)
const;
533 bool isValidInsertForm(
unsigned DstR,
unsigned SrcR,
unsigned InsR,
535 bool findSelfReference(
unsigned VR)
const;
536 bool findNonSelfReference(
unsigned VR)
const;
537 void getInstrDefs(
const MachineInstr *
MI, RegisterSet &Defs)
const;
541 PairMapType &M)
const;
544 PairMapType &M)
const;
545 bool findRecordInsertForms(
unsigned VR, OrderedRegisterList &AVs);
547 void findRemovableRegisters(
unsigned VR, IFRecord IF,
548 RegisterSet &RMs)
const;
549 void computeRemovableRegisters();
551 void pruneEmptyLists();
552 void pruneCoveredSets(
unsigned VR);
553 void pruneUsesTooFar(
unsigned VR,
const UnsignedMap &RPO, PairMapType &M);
554 void pruneRegCopies(
unsigned VR);
555 void pruneCandidates();
556 void selectCandidates();
557 bool generateInserts();
562 using IFListType = std::vector<IFRecordWithRegSet>;
565 void dump_map()
const;
575 RegisterOrdering BaseOrd;
576 RegisterOrdering CellOrd;
582char HexagonGenInsert::ID = 0;
584void HexagonGenInsert::dump_map()
const {
585 for (
const auto &
I : IFMap) {
587 const IFListType &LL =
I.second;
588 for (
const auto &J : LL)
589 dbgs() <<
" " << PrintIFR(J.first, HRI) <<
", "
590 << PrintRegSet(J.second, HRI) <<
'\n';
594void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO)
const {
598 if (!CMS->BT.reached(&
B))
603 if (MO.isReg() && MO.isDef()) {
605 assert(MO.getSubReg() == 0 &&
"Unexpected subregister in definition");
607 RO.insert(std::make_pair(R,
Index++));
617void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB,
618 RegisterOrdering &RO)
const {
621 BitValueOrdering BVO(RB);
622 RegisterCellLexCompare LexCmp(BVO, *CMS);
624 using SortableVectorType = std::vector<unsigned>;
626 SortableVectorType VRs;
628 VRs.push_back(
I.first);
631 for (
unsigned i = 0, n = VRs.size(); i < n; ++i)
632 RO.insert(std::make_pair(VRs[i], i));
636 return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;
639bool HexagonGenInsert::isConstant(
unsigned VR)
const {
644 if (BV.
is(0) || BV.
is(1))
651bool HexagonGenInsert::isSmallConstant(
unsigned VR)
const {
671 return isInt<8>(
Lo_32(V)) && isInt<8>(
Hi_32(V));
674bool HexagonGenInsert::isValidInsertForm(
unsigned DstR,
unsigned SrcR,
680 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))
688 if (DstRC == &Hexagon::DoubleRegsRegClass)
691 if (S < 32 && S+L > 32)
696bool HexagonGenInsert::findSelfReference(
unsigned VR)
const {
706bool HexagonGenInsert::findNonSelfReference(
unsigned VR)
const {
717 RegisterSet &Defs)
const {
719 if (!MO.isReg() || !MO.isDef())
729 RegisterSet &
Uses)
const {
731 if (!MO.isReg() || !MO.isUse())
742 PairMapType &M)
const {
749 PairMapType::iterator
F =
M.find(std::make_pair(FromN, ToN));
752 unsigned ToRPO = RPO.lookup(ToN);
760 if (
PB == FromB || RPO.lookup(
PB->getNumber()) >= ToRPO)
762 unsigned D =
PB->size() + distance(FromB,
PB, RPO, M);
768 M.insert(std::make_pair(std::make_pair(FromN, ToN), MaxD));
774 PairMapType &M)
const {
777 return std::distance(FromI, ToI);
778 unsigned D1 = std::distance(
TB->begin(), ToI);
779 unsigned D2 = distance(FB, TB, RPO, M);
780 unsigned D3 = std::distance(FromI, FB->
end());
784bool HexagonGenInsert::findRecordInsertForms(
unsigned VR,
785 OrderedRegisterList &AVs) {
788 <<
" AVs: " << PrintORL(AVs, HRI) <<
"\n";
793 using iterator = OrderedRegisterList::iterator;
795 BitValueOrdering BVO(BaseOrd);
799 using RSRecord = std::pair<unsigned, uint16_t>;
800 using RSListType = std::vector<RSRecord>;
811 iterator
B = AVs.begin(), E = AVs.end();
819 for (L = 0;
L <
W-S; ++
L) {
822 RegisterCellBitCompareSel RCB(VR, S+L, L, BVO, *CMS);
823 iterator NewB = std::lower_bound(
B, E, VR, RCB);
824 iterator NewE = std::upper_bound(NewB, E, VR, RCB);
830 for (iterator
I =
B;
I != NewB; ++
I)
831 LM[L].push_back(std::make_pair(*
I, S));
832 for (iterator
I = NewE;
I != E; ++
I)
833 LM[L].push_back(std::make_pair(*
I, S));
843 for (iterator
I =
B;
I != E; ++
I)
844 LM[L].push_back(std::make_pair(*
I, S));
852 dbgs() <<
"Prefixes matching register " <<
printReg(VR, HRI) <<
"\n";
853 for (
const auto &
I : LM) {
854 dbgs() <<
" L=" <<
I.first <<
':';
855 const RSListType &LL =
I.second;
856 for (
const auto &J : LL)
857 dbgs() <<
" (" <<
printReg(J.first, HRI) <<
",@" << J.second <<
')';
862 bool Recorded =
false;
864 for (
unsigned SrcR : AVs) {
865 int FDi = -1, LDi = -1;
868 for (
uint16_t i = 0, w = std::min(W, AW); i < w; ++i) {
882 LRSMapType::iterator
F = LM.find(L);
885 RSListType &LL =
F->second;
886 for (
const auto &
I : LL) {
895 uint16_t LowS = (EL < FD) ? FD-EL : 0;
898 unsigned InsR =
I.first;
899 if (!isValidInsertForm(VR, SrcR, InsR, L, S))
903 <<
',' <<
printReg(InsR, HRI) <<
",#" <<
L <<
",#"
906 IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S),
RegisterSet());
907 IFMap[VR].push_back(RR);
917 OrderedRegisterList &AVs) {
923 if (!CMS->BT.reached(
B))
933 getInstrDefs(&
MI, InsDefs);
935 bool Skip =
MI.isCopy() ||
MI.isRegSequence();
940 for (
unsigned VR = InsDefs.find_first(); VR; VR = InsDefs.find_next(VR)) {
949 if (findSelfReference(VR) || isSmallConstant(VR))
952 findRecordInsertForms(VR, AVs);
961 for (
unsigned VR = InsDefs.find_first(); VR; VR = InsDefs.find_next(VR))
963 BlockDefs.insert(InsDefs);
966 for (
auto *DTN : children<MachineDomTreeNode*>(MDT->getNode(
B))) {
968 collectInBlock(SB, AVs);
971 for (
unsigned VR = BlockDefs.find_first(); VR; VR = BlockDefs.find_next(VR))
975void HexagonGenInsert::findRemovableRegisters(
unsigned VR, IFRecord IF,
976 RegisterSet &RMs)
const {
986 while (!Regs[S].empty()) {
988 unsigned OtherS = 1-S;
989 Regs[OtherS].clear();
990 for (
unsigned R = Regs[S].find_first();
R;
R = Regs[S].find_next(R)) {
992 if (R ==
IF.SrcR || R ==
IF.InsR)
1004 if (!findNonSelfReference(R))
1014 getInstrUses(DefI, Regs[OtherS]);
1026void HexagonGenInsert::computeRemovableRegisters() {
1027 for (
auto &
I : IFMap) {
1028 IFListType &LL =
I.second;
1030 findRemovableRegisters(
I.first, J.first, J.second);
1034void HexagonGenInsert::pruneEmptyLists() {
1039 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1040 if (
I->second.empty())
1043 for (
const auto &It : Prune)
1047void HexagonGenInsert::pruneCoveredSets(
unsigned VR) {
1048 IFMapType::iterator
F = IFMap.find(VR);
1050 IFListType &LL =
F->second;
1060 bool DefEx = HII->isConstExtended(*DefVR);
1062 for (
const auto &
I : LL) {
1063 if (
I.second.empty())
1068 if (!DefEx || HasNE) {
1071 auto IsEmpty = [] (
const IFRecordWithRegSet &
IR) ->
bool {
1072 return IR.second.empty();
1081 IFRecord MaxIF = LL[0].first;
1082 for (
unsigned i = 1, n = LL.size(); i < n; ++i) {
1084 const IFRecord &
IF = LL[i].first;
1085 unsigned M0 = BaseOrd[MaxIF.SrcR],
M1 = BaseOrd[MaxIF.InsR];
1086 unsigned R0 = BaseOrd[
IF.SrcR], R1 = BaseOrd[
IF.InsR];
1093 if (MaxIF.Wdh >
IF.Wdh)
1095 if (MaxIF.Wdh ==
IF.Wdh && MaxIF.Off >=
IF.Off)
1105 LL.push_back(std::make_pair(MaxIF,
RegisterSet()));
1115 for (
unsigned i = 0, n = LL.size(); i < n; ) {
1119 if (j != i && LL[j].second.includes(RMi))
1127 LL.erase(LL.begin()+i);
1132void HexagonGenInsert::pruneUsesTooFar(
unsigned VR,
const UnsignedMap &RPO,
1134 IFMapType::iterator
F = IFMap.find(VR);
1136 IFListType &LL =
F->second;
1140 for (
unsigned i = LL.size(); i > 0; --i) {
1141 unsigned SR = LL[i-1].first.SrcR,
IR = LL[i-1].first.InsR;
1144 unsigned DSV = distance(DefS, DefV, RPO, M);
1146 unsigned DIV = distance(DefI, DefV, RPO, M);
1150 LL.erase(LL.begin()+(i-1));
1154void HexagonGenInsert::pruneRegCopies(
unsigned VR) {
1155 IFMapType::iterator
F = IFMap.find(VR);
1157 IFListType &LL =
F->second;
1159 auto IsCopy = [] (
const IFRecordWithRegSet &
IR) ->
bool {
1160 return IR.first.Wdh == 32 && (
IR.first.Off == 0 ||
IR.first.Off == 32);
1165void HexagonGenInsert::pruneCandidates() {
1170 for (
const auto &
I : IFMap)
1171 pruneCoveredSets(
I.first);
1179 for (
const auto &
I : RPOT)
1180 RPO[
I->getNumber()] = RPON++;
1184 for (
const auto &
I : IFMap)
1185 pruneUsesTooFar(
I.first, RPO, Memo);
1189 for (
const auto &
I : IFMap)
1190 pruneRegCopies(
I.first);
1204 IFOrdering(
const UnsignedMap &UC,
const RegisterOrdering &BO)
1205 : UseC(UC), BaseOrd(BO) {}
1207 bool operator() (
const IFRecordWithRegSet &
A,
1208 const IFRecordWithRegSet &
B)
const;
1211 void stats(
const RegisterSet &Rs,
unsigned &
Size,
unsigned &Zero,
1212 unsigned &Sum)
const;
1214 const UnsignedMap &UseC;
1215 const RegisterOrdering &BaseOrd;
1220bool IFOrdering::operator() (
const IFRecordWithRegSet &
A,
1221 const IFRecordWithRegSet &
B)
const {
1222 unsigned SizeA = 0, ZeroA = 0, SumA = 0;
1223 unsigned SizeB = 0, ZeroB = 0, SumB = 0;
1224 stats(
A.second, SizeA, ZeroA, SumA);
1225 stats(
B.second, SizeB, ZeroB, SumB);
1229 return ZeroA > ZeroB;
1231 uint64_t AvgA = SumA*SizeB, AvgB = SumB*SizeA;
1237 unsigned OSA = BaseOrd[
A.first.SrcR], OSB = BaseOrd[
B.first.SrcR];
1240 unsigned OIA = BaseOrd[
A.first.InsR], OIB = BaseOrd[
B.first.InsR];
1243 if (
A.first.Wdh !=
B.first.Wdh)
1244 return A.first.Wdh <
B.first.Wdh;
1245 return A.first.Off <
B.first.Off;
1248void IFOrdering::stats(
const RegisterSet &Rs,
unsigned &
Size,
unsigned &Zero,
1249 unsigned &Sum)
const {
1250 for (
unsigned R = Rs.find_first(); R; R = Rs.find_next(R)) {
1251 UnsignedMap::const_iterator
F = UseC.find(R);
1253 unsigned UC =
F->second;
1261void HexagonGenInsert::selectCandidates() {
1269 UnsignedMap UseC, RemC;
1270 IFMapType::iterator
End = IFMap.end();
1272 for (IFMapType::iterator
I = IFMap.begin();
I !=
End; ++
I) {
1273 const IFListType &LL =
I->second;
1275 for (
const auto &J : LL)
1276 TT.insert(J.second);
1277 for (
unsigned R =
TT.find_first(); R; R =
TT.find_next(R))
1282 for (
unsigned R = AllRMs.find_first(); R; R = AllRMs.find_next(R)) {
1289 use_iterator E =
MRI->use_nodbg_end();
1290 for (use_iterator
I =
MRI->use_nodbg_begin(R);
I != E; ++
I)
1291 UIs.insert(
I->getParent());
1292 unsigned C = UIs.size();
1295 unsigned D = RemC[
R];
1296 UseC[
R] = (
C >
D) ?
C-
D : 0;
1300 if (!SelectAll0 && !SelectHas0)
1308 IFOrdering IFO(UseC, BaseOrd);
1309 for (IFMapType::iterator
I = IFMap.begin();
I !=
End; ++
I) {
1310 IFListType &LL =
I->second;
1318 assert(MinI != LL.end());
1319 IFRecordWithRegSet
M = *MinI;
1330 getInstrUses(DefI, Us);
1331 bool Accept =
false;
1335 for (
unsigned R = Us.find_first(); R; R = Us.find_next(R)) {
1342 }
else if (SelectHas0) {
1344 for (
unsigned R = Us.find_first(); R; R = Us.find_next(R)) {
1361 for (IFMapType::iterator
I = IFMap.begin();
I !=
End; ++
I) {
1362 const IFListType &LL =
I->second;
1364 AllRMs.insert(LL[0].second);
1366 for (IFMapType::iterator
I = IFMap.begin();
I !=
End; ++
I) {
1367 IFListType &LL =
I->second;
1370 unsigned SR = LL[0].first.SrcR,
IR = LL[0].first.InsR;
1371 if (AllRMs[SR] || AllRMs[
IR])
1378bool HexagonGenInsert::generateInserts() {
1382 for (
auto &
I : IFMap) {
1383 unsigned VR =
I.first;
1392 for (
auto &
I : IFMap) {
1396 unsigned NewR = RegMap[
I.first];
1397 bool R32 =
MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;
1398 const MCInstrDesc &
D = R32 ? HII->get(Hexagon::S2_insert)
1399 : HII->get(Hexagon::S2_insertp);
1400 IFRecord
IF =
I.second[0].first;
1401 unsigned Wdh =
IF.Wdh,
Off =
IF.Off;
1403 if (R32 &&
MRI->getRegClass(
IF.InsR) == &Hexagon::DoubleRegsRegClass) {
1404 InsS = Hexagon::isub_lo;
1406 InsS = Hexagon::isub_hi;
1414 At =
B.getFirstNonPHI();
1422 MRI->clearKillFlags(
IF.SrcR);
1423 MRI->clearKillFlags(
IF.InsR);
1426 for (
const auto &
I : IFMap) {
1428 MRI->replaceRegWith(
I.first, RegMap[
I.first]);
1436 bool Changed =
false;
1438 for (
auto *DTN : children<MachineDomTreeNode*>(
N))
1439 Changed |= removeDeadCode(DTN);
1442 std::vector<MachineInstr*> Instrs;
1444 Instrs.push_back(&
MI);
1447 unsigned Opc =
MI->getOpcode();
1450 if (Opc == TargetOpcode::LIFETIME_START ||
1451 Opc == TargetOpcode::LIFETIME_END)
1454 if (
MI->isInlineAsm() || !
MI->isSafeToMove(Store))
1457 bool AllDead =
true;
1460 if (!MO.isReg() || !MO.isDef())
1463 if (!
R.isVirtual() || !
MRI->use_nodbg_empty(R)) {
1473 for (
unsigned Reg : Regs)
1474 MRI->markUsesInDebugValueAsUndef(Reg);
1486 bool Changed =
false;
1496 HII =
ST.getInstrInfo();
1497 HRI =
ST.getRegisterInfo();
1500 MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1507 Changed = removeDeadCode(MDT->getRootNode());
1513 CellMapShadow MS(BTLoc);
1516 buildOrderingMF(BaseOrd);
1517 buildOrderingBT(BaseOrd, CellOrd);
1520 dbgs() <<
"Cell ordering:\n";
1521 for (
const auto &
I : CellOrd) {
1522 unsigned VR =
I.first, Pos =
I.second;
1529 OrderedRegisterList AvailR(CellOrd);
1531 const char *
const TGName =
"hexinsert";
1532 const char *
const TGDesc =
"Generate Insert Instructions";
1537 collectInBlock(RootB, AvailR);
1539 computeRemovableRegisters();
1543 dbgs() <<
"Candidates after collection:\n";
1556 dbgs() <<
"Candidates after pruning:\n";
1564 NamedRegionTimer _T(
"selection",
"selection", TGName, TGDesc, TimingDetail);
1569 dbgs() <<
"Candidates after selection:\n";
1580 for (IFMapType::iterator
I = IFMap.begin(), E = IFMap.end();
I != E; ++
I) {
1585 for (
const auto &It : Out)
1601 return new HexagonGenInsert();
1609 "Hexagon generate \"insert\" instructions",
false,
false)
unsigned const MachineRegisterInfo * MRI
static bool isConstant(const MachineInstr &MI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static std::optional< ArrayRef< InsnRange >::iterator > intersects(const MachineInstr *StartMI, const MachineInstr *EndMI, const ArrayRef< InsnRange > &Ranges, const InstructionOrdering &Ordering)
Check if the instruction range [StartMI, EndMI] intersects any instruction range in Ranges.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
Rewrite Partial Register Uses
This file defines the little GraphTraits<X> template class that should be specialized by classes that...
static cl::opt< bool > OptConst("insert-const", cl::init(false), cl::Hidden)
static cl::opt< unsigned > MaxORLSize("insert-max-orl", cl::init(4096), cl::Hidden, cl::desc("Maximum size of OrderedRegisterList"))
static cl::opt< unsigned > MaxIFMSize("insert-max-ifmap", cl::init(1024), cl::Hidden, cl::desc("Maximum size of IFMap"))
static cl::opt< bool > OptTimingDetail("insert-timing-detail", cl::Hidden, cl::desc("Enable detailed timing of insert " "generation"))
static cl::opt< bool > OptTiming("insert-timing", cl::Hidden, cl::desc("Enable timing of insert generation"))
static cl::opt< unsigned > VRegDistCutoff("insert-dist-cutoff", cl::init(30U), cl::Hidden, cl::desc("Vreg distance cutoff for insert " "generation."))
static cl::opt< bool > OptSelectAll0("insert-all0", cl::init(false), cl::Hidden)
static cl::opt< unsigned > VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, cl::desc("Vreg# cutoff for insert generation."))
static cl::opt< bool > OptSelectHas0("insert-has0", cl::init(false), cl::Hidden)
Hexagon generate insert instructions
static bool lookup(const GsymReader &GR, DataExtractor &Data, uint64_t &Offset, uint64_t BaseAddr, uint64_t Addr, SourceLocations &SrcLocs, llvm::Error &Err)
A Lookup helper functions.
Legalize the Machine IR a function s Machine IR
unsigned const TargetRegisterInfo * TRI
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool test(unsigned Idx) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
bool anyCommon(const BitVector &RHS) const
Test if any common bits are set.
void clear()
clear - Removes all bits from the bitvector.
bool any() const
any - Returns true if any bit is set.
BitVector & operator|=(const BitVector &RHS)
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
reference operator[](unsigned Idx)
Base class for the actual dominator tree node.
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
iterator_range< pred_iterator > predecessors()
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
friend const_iterator begin(StringRef path, Style style)
Get begin iterator over path.
friend const_iterator end(StringRef path)
Get end iterator over path.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ TB
TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...
initializer< Ty > init(const Ty &Val)
std::set< RegisterRef > RegisterSet
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
auto min_element(R &&Range)
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned M1(unsigned Val)
bool DebugFlag
This boolean is set to true if the '-debug' command line option is specified.
auto reverse(ContainerTy &&C)
void sort(IteratorTy Start, IteratorTy End)
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createHexagonGenInsert()
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
bool isCurrentDebugType(const char *Type)
isCurrentDebugType - Return true if the specified string is the debug type specified on the command l...
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
unsigned M0(unsigned Val)
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
void initializeHexagonGenInsertPass(PassRegistry &)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
bool is(unsigned T) const
const RegisterCell & lookup(unsigned Reg) const
This class is basically a combination of TimeRegion and Timer.