121#define DEBUG_TYPE "expand-condsets"
170 bool CoaLimitActive =
false;
171 bool TfrLimitActive =
false;
174 unsigned CoaCounter = 0;
175 unsigned TfrCounter = 0;
180 Sub(
Op.getSubReg()) {}
181 RegisterRef(
unsigned R = 0,
unsigned S = 0) :
Reg(
R), Sub(S) {}
184 return Reg == RR.Reg && Sub == RR.Sub;
188 return Reg < RR.Reg || (
Reg == RR.Reg && Sub < RR.Sub);
196 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
197 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
199 unsigned getMaskForSub(
unsigned Sub);
203 void addRefToMap(RegisterRef RR, ReferenceMap &Map,
unsigned Exec);
204 bool isRefInMap(RegisterRef, ReferenceMap &Map,
unsigned Exec);
209 void recalculateLiveInterval(
Register Reg);
211 void updateLiveness(
const std::set<Register> &RegSet,
bool Recalc,
212 bool UpdateKills,
bool UpdateDeads);
213 void distributeLiveIntervals(
const std::set<Register> &Regs);
219 bool ReadUndef,
bool ImpUse);
230 std::set<Register> &UpdRegs);
231 void renameInRange(RegisterRef RO, RegisterRef RN,
unsigned PredR,
237 bool isIntReg(RegisterRef RR,
unsigned &BW);
239 bool coalesceRegisters(RegisterRef R1, RegisterRef
R2);
241 std::set<Register> &UpdRegs);
246char HexagonExpandCondsets::ID = 0;
255 "Hexagon Expand Condsets",
false,
false)
262unsigned HexagonExpandCondsets::getMaskForSub(
unsigned Sub) {
264 case Hexagon::isub_lo:
265 case Hexagon::vsub_lo:
267 case Hexagon::isub_hi:
268 case Hexagon::vsub_hi:
270 case Hexagon::NoSubRegister:
277 unsigned Opc =
MI.getOpcode();
279 case Hexagon::C2_mux:
280 case Hexagon::C2_muxii:
281 case Hexagon::C2_muxir:
282 case Hexagon::C2_muxri:
283 case Hexagon::PS_pselect:
292 return Sub != 0 ?
TRI->getSubRegIndexLaneMask(Sub)
293 :
MRI->getMaxLaneMaskForVReg(Reg);
296void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
298 unsigned Mask = getMaskForSub(RR.Sub) |
Exec;
299 ReferenceMap::iterator
F =
Map.find(RR.Reg);
301 Map.insert(std::make_pair(RR.Reg, Mask));
306bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
308 ReferenceMap::iterator
F =
Map.find(RR.Reg);
311 unsigned Mask = getMaskForSub(RR.Sub) |
Exec;
312 if (Mask &
F->second)
317void HexagonExpandCondsets::updateKillFlags(
Register Reg) {
321 for (
unsigned i = 0, e =
MI->getNumOperands(); i !=
e; ++i) {
323 if (!
Op.isReg() || !
Op.isUse() ||
Op.getReg() !=
Reg ||
324 MI->isRegTiedToDefOperand(i))
327 if ((SLM & LM) == SLM) {
338 if (!
I->end.isRegister())
342 auto NextI = std::next(
I);
343 if (NextI !=
E && NextI->start.isRegister()) {
344 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
345 if (HII->isPredicated(*DefI))
348 bool WholeReg =
true;
352 return F != S.end() &&
I->end ==
F->end;
358 KillAt(
I->end, S.LaneMask);
364 KillAt(
I->end,
MRI->getMaxLaneMaskForVReg(Reg));
376 if (!
Op.isReg() || !
Op.isDef())
377 return {
false,
false };
380 return {
false,
false };
383 return {
A.any(),
A == SLM };
396 if (
D != Dest && MDT->dominates(
D, Dest))
401 for (
unsigned i = 0; i < Work.size(); ++i) {
407 for (
auto *
P :
B->predecessors())
418 for (
auto &Seg : Range) {
419 if (!Seg.start.isRegister())
421 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
423 if (HII->isPredicated(*DefI))
431 for (
auto &SI : PredDefs) {
433 auto P =
Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI);
434 if (
P.first !=
nullptr ||
P.second)
441 for (
auto &SI : PredDefs) {
457 if (Dominate(Defs, BB))
462 LIS->extendToIndices(Range, ExtTo, Undefs);
471 std::set<RegisterRef> DefRegs;
472 for (
auto &Seg : Range) {
473 if (!Seg.start.isRegister())
475 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
477 auto P = IsRegDef(Op);
478 if (
P.second && Seg.end.isDead()) {
480 }
else if (
P.first) {
489 for (
auto &Seg : Range) {
490 if (!Seg.start.isRegister() || !
Range.liveAt(Seg.start.getPrevSlot()))
492 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
493 if (!HII->isPredicated(*DefI))
498 std::map<RegisterRef,unsigned> ImpUses;
501 if (!
Op.isReg() || !DefRegs.count(Op))
507 ImpUses.insert({
Op, i});
521 for (
auto [R, DefIdx] : ImpUses) {
528void HexagonExpandCondsets::updateDeadFlags(
Register Reg) {
532 updateDeadsInRange(Reg, S.LaneMask, S);
533 LIS->shrinkToUses(S, Reg);
536 LIS->constructMainRangeFromSubranges(LI);
538 updateDeadsInRange(Reg,
MRI->getMaxLaneMaskForVReg(Reg), LI);
542void HexagonExpandCondsets::recalculateLiveInterval(
Register Reg) {
543 LIS->removeInterval(Reg);
544 LIS->createAndComputeVirtRegInterval(Reg);
548 LIS->RemoveMachineInstrFromMaps(
MI);
549 MI.eraseFromParent();
552void HexagonExpandCondsets::updateLiveness(
const std::set<Register> &RegSet,
553 bool Recalc,
bool UpdateKills,
555 UpdateKills |= UpdateDeads;
557 if (!
R.isVirtual()) {
565 recalculateLiveInterval(R);
567 MRI->clearKillFlags(R);
574 LIS->getInterval(R).verify();
578void HexagonExpandCondsets::distributeLiveIntervals(
579 const std::set<Register> &Regs) {
585 unsigned NumComp = EQC.Classify(LI);
591 for (
unsigned I = 1;
I < NumComp; ++
I) {
593 NewLIs.
push_back(&LIS->createEmptyInterval(NewR));
595 EQC.Distribute(LI, NewLIs.
begin(), *
MRI);
601unsigned HexagonExpandCondsets::getCondTfrOpcode(
const MachineOperand &SO,
606 if (RS.Reg.isVirtual()) {
608 assert(
VC->begin() !=
VC->end() &&
"Empty register class");
609 PhysR = *
VC->begin();
613 MCRegister PhysS = (RS.Sub == 0) ? PhysR :
TRI->getSubReg(PhysR, RS.Sub);
615 switch (
TRI->getRegSizeInBits(*RC)) {
617 return IfTrue ? Hexagon::A2_tfrt : Hexagon::A2_tfrf;
619 return IfTrue ? Hexagon::A2_tfrpt : Hexagon::A2_tfrpf;
632 return IfTrue ? Hexagon::C2_cmoveit : Hexagon::C2_cmoveif;
646 bool PredSense,
bool ReadUndef,
bool ImpUse) {
657 unsigned Opc = getCondTfrOpcode(
SrcOp, PredSense);
659 unsigned PredState =
getRegState(PredOp) & ~RegState::Kill;
664 if (RegisterRef(
SrcOp) == RegisterRef(DstR, DstSR))
665 SrcState &= ~RegState::Kill;
667 .
addReg(DstR, DstState, DstSR)
672 .
addReg(DstR, DstState, DstSR)
684 std::set<Register> &UpdRegs) {
685 if (TfrLimitActive) {
686 if (TfrCounter >= TfrLimit)
700 for (
auto &Op :
MI.operands()) {
702 UpdRegs.insert(
Op.getReg());
711 if (
ST.isReg() && SF.
isReg()) {
713 if (RT == RegisterRef(SF)) {
716 MI.setDesc(HII->get(TargetOpcode::COPY));
718 while (
MI.getNumOperands() > 1)
719 MI.removeOperand(
MI.getNumOperands()-1);
730 genCondTfrFor(ST, At, DR, DSR, MP,
true, ReadUndef,
false);
732 genCondTfrFor(SF, At, DR, DSR, MP,
false, ReadUndef,
true);
733 LIS->InsertMachineInstrInMaps(*TfrT);
734 LIS->InsertMachineInstrInMaps(*TfrF);
744 if (HII->isPredicated(*
MI) || !HII->isPredicable(*
MI))
746 if (
MI->hasUnmodeledSideEffects() ||
MI->mayStore())
750 for (
auto &Op :
MI->operands()) {
751 if (!
Op.isReg() || !
Op.isDef())
757 for (
auto &Mo :
MI->memoperands()) {
758 if (Mo->isVolatile() || Mo->isAtomic())
767MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
774 bool PredValid =
true;
780 if (PredValid && HII->isPredicated(*
MI)) {
781 if (
MI->readsRegister(PredR) && (
Cond != HII->isPredicatedTrue(*
MI)))
787 for (
auto &Op :
MI->operands()) {
788 if (!
Op.isReg() || !
Op.isDef())
791 if (RR.Reg == PredR) {
795 if (RR.Reg != RD.Reg)
800 if (RR.Sub == RD.Sub)
802 if (RR.Sub == 0 || RD.Sub == 0)
816bool HexagonExpandCondsets::canMoveOver(
MachineInstr &
MI, ReferenceMap &Defs,
817 ReferenceMap &
Uses) {
821 for (
auto &Op :
MI.operands()) {
828 if (!RR.Reg.isVirtual())
831 if (isRefInMap(RR, Defs, Exec_Then))
834 if (
Op.isDef() && isRefInMap(RR,
Uses, Exec_Then))
845 if (!IsLoad && !IsStore)
847 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
858 if (
MI.hasUnmodeledSideEffects())
860 bool L =
MI.mayLoad(), S =
MI.mayStore();
863 if (Ordered &&
MI.hasOrderedMemoryRef())
866 bool Conflict = (
L && IsStore) || S;
875void HexagonExpandCondsets::predicateAt(
const MachineOperand &DefOp,
879 std::set<Register> &UpdRegs) {
893 unsigned Opc =
MI.getOpcode();
894 unsigned PredOpc = HII->getCondOpcode(Opc, !
Cond);
896 unsigned Ox = 0, NP =
MI.getNumOperands();
919 LIS->InsertMachineInstrInMaps(*NewI);
923 UpdRegs.insert(
Op.getReg());
930void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
937 if (!HII->isPredicated(
MI))
939 if (!
MI.readsRegister(PredR) || (
Cond != HII->isPredicatedTrue(
MI)))
942 for (
auto &Op :
MI.operands()) {
943 if (!
Op.isReg() || RO != RegisterRef(Op))
946 Op.setSubReg(
RN.Sub);
948 assert(!
Op.isDef() &&
"Not expecting a def");
957 std::set<Register> &UpdRegs) {
961 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
981 if (!DefI || !isPredicable(DefI))
989 ReferenceMap
Uses, Defs;
995 bool PredValid =
true;
997 if (!
MI.modifiesRegister(PredR,
nullptr))
1008 unsigned Exec = Exec_Then | Exec_Else;
1009 if (PredValid && HII->isPredicated(
MI) &&
MI.readsRegister(PredR))
1010 Exec = (
Cond == HII->isPredicatedTrue(
MI)) ? Exec_Then : Exec_Else;
1012 for (
auto &Op :
MI.operands()) {
1022 RegisterRef RR =
Op;
1023 if (!RR.Reg.isVirtual())
1026 ReferenceMap &
Map =
Op.isDef() ? Defs :
Uses;
1027 if (
Op.isDef() &&
Op.isUndef()) {
1028 assert(RR.Sub &&
"Expecting a subregister on <def,read-undef>");
1034 addRefToMap(RR, Map, Exec);
1051 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT,
Uses, Exec_Else))
1053 RegisterRef RD = MD;
1060 bool CanUp = canMoveOver(TfrI, Defs,
Uses);
1061 bool CanDown = canMoveOver(*DefI, Defs,
Uses);
1065 if (!canMoveMemTo(*DefI, TfrI,
true))
1070 <<
", can move down: " << (CanDown ?
"yes\n" :
"no\n"));
1073 predicateAt(MD, *DefI, PastDefIt, MP,
Cond, UpdRegs);
1075 predicateAt(MD, *DefI, TfrIt, MP,
Cond, UpdRegs);
1080 renameInRange(RT, RD, PredR,
Cond, PastDefIt, TfrIt);
1081 UpdRegs.insert(RT.Reg);
1091 std::set<Register> &UpdRegs) {
1092 bool Changed =
false;
1094 unsigned Opc =
MI.getOpcode();
1095 if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
1096 bool Done = predicate(
MI, (Opc == Hexagon::A2_tfrt), UpdRegs);
1100 if (RegisterRef(
MI.getOperand(0)) == RegisterRef(
MI.getOperand(2))) {
1101 for (
auto &Op :
MI.operands()) {
1103 UpdRegs.insert(
Op.getReg());
1114bool HexagonExpandCondsets::isIntReg(RegisterRef RR,
unsigned &BW) {
1115 if (!RR.Reg.isVirtual())
1118 if (RC == &Hexagon::IntRegsRegClass) {
1122 if (RC == &Hexagon::DoubleRegsRegClass) {
1123 BW = (RR.Sub != 0) ? 32 : 64;
1129bool HexagonExpandCondsets::isIntraBlocks(
LiveInterval &LI) {
1132 if (!LR.start.isRegister())
1135 if (!LR.end.isRegister() && !LR.end.isDead())
1141bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef
R2) {
1142 if (CoaLimitActive) {
1143 if (CoaCounter >= CoaLimit)
1150 if (
MRI->isLiveIn(R1.Reg))
1152 if (
MRI->isLiveIn(
R2.Reg))
1164 << (Overlap ?
"overlap" :
"disjoint") <<
")\n "
1165 <<
printReg(R1.Reg,
TRI, R1.Sub) <<
" " << L1 <<
"\n "
1167 if (R1.Sub ||
R2.Sub)
1175 if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
1178 MRI->replaceRegWith(
R2.Reg, R1.Reg);
1184 VNInfo *NewVN, *OldVN =
I.valno;
1185 ValueInfoMap::iterator
F = VM.find(OldVN);
1186 if (
F == VM.end()) {
1187 NewVN = L1.
getNextValue(
I.valno->def, LIS->getVNInfoAllocator());
1188 VM.insert(std::make_pair(OldVN, NewVN));
1195 L2.removeSegment(*L2.begin());
1196 LIS->removeInterval(
R2.Reg);
1198 updateKillFlags(R1.Reg);
1208bool HexagonExpandCondsets::coalesceSegments(
1210 std::set<Register> &UpdRegs) {
1214 if (!S1.
isReg() && !S2.isReg())
1219 bool Changed =
false;
1221 RegisterRef RD = CI->getOperand(0);
1222 RegisterRef
RP = CI->getOperand(1);
1244 RegisterRef RS = S1;
1245 MachineInstr *RDef = getReachingDefForPred(RS, CI,
RP.Reg,
true);
1246 if (!RDef || !HII->isPredicable(*RDef)) {
1247 Done = coalesceRegisters(RD, RegisterRef(S1));
1249 UpdRegs.insert(RD.Reg);
1250 UpdRegs.insert(S1.
getReg());
1254 if (!
Done && S2.isReg()) {
1255 RegisterRef RS = S2;
1256 MachineInstr *RDef = getReachingDefForPred(RS, CI,
RP.Reg,
false);
1257 if (!RDef || !HII->isPredicable(*RDef)) {
1258 Done = coalesceRegisters(RD, RegisterRef(S2));
1260 UpdRegs.insert(RD.Reg);
1261 UpdRegs.insert(S2.getReg());
1270bool HexagonExpandCondsets::runOnMachineFunction(
MachineFunction &MF) {
1276 MDT = &getAnalysis<MachineDominatorTree>();
1277 LIS = &getAnalysis<LiveIntervals>();
1283 bool Changed =
false;
1284 std::set<Register> CoalUpd, PredUpd;
1287 for (
auto &
B : MF) {
1296 Changed |= coalesceSegments(
Condsets, CoalUpd);
1303 std::set<Register> KillUpd;
1306 if (
Op.isReg() &&
Op.isUse()) {
1307 if (!CoalUpd.count(
Op.getReg()))
1308 KillUpd.insert(
Op.getReg());
1314 LIS->print(
dbgs() <<
"After coalescing\n", MF.getFunction().getParent()));
1321 Changed |=
split(*
MI, PredUpd);
1331 LIS->print(
dbgs() <<
"After splitting\n", MF.getFunction().getParent()));
1338 Changed |= predicateInBlock(
B, PredUpd);
1340 MF.getFunction().getParent()));
1342 PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
1346 distributeLiveIntervals(PredUpd);
1350 LIS->print(
dbgs() <<
"After expand-condsets\n",
1351 MF.getFunction().getParent());
1361 return new HexagonExpandCondsets();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
SmallVector< MachineOperand, 4 > Cond
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static Error split(StringRef Str, char Separator, std::pair< StringRef, StringRef > &Split)
Checked version of split, to ensure mandatory subparts.
This file defines the DenseMap class.
Rewrite Partial Register Uses
static Expected< BitVector > expand(StringRef S, StringRef Original)
static cl::opt< unsigned > OptCoaLimit("expand-condsets-coa-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"))
static cl::opt< unsigned > OptTfrLimit("expand-condsets-tfr-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"))
expand Hexagon Expand Condsets
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static void updateLiveness(MachineFunction &MF)
Helper function to update the liveness information for the callee-saved registers.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
FunctionPass class - This class is used to implement most global optimizations.
Module * getParent()
Get the module that this global value is contained inside of...
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
void verify(const MachineRegisterInfo *MRI=nullptr) const
Walks the interval and assert if any invariants fail to hold.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
This class represents the liveness of a register, stack slot, etc.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Wrapper class representing physical registers. Should be passed by value.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
const MachineBasicBlock * getParent() const
unsigned getNumOperands() const
Retuns the total number of operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
iterator_range< mop_iterator > operands()
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
const MachineOperand & getOperand(unsigned i) const
void clearKillInfo()
Clears kill flags on all operands.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_FPImmediate
Floating-point immediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
A vector that has set insertion semantics.
bool insert(const value_type &X)
Insert a new element into the SetVector.
SlotIndex - An opaque wrapper around machine indexes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
VNInfo - Value Number Information.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isIntReg(unsigned Reg)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Undef
Value of the register doesn't matter.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
bool operator<(int64_t V1, const APSInt &V2)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
FunctionPass * createHexagonExpandCondsets()
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
void initializeHexagonExpandCondsetsPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
char & HexagonExpandCondsetsID
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
This represents a simple continuous liveness interval for a value.