LLVM  15.0.0git
PPCTargetTransformInfo.cpp
Go to the documentation of this file.
1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 #include "llvm/CodeGen/CostTable.h"
17 #include "llvm/IR/IntrinsicsPowerPC.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/KnownBits.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "ppctti"
27 
28 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
29 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
30 
31 // This is currently only used for the data prefetch pass
32 static cl::opt<unsigned>
33 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
34  cl::desc("The loop prefetch cache line size"));
35 
36 static cl::opt<bool>
37 EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false),
38  cl::desc("Enable using coldcc calling conv for cold "
39  "internal functions"));
40 
41 static cl::opt<bool>
42 LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false),
43  cl::desc("Do not add instruction count to lsr cost model"));
44 
45 // The latency of mtctr is only justified if there are more than 4
46 // comparisons that will be removed as a result.
47 static cl::opt<unsigned>
48 SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden,
49  cl::desc("Loops with a constant trip count smaller than "
50  "this value will not use the count register."));
51 
52 //===----------------------------------------------------------------------===//
53 //
54 // PPC cost model.
55 //
56 //===----------------------------------------------------------------------===//
57 
59 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) {
60  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
61  if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64)
62  return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ?
64  return TTI::PSK_Software;
65 }
66 
69  Intrinsic::ID IID = II.getIntrinsicID();
70  switch (IID) {
71  default:
72  break;
73  case Intrinsic::ppc_altivec_lvx:
74  case Intrinsic::ppc_altivec_lvxl:
75  // Turn PPC lvx -> load if the pointer is known aligned.
77  II.getArgOperand(0), Align(16), IC.getDataLayout(), &II,
78  &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) {
79  Value *Ptr = IC.Builder.CreateBitCast(
81  return new LoadInst(II.getType(), Ptr, "", false, Align(16));
82  }
83  break;
84  case Intrinsic::ppc_vsx_lxvw4x:
85  case Intrinsic::ppc_vsx_lxvd2x: {
86  // Turn PPC VSX loads into normal loads.
87  Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(0),
89  return new LoadInst(II.getType(), Ptr, Twine(""), false, Align(1));
90  }
91  case Intrinsic::ppc_altivec_stvx:
92  case Intrinsic::ppc_altivec_stvxl:
93  // Turn stvx -> store if the pointer is known aligned.
95  II.getArgOperand(1), Align(16), IC.getDataLayout(), &II,
96  &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) {
97  Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType());
98  Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy);
99  return new StoreInst(II.getArgOperand(0), Ptr, false, Align(16));
100  }
101  break;
102  case Intrinsic::ppc_vsx_stxvw4x:
103  case Intrinsic::ppc_vsx_stxvd2x: {
104  // Turn PPC VSX stores into normal stores.
105  Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType());
106  Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy);
107  return new StoreInst(II.getArgOperand(0), Ptr, false, Align(1));
108  }
109  case Intrinsic::ppc_altivec_vperm:
110  // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
111  // Note that ppc_altivec_vperm has a big-endian bias, so when creating
112  // a vectorshuffle for little endian, we must undo the transformation
113  // performed on vec_perm in altivec.h. That is, we must complement
114  // the permutation mask with respect to 31 and reverse the order of
115  // V1 and V2.
116  if (Constant *Mask = dyn_cast<Constant>(II.getArgOperand(2))) {
117  assert(cast<FixedVectorType>(Mask->getType())->getNumElements() == 16 &&
118  "Bad type for intrinsic!");
119 
120  // Check that all of the elements are integer constants or undefs.
121  bool AllEltsOk = true;
122  for (unsigned i = 0; i != 16; ++i) {
123  Constant *Elt = Mask->getAggregateElement(i);
124  if (!Elt || !(isa<ConstantInt>(Elt) || isa<UndefValue>(Elt))) {
125  AllEltsOk = false;
126  break;
127  }
128  }
129 
130  if (AllEltsOk) {
131  // Cast the input vectors to byte vectors.
132  Value *Op0 =
133  IC.Builder.CreateBitCast(II.getArgOperand(0), Mask->getType());
134  Value *Op1 =
135  IC.Builder.CreateBitCast(II.getArgOperand(1), Mask->getType());
136  Value *Result = UndefValue::get(Op0->getType());
137 
138  // Only extract each element once.
139  Value *ExtractedElts[32];
140  memset(ExtractedElts, 0, sizeof(ExtractedElts));
141 
142  for (unsigned i = 0; i != 16; ++i) {
143  if (isa<UndefValue>(Mask->getAggregateElement(i)))
144  continue;
145  unsigned Idx =
146  cast<ConstantInt>(Mask->getAggregateElement(i))->getZExtValue();
147  Idx &= 31; // Match the hardware behavior.
148  if (DL.isLittleEndian())
149  Idx = 31 - Idx;
150 
151  if (!ExtractedElts[Idx]) {
152  Value *Op0ToUse = (DL.isLittleEndian()) ? Op1 : Op0;
153  Value *Op1ToUse = (DL.isLittleEndian()) ? Op0 : Op1;
154  ExtractedElts[Idx] = IC.Builder.CreateExtractElement(
155  Idx < 16 ? Op0ToUse : Op1ToUse, IC.Builder.getInt32(Idx & 15));
156  }
157 
158  // Insert this value into the result vector.
159  Result = IC.Builder.CreateInsertElement(Result, ExtractedElts[Idx],
160  IC.Builder.getInt32(i));
161  }
162  return CastInst::Create(Instruction::BitCast, Result, II.getType());
163  }
164  }
165  break;
166  }
167  return None;
168 }
169 
173  return BaseT::getIntImmCost(Imm, Ty, CostKind);
174 
175  assert(Ty->isIntegerTy());
176 
177  unsigned BitSize = Ty->getPrimitiveSizeInBits();
178  if (BitSize == 0)
179  return ~0U;
180 
181  if (Imm == 0)
182  return TTI::TCC_Free;
183 
184  if (Imm.getBitWidth() <= 64) {
185  if (isInt<16>(Imm.getSExtValue()))
186  return TTI::TCC_Basic;
187 
188  if (isInt<32>(Imm.getSExtValue())) {
189  // A constant that can be materialized using lis.
190  if ((Imm.getZExtValue() & 0xFFFF) == 0)
191  return TTI::TCC_Basic;
192 
193  return 2 * TTI::TCC_Basic;
194  }
195  }
196 
197  return 4 * TTI::TCC_Basic;
198 }
199 
201  const APInt &Imm, Type *Ty,
204  return BaseT::getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
205 
206  assert(Ty->isIntegerTy());
207 
208  unsigned BitSize = Ty->getPrimitiveSizeInBits();
209  if (BitSize == 0)
210  return ~0U;
211 
212  switch (IID) {
213  default:
214  return TTI::TCC_Free;
215  case Intrinsic::sadd_with_overflow:
216  case Intrinsic::uadd_with_overflow:
217  case Intrinsic::ssub_with_overflow:
218  case Intrinsic::usub_with_overflow:
219  if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
220  return TTI::TCC_Free;
221  break;
222  case Intrinsic::experimental_stackmap:
223  if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
224  return TTI::TCC_Free;
225  break;
226  case Intrinsic::experimental_patchpoint_void:
227  case Intrinsic::experimental_patchpoint_i64:
228  if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
229  return TTI::TCC_Free;
230  break;
231  }
232  return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind);
233 }
234 
235 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
236  const APInt &Imm, Type *Ty,
238  Instruction *Inst) {
240  return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
241 
242  assert(Ty->isIntegerTy());
243 
244  unsigned BitSize = Ty->getPrimitiveSizeInBits();
245  if (BitSize == 0)
246  return ~0U;
247 
248  unsigned ImmIdx = ~0U;
249  bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
250  ZeroFree = false;
251  switch (Opcode) {
252  default:
253  return TTI::TCC_Free;
254  case Instruction::GetElementPtr:
255  // Always hoist the base address of a GetElementPtr. This prevents the
256  // creation of new constants for every base constant that gets constant
257  // folded with the offset.
258  if (Idx == 0)
259  return 2 * TTI::TCC_Basic;
260  return TTI::TCC_Free;
261  case Instruction::And:
262  RunFree = true; // (for the rotate-and-mask instructions)
264  case Instruction::Add:
265  case Instruction::Or:
266  case Instruction::Xor:
267  ShiftedFree = true;
269  case Instruction::Sub:
270  case Instruction::Mul:
271  case Instruction::Shl:
272  case Instruction::LShr:
273  case Instruction::AShr:
274  ImmIdx = 1;
275  break;
276  case Instruction::ICmp:
277  UnsignedFree = true;
278  ImmIdx = 1;
279  // Zero comparisons can use record-form instructions.
281  case Instruction::Select:
282  ZeroFree = true;
283  break;
284  case Instruction::PHI:
285  case Instruction::Call:
286  case Instruction::Ret:
287  case Instruction::Load:
288  case Instruction::Store:
289  break;
290  }
291 
292  if (ZeroFree && Imm == 0)
293  return TTI::TCC_Free;
294 
295  if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
296  if (isInt<16>(Imm.getSExtValue()))
297  return TTI::TCC_Free;
298 
299  if (RunFree) {
300  if (Imm.getBitWidth() <= 32 &&
301  (isShiftedMask_32(Imm.getZExtValue()) ||
303  return TTI::TCC_Free;
304 
305  if (ST->isPPC64() &&
306  (isShiftedMask_64(Imm.getZExtValue()) ||
308  return TTI::TCC_Free;
309  }
310 
311  if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
312  return TTI::TCC_Free;
313 
314  if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
315  return TTI::TCC_Free;
316  }
317 
318  return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind);
319 }
320 
321 // Check if the current Type is an MMA vector type. Valid MMA types are
322 // v256i1 and v512i1 respectively.
323 static bool isMMAType(Type *Ty) {
324  return Ty->isVectorTy() && (Ty->getScalarSizeInBits() == 1) &&
325  (Ty->getPrimitiveSizeInBits() > 128);
326 }
327 
331  // We already implement getCastInstrCost and getMemoryOpCost where we perform
332  // the vector adjustment there.
333  if (isa<CastInst>(U) || isa<LoadInst>(U) || isa<StoreInst>(U))
335 
336  if (U->getType()->isVectorTy()) {
337  // Instructions that need to be split should cost more.
338  std::pair<InstructionCost, MVT> LT =
339  TLI->getTypeLegalizationCost(DL, U->getType());
340  return LT.first * BaseT::getUserCost(U, Operands, CostKind);
341  }
342 
344 }
345 
346 // Determining the address of a TLS variable results in a function call in
347 // certain TLS models.
348 static bool memAddrUsesCTR(const Value *MemAddr, const PPCTargetMachine &TM,
350  // No need to traverse again if we already checked this operand.
351  if (!Visited.insert(MemAddr).second)
352  return false;
353  const auto *GV = dyn_cast<GlobalValue>(MemAddr);
354  if (!GV) {
355  // Recurse to check for constants that refer to TLS global variables.
356  if (const auto *CV = dyn_cast<Constant>(MemAddr))
357  for (const auto &CO : CV->operands())
358  if (memAddrUsesCTR(CO, TM, Visited))
359  return true;
360  return false;
361  }
362 
363  if (!GV->isThreadLocal())
364  return false;
365  TLSModel::Model Model = TM.getTLSModel(GV);
367 }
368 
369 bool PPCTTIImpl::mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo,
371  const PPCTargetMachine &TM = ST->getTargetMachine();
372 
373  // Loop through the inline asm constraints and look for something that
374  // clobbers ctr.
375  auto asmClobbersCTR = [](InlineAsm *IA) {
376  InlineAsm::ConstraintInfoVector CIV = IA->ParseConstraints();
377  for (const InlineAsm::ConstraintInfo &C : CIV) {
378  if (C.Type != InlineAsm::isInput)
379  for (const auto &Code : C.Codes)
380  if (StringRef(Code).equals_insensitive("{ctr}"))
381  return true;
382  }
383  return false;
384  };
385 
386  auto isLargeIntegerTy = [](bool Is32Bit, Type *Ty) {
387  if (IntegerType *ITy = dyn_cast<IntegerType>(Ty))
388  return ITy->getBitWidth() > (Is32Bit ? 32U : 64U);
389 
390  return false;
391  };
392 
393  auto supportedHalfPrecisionOp = [](Instruction *Inst) {
394  switch (Inst->getOpcode()) {
395  default:
396  return false;
397  case Instruction::FPTrunc:
398  case Instruction::FPExt:
399  case Instruction::Load:
400  case Instruction::Store:
401  case Instruction::FPToUI:
402  case Instruction::UIToFP:
403  case Instruction::FPToSI:
404  case Instruction::SIToFP:
405  return true;
406  }
407  };
408 
409  for (BasicBlock::iterator J = BB->begin(), JE = BB->end();
410  J != JE; ++J) {
411  // There are no direct operations on half precision so assume that
412  // anything with that type requires a call except for a few select
413  // operations with Power9.
414  if (Instruction *CurrInst = dyn_cast<Instruction>(J)) {
415  for (const auto &Op : CurrInst->operands()) {
416  if (Op->getType()->getScalarType()->isHalfTy() ||
417  CurrInst->getType()->getScalarType()->isHalfTy())
418  return !(ST->isISA3_0() && supportedHalfPrecisionOp(CurrInst));
419  }
420  }
421  if (CallInst *CI = dyn_cast<CallInst>(J)) {
422  // Inline ASM is okay, unless it clobbers the ctr register.
423  if (InlineAsm *IA = dyn_cast<InlineAsm>(CI->getCalledOperand())) {
424  if (asmClobbersCTR(IA))
425  return true;
426  continue;
427  }
428 
429  if (Function *F = CI->getCalledFunction()) {
430  // Most intrinsics don't become function calls, but some might.
431  // sin, cos, exp and log are always calls.
432  unsigned Opcode = 0;
433  if (F->getIntrinsicID() != Intrinsic::not_intrinsic) {
434  switch (F->getIntrinsicID()) {
435  default: continue;
436  // If we have a call to loop_decrement or set_loop_iterations,
437  // we're definitely using CTR.
438  case Intrinsic::set_loop_iterations:
439  case Intrinsic::loop_decrement:
440  return true;
441 
442  // Binary operations on 128-bit value will use CTR.
443  case Intrinsic::experimental_constrained_fadd:
444  case Intrinsic::experimental_constrained_fsub:
445  case Intrinsic::experimental_constrained_fmul:
446  case Intrinsic::experimental_constrained_fdiv:
447  case Intrinsic::experimental_constrained_frem:
448  if (F->getType()->getScalarType()->isFP128Ty() ||
449  F->getType()->getScalarType()->isPPC_FP128Ty())
450  return true;
451  break;
452 
453  case Intrinsic::experimental_constrained_fptosi:
454  case Intrinsic::experimental_constrained_fptoui:
455  case Intrinsic::experimental_constrained_sitofp:
456  case Intrinsic::experimental_constrained_uitofp: {
457  Type *SrcType = CI->getArgOperand(0)->getType()->getScalarType();
458  Type *DstType = CI->getType()->getScalarType();
459  if (SrcType->isPPC_FP128Ty() || DstType->isPPC_FP128Ty() ||
460  isLargeIntegerTy(!TM.isPPC64(), SrcType) ||
461  isLargeIntegerTy(!TM.isPPC64(), DstType))
462  return true;
463  break;
464  }
465 
466  // Exclude eh_sjlj_setjmp; we don't need to exclude eh_sjlj_longjmp
467  // because, although it does clobber the counter register, the
468  // control can't then return to inside the loop unless there is also
469  // an eh_sjlj_setjmp.
470  case Intrinsic::eh_sjlj_setjmp:
471 
472  case Intrinsic::memcpy:
473  case Intrinsic::memmove:
474  case Intrinsic::memset:
475  case Intrinsic::powi:
476  case Intrinsic::log:
477  case Intrinsic::log2:
478  case Intrinsic::log10:
479  case Intrinsic::exp:
480  case Intrinsic::exp2:
481  case Intrinsic::pow:
482  case Intrinsic::sin:
483  case Intrinsic::cos:
484  case Intrinsic::experimental_constrained_powi:
485  case Intrinsic::experimental_constrained_log:
486  case Intrinsic::experimental_constrained_log2:
487  case Intrinsic::experimental_constrained_log10:
488  case Intrinsic::experimental_constrained_exp:
489  case Intrinsic::experimental_constrained_exp2:
490  case Intrinsic::experimental_constrained_pow:
491  case Intrinsic::experimental_constrained_sin:
492  case Intrinsic::experimental_constrained_cos:
493  return true;
494  case Intrinsic::copysign:
495  if (CI->getArgOperand(0)->getType()->getScalarType()->
496  isPPC_FP128Ty())
497  return true;
498  else
499  continue; // ISD::FCOPYSIGN is never a library call.
500  case Intrinsic::fmuladd:
501  case Intrinsic::fma: Opcode = ISD::FMA; break;
502  case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
503  case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
504  case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
505  case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
506  case Intrinsic::rint: Opcode = ISD::FRINT; break;
507  case Intrinsic::lrint: Opcode = ISD::LRINT; break;
508  case Intrinsic::llrint: Opcode = ISD::LLRINT; break;
509  case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
510  case Intrinsic::round: Opcode = ISD::FROUND; break;
511  case Intrinsic::lround: Opcode = ISD::LROUND; break;
512  case Intrinsic::llround: Opcode = ISD::LLROUND; break;
513  case Intrinsic::minnum: Opcode = ISD::FMINNUM; break;
514  case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break;
515  case Intrinsic::experimental_constrained_fcmp:
516  Opcode = ISD::STRICT_FSETCC;
517  break;
518  case Intrinsic::experimental_constrained_fcmps:
519  Opcode = ISD::STRICT_FSETCCS;
520  break;
521  case Intrinsic::experimental_constrained_fma:
522  Opcode = ISD::STRICT_FMA;
523  break;
524  case Intrinsic::experimental_constrained_sqrt:
525  Opcode = ISD::STRICT_FSQRT;
526  break;
527  case Intrinsic::experimental_constrained_floor:
528  Opcode = ISD::STRICT_FFLOOR;
529  break;
530  case Intrinsic::experimental_constrained_ceil:
531  Opcode = ISD::STRICT_FCEIL;
532  break;
533  case Intrinsic::experimental_constrained_trunc:
534  Opcode = ISD::STRICT_FTRUNC;
535  break;
536  case Intrinsic::experimental_constrained_rint:
537  Opcode = ISD::STRICT_FRINT;
538  break;
539  case Intrinsic::experimental_constrained_lrint:
540  Opcode = ISD::STRICT_LRINT;
541  break;
542  case Intrinsic::experimental_constrained_llrint:
543  Opcode = ISD::STRICT_LLRINT;
544  break;
545  case Intrinsic::experimental_constrained_nearbyint:
546  Opcode = ISD::STRICT_FNEARBYINT;
547  break;
548  case Intrinsic::experimental_constrained_round:
549  Opcode = ISD::STRICT_FROUND;
550  break;
551  case Intrinsic::experimental_constrained_lround:
552  Opcode = ISD::STRICT_LROUND;
553  break;
554  case Intrinsic::experimental_constrained_llround:
555  Opcode = ISD::STRICT_LLROUND;
556  break;
557  case Intrinsic::experimental_constrained_minnum:
558  Opcode = ISD::STRICT_FMINNUM;
559  break;
560  case Intrinsic::experimental_constrained_maxnum:
561  Opcode = ISD::STRICT_FMAXNUM;
562  break;
563  case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break;
564  case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break;
565  }
566  }
567 
568  // PowerPC does not use [US]DIVREM or other library calls for
569  // operations on regular types which are not otherwise library calls
570  // (i.e. soft float or atomics). If adapting for targets that do,
571  // additional care is required here.
572 
573  LibFunc Func;
574  if (!F->hasLocalLinkage() && F->hasName() && LibInfo &&
575  LibInfo->getLibFunc(F->getName(), Func) &&
576  LibInfo->hasOptimizedCodeGen(Func)) {
577  // Non-read-only functions are never treated as intrinsics.
578  if (!CI->onlyReadsMemory())
579  return true;
580 
581  // Conversion happens only for FP calls.
582  if (!CI->getArgOperand(0)->getType()->isFloatingPointTy())
583  return true;
584 
585  switch (Func) {
586  default: return true;
587  case LibFunc_copysign:
588  case LibFunc_copysignf:
589  continue; // ISD::FCOPYSIGN is never a library call.
590  case LibFunc_copysignl:
591  return true;
592  case LibFunc_fabs:
593  case LibFunc_fabsf:
594  case LibFunc_fabsl:
595  continue; // ISD::FABS is never a library call.
596  case LibFunc_sqrt:
597  case LibFunc_sqrtf:
598  case LibFunc_sqrtl:
599  Opcode = ISD::FSQRT; break;
600  case LibFunc_floor:
601  case LibFunc_floorf:
602  case LibFunc_floorl:
603  Opcode = ISD::FFLOOR; break;
604  case LibFunc_nearbyint:
605  case LibFunc_nearbyintf:
606  case LibFunc_nearbyintl:
607  Opcode = ISD::FNEARBYINT; break;
608  case LibFunc_ceil:
609  case LibFunc_ceilf:
610  case LibFunc_ceill:
611  Opcode = ISD::FCEIL; break;
612  case LibFunc_rint:
613  case LibFunc_rintf:
614  case LibFunc_rintl:
615  Opcode = ISD::FRINT; break;
616  case LibFunc_round:
617  case LibFunc_roundf:
618  case LibFunc_roundl:
619  Opcode = ISD::FROUND; break;
620  case LibFunc_trunc:
621  case LibFunc_truncf:
622  case LibFunc_truncl:
623  Opcode = ISD::FTRUNC; break;
624  case LibFunc_fmin:
625  case LibFunc_fminf:
626  case LibFunc_fminl:
627  Opcode = ISD::FMINNUM; break;
628  case LibFunc_fmax:
629  case LibFunc_fmaxf:
630  case LibFunc_fmaxl:
631  Opcode = ISD::FMAXNUM; break;
632  }
633  }
634 
635  if (Opcode) {
636  EVT EVTy =
637  TLI->getValueType(DL, CI->getArgOperand(0)->getType(), true);
638 
639  if (EVTy == MVT::Other)
640  return true;
641 
642  if (TLI->isOperationLegalOrCustom(Opcode, EVTy))
643  continue;
644  else if (EVTy.isVector() &&
645  TLI->isOperationLegalOrCustom(Opcode, EVTy.getScalarType()))
646  continue;
647 
648  return true;
649  }
650  }
651 
652  return true;
653  } else if ((J->getType()->getScalarType()->isFP128Ty() ||
654  J->getType()->getScalarType()->isPPC_FP128Ty())) {
655  // Most operations on f128 or ppc_f128 values become calls.
656  return true;
657  } else if (isa<FCmpInst>(J) &&
658  J->getOperand(0)->getType()->getScalarType()->isFP128Ty()) {
659  return true;
660  } else if ((isa<FPTruncInst>(J) || isa<FPExtInst>(J)) &&
661  (cast<CastInst>(J)->getSrcTy()->getScalarType()->isFP128Ty() ||
662  cast<CastInst>(J)->getDestTy()->getScalarType()->isFP128Ty())) {
663  return true;
664  } else if (isa<UIToFPInst>(J) || isa<SIToFPInst>(J) ||
665  isa<FPToUIInst>(J) || isa<FPToSIInst>(J)) {
666  CastInst *CI = cast<CastInst>(J);
667  if (CI->getSrcTy()->getScalarType()->isPPC_FP128Ty() ||
668  CI->getDestTy()->getScalarType()->isPPC_FP128Ty() ||
669  isLargeIntegerTy(!TM.isPPC64(), CI->getSrcTy()->getScalarType()) ||
670  isLargeIntegerTy(!TM.isPPC64(), CI->getDestTy()->getScalarType()))
671  return true;
672  } else if (isLargeIntegerTy(!TM.isPPC64(),
673  J->getType()->getScalarType()) &&
674  (J->getOpcode() == Instruction::UDiv ||
675  J->getOpcode() == Instruction::SDiv ||
676  J->getOpcode() == Instruction::URem ||
677  J->getOpcode() == Instruction::SRem)) {
678  return true;
679  } else if (!TM.isPPC64() &&
680  isLargeIntegerTy(false, J->getType()->getScalarType()) &&
681  (J->getOpcode() == Instruction::Shl ||
682  J->getOpcode() == Instruction::AShr ||
683  J->getOpcode() == Instruction::LShr)) {
684  // Only on PPC32, for 128-bit integers (specifically not 64-bit
685  // integers), these might be runtime calls.
686  return true;
687  } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) {
688  // On PowerPC, indirect jumps use the counter register.
689  return true;
690  } else if (SwitchInst *SI = dyn_cast<SwitchInst>(J)) {
691  if (SI->getNumCases() + 1 >= (unsigned)TLI->getMinimumJumpTableEntries())
692  return true;
693  }
694 
695  // FREM is always a call.
696  if (J->getOpcode() == Instruction::FRem)
697  return true;
698 
699  if (ST->useSoftFloat()) {
700  switch(J->getOpcode()) {
701  case Instruction::FAdd:
702  case Instruction::FSub:
703  case Instruction::FMul:
704  case Instruction::FDiv:
705  case Instruction::FPTrunc:
706  case Instruction::FPExt:
707  case Instruction::FPToUI:
708  case Instruction::FPToSI:
709  case Instruction::UIToFP:
710  case Instruction::SIToFP:
711  case Instruction::FCmp:
712  return true;
713  }
714  }
715 
716  for (Value *Operand : J->operands())
717  if (memAddrUsesCTR(Operand, TM, Visited))
718  return true;
719  }
720 
721  return false;
722 }
723 
725  AssumptionCache &AC,
726  TargetLibraryInfo *LibInfo,
727  HardwareLoopInfo &HWLoopInfo) {
728  const PPCTargetMachine &TM = ST->getTargetMachine();
729  TargetSchedModel SchedModel;
730  SchedModel.init(ST);
731 
732  // Do not convert small short loops to CTR loop.
733  unsigned ConstTripCount = SE.getSmallConstantTripCount(L);
734  if (ConstTripCount && ConstTripCount < SmallCTRLoopThreshold) {
736  CodeMetrics::collectEphemeralValues(L, &AC, EphValues);
738  for (BasicBlock *BB : L->blocks())
739  Metrics.analyzeBasicBlock(BB, *this, EphValues);
740  // 6 is an approximate latency for the mtctr instruction.
741  if (Metrics.NumInsts <= (6 * SchedModel.getIssueWidth()))
742  return false;
743  }
744 
745  // We don't want to spill/restore the counter register, and so we don't
746  // want to use the counter register if the loop contains calls.
748  for (Loop::block_iterator I = L->block_begin(), IE = L->block_end();
749  I != IE; ++I)
750  if (mightUseCTR(*I, LibInfo, Visited))
751  return false;
752 
753  SmallVector<BasicBlock*, 4> ExitingBlocks;
754  L->getExitingBlocks(ExitingBlocks);
755 
756  // If there is an exit edge known to be frequently taken,
757  // we should not transform this loop.
758  for (auto &BB : ExitingBlocks) {
759  Instruction *TI = BB->getTerminator();
760  if (!TI) continue;
761 
762  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
763  uint64_t TrueWeight = 0, FalseWeight = 0;
764  if (!BI->isConditional() ||
765  !BI->extractProfMetadata(TrueWeight, FalseWeight))
766  continue;
767 
768  // If the exit path is more frequent than the loop path,
769  // we return here without further analysis for this loop.
770  bool TrueIsExit = !L->contains(BI->getSuccessor(0));
771  if (( TrueIsExit && FalseWeight < TrueWeight) ||
772  (!TrueIsExit && FalseWeight > TrueWeight))
773  return false;
774  }
775  }
776 
777  // If an exit block has a PHI that accesses a TLS variable as one of the
778  // incoming values from the loop, we cannot produce a CTR loop because the
779  // address for that value will be computed in the loop.
780  SmallVector<BasicBlock *, 4> ExitBlocks;
781  L->getExitBlocks(ExitBlocks);
782  for (auto &BB : ExitBlocks) {
783  for (auto &PHI : BB->phis()) {
784  for (int Idx = 0, EndIdx = PHI.getNumIncomingValues(); Idx < EndIdx;
785  Idx++) {
786  const BasicBlock *IncomingBB = PHI.getIncomingBlock(Idx);
787  const Value *IncomingValue = PHI.getIncomingValue(Idx);
788  if (L->contains(IncomingBB) &&
789  memAddrUsesCTR(IncomingValue, TM, Visited))
790  return false;
791  }
792  }
793  }
794 
795  LLVMContext &C = L->getHeader()->getContext();
796  HWLoopInfo.CountType = TM.isPPC64() ?
798  HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1);
799  return true;
800 }
801 
805  if (ST->getCPUDirective() == PPC::DIR_A2) {
806  // The A2 is in-order with a deep pipeline, and concatenation unrolling
807  // helps expose latency-hiding opportunities to the instruction scheduler.
808  UP.Partial = UP.Runtime = true;
809 
810  // We unroll a lot on the A2 (hundreds of instructions), and the benefits
811  // often outweigh the cost of a division to compute the trip count.
812  UP.AllowExpensiveTripCount = true;
813  }
814 
815  BaseT::getUnrollingPreferences(L, SE, UP, ORE);
816 }
817 
820  BaseT::getPeelingPreferences(L, SE, PP);
821 }
822 // This function returns true to allow using coldcc calling convention.
823 // Returning true results in coldcc being used for functions which are cold at
824 // all call sites when the callers of the functions are not calling any other
825 // non coldcc functions.
827  return EnablePPCColdCC;
828 }
829 
830 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) {
831  // On the A2, always unroll aggressively.
832  if (ST->getCPUDirective() == PPC::DIR_A2)
833  return true;
834 
835  return LoopHasReductions;
836 }
837 
839 PPCTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
841  Options.LoadSizes = {8, 4, 2, 1};
842  Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
843  return Options;
844 }
845 
847  return true;
848 }
849 
850 unsigned PPCTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
851  assert(ClassID == GPRRC || ClassID == FPRRC ||
852  ClassID == VRRC || ClassID == VSXRC);
853  if (ST->hasVSX()) {
854  assert(ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC);
855  return ClassID == VSXRC ? 64 : 32;
856  }
857  assert(ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC);
858  return 32;
859 }
860 
861 unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const {
862  if (Vector)
863  return ST->hasVSX() ? VSXRC : VRRC;
864  else if (Ty && (Ty->getScalarType()->isFloatTy() ||
865  Ty->getScalarType()->isDoubleTy()))
866  return ST->hasVSX() ? VSXRC : FPRRC;
867  else if (Ty && (Ty->getScalarType()->isFP128Ty() ||
868  Ty->getScalarType()->isPPC_FP128Ty()))
869  return VRRC;
870  else if (Ty && Ty->getScalarType()->isHalfTy())
871  return VSXRC;
872  else
873  return GPRRC;
874 }
875 
876 const char* PPCTTIImpl::getRegisterClassName(unsigned ClassID) const {
877 
878  switch (ClassID) {
879  default:
880  llvm_unreachable("unknown register class");
881  return "PPC::unknown register class";
882  case GPRRC: return "PPC::GPRRC";
883  case FPRRC: return "PPC::FPRRC";
884  case VRRC: return "PPC::VRRC";
885  case VSXRC: return "PPC::VSXRC";
886  }
887 }
888 
889 TypeSize
891  switch (K) {
893  return TypeSize::getFixed(ST->isPPC64() ? 64 : 32);
895  return TypeSize::getFixed(ST->hasAltivec() ? 128 : 0);
897  return TypeSize::getScalable(0);
898  }
899 
900  llvm_unreachable("Unsupported register kind");
901 }
902 
904  // Check first if the user specified a custom line size.
905  if (CacheLineSize.getNumOccurrences() > 0)
906  return CacheLineSize;
907 
908  // Starting with P7 we have a cache line size of 128.
909  unsigned Directive = ST->getCPUDirective();
910  // Assume that Future CPU has the same cache line size as the others.
914  return 128;
915 
916  // On other processors return a default of 64 bytes.
917  return 64;
918 }
919 
921  return 300;
922 }
923 
924 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
925  unsigned Directive = ST->getCPUDirective();
926  // The 440 has no SIMD support, but floating-point instructions
927  // have a 5-cycle latency, so unroll by 5x for latency hiding.
928  if (Directive == PPC::DIR_440)
929  return 5;
930 
931  // The A2 has no SIMD support, but floating-point instructions
932  // have a 6-cycle latency, so unroll by 6x for latency hiding.
933  if (Directive == PPC::DIR_A2)
934  return 6;
935 
936  // FIXME: For lack of any better information, do no harm...
938  return 1;
939 
940  // For P7 and P8, floating-point instructions have a 6-cycle latency and
941  // there are two execution units, so unroll by 12x for latency hiding.
942  // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
943  // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
944  // Assume that future is the same as the others.
948  return 12;
949 
950  // For most things, modern systems have two execution units (and
951  // out-of-order execution).
952  return 2;
953 }
954 
955 // Returns a cost adjustment factor to adjust the cost of vector instructions
956 // on targets which there is overlap between the vector and scalar units,
957 // thereby reducing the overall throughput of vector code wrt. scalar code.
958 // An invalid instruction cost is returned if the type is an MMA vector type.
960  Type *Ty1, Type *Ty2) {
961  // If the vector type is of an MMA type (v256i1, v512i1), an invalid
962  // instruction cost is returned. This is to signify to other cost computing
963  // functions to return the maximum instruction cost in order to prevent any
964  // opportunities for the optimizer to produce MMA types within the IR.
965  if (isMMAType(Ty1))
967 
968  if (!ST->vectorsUseTwoUnits() || !Ty1->isVectorTy())
969  return InstructionCost(1);
970 
971  std::pair<InstructionCost, MVT> LT1 = TLI->getTypeLegalizationCost(DL, Ty1);
972  // If type legalization involves splitting the vector, we don't want to
973  // double the cost at every step - only the last step.
974  if (LT1.first != 1 || !LT1.second.isVector())
975  return InstructionCost(1);
976 
977  int ISD = TLI->InstructionOpcodeToISD(Opcode);
978  if (TLI->isOperationExpand(ISD, LT1.second))
979  return InstructionCost(1);
980 
981  if (Ty2) {
982  std::pair<InstructionCost, MVT> LT2 = TLI->getTypeLegalizationCost(DL, Ty2);
983  if (LT2.first != 1 || !LT2.second.isVector())
984  return InstructionCost(1);
985  }
986 
987  return InstructionCost(2);
988 }
989 
991  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
993  TTI::OperandValueProperties Opd1PropInfo,
995  const Instruction *CxtI) {
996  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
997 
998  InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Ty, nullptr);
999  if (!CostFactor.isValid())
1000  return InstructionCost::getMax();
1001 
1002  // TODO: Handle more cost kinds.
1004  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
1005  Op2Info, Opd1PropInfo,
1006  Opd2PropInfo, Args, CxtI);
1007 
1008  // Fallback to the default implementation.
1010  Opcode, Ty, CostKind, Op1Info, Op2Info, Opd1PropInfo, Opd2PropInfo);
1011  return Cost * CostFactor;
1012 }
1013 
1015  ArrayRef<int> Mask, int Index,
1016  Type *SubTp,
1018 
1019  InstructionCost CostFactor =
1020  vectorCostAdjustmentFactor(Instruction::ShuffleVector, Tp, nullptr);
1021  if (!CostFactor.isValid())
1022  return InstructionCost::getMax();
1023 
1024  // Legalize the type.
1025  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
1026 
1027  // PPC, for both Altivec/VSX, support cheap arbitrary permutations
1028  // (at least in the sense that there need only be one non-loop-invariant
1029  // instruction). We need one such shuffle instruction for each actual
1030  // register (this is not true for arbitrary shuffles, but is true for the
1031  // structured types of shuffles covered by TTI::ShuffleKind).
1032  return LT.first * CostFactor;
1033 }
1034 
1037  const Instruction *I) {
1039  return Opcode == Instruction::PHI ? 0 : 1;
1040  // Branches are assumed to be predicted.
1041  return 0;
1042 }
1043 
1045  Type *Src,
1048  const Instruction *I) {
1049  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
1050 
1051  InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Dst, Src);
1052  if (!CostFactor.isValid())
1053  return InstructionCost::getMax();
1054 
1055  InstructionCost Cost =
1056  BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1057  Cost *= CostFactor;
1058  // TODO: Allow non-throughput costs that aren't binary.
1060  return Cost == 0 ? 0 : 1;
1061  return Cost;
1062 }
1063 
1065  Type *CondTy,
1066  CmpInst::Predicate VecPred,
1068  const Instruction *I) {
1069  InstructionCost CostFactor =
1070  vectorCostAdjustmentFactor(Opcode, ValTy, nullptr);
1071  if (!CostFactor.isValid())
1072  return InstructionCost::getMax();
1073 
1074  InstructionCost Cost =
1075  BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
1076  // TODO: Handle other cost kinds.
1078  return Cost;
1079  return Cost * CostFactor;
1080 }
1081 
1083  unsigned Index) {
1084  assert(Val->isVectorTy() && "This must be a vector type");
1085 
1086  int ISD = TLI->InstructionOpcodeToISD(Opcode);
1087  assert(ISD && "Invalid opcode");
1088 
1089  InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Val, nullptr);
1090  if (!CostFactor.isValid())
1091  return InstructionCost::getMax();
1092 
1093  InstructionCost Cost = BaseT::getVectorInstrCost(Opcode, Val, Index);
1094  Cost *= CostFactor;
1095 
1096  if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
1097  // Double-precision scalars are already located in index #0 (or #1 if LE).
1098  if (ISD == ISD::EXTRACT_VECTOR_ELT &&
1099  Index == (ST->isLittleEndian() ? 1 : 0))
1100  return 0;
1101 
1102  return Cost;
1103 
1104  } else if (Val->getScalarType()->isIntegerTy() && Index != -1U) {
1105  if (ST->hasP9Altivec()) {
1106  if (ISD == ISD::INSERT_VECTOR_ELT)
1107  // A move-to VSR and a permute/insert. Assume vector operation cost
1108  // for both (cost will be 2x on P9).
1109  return 2 * CostFactor;
1110 
1111  // It's an extract. Maybe we can do a cheap move-from VSR.
1112  unsigned EltSize = Val->getScalarSizeInBits();
1113  if (EltSize == 64) {
1114  unsigned MfvsrdIndex = ST->isLittleEndian() ? 1 : 0;
1115  if (Index == MfvsrdIndex)
1116  return 1;
1117  } else if (EltSize == 32) {
1118  unsigned MfvsrwzIndex = ST->isLittleEndian() ? 2 : 1;
1119  if (Index == MfvsrwzIndex)
1120  return 1;
1121  }
1122 
1123  // We need a vector extract (or mfvsrld). Assume vector operation cost.
1124  // The cost of the load constant for a vector extract is disregarded
1125  // (invariant, easily schedulable).
1126  return CostFactor;
1127 
1128  } else if (ST->hasDirectMove())
1129  // Assume permute has standard cost.
1130  // Assume move-to/move-from VSR have 2x standard cost.
1131  return 3;
1132  }
1133 
1134  // Estimated cost of a load-hit-store delay. This was obtained
1135  // experimentally as a minimum needed to prevent unprofitable
1136  // vectorization for the paq8p benchmark. It may need to be
1137  // raised further if other unprofitable cases remain.
1138  unsigned LHSPenalty = 2;
1139  if (ISD == ISD::INSERT_VECTOR_ELT)
1140  LHSPenalty += 7;
1141 
1142  // Vector element insert/extract with Altivec is very expensive,
1143  // because they require store and reload with the attendant
1144  // processor stall for load-hit-store. Until VSX is available,
1145  // these need to be estimated as very costly.
1146  if (ISD == ISD::EXTRACT_VECTOR_ELT ||
1147  ISD == ISD::INSERT_VECTOR_ELT)
1148  return LHSPenalty + Cost;
1149 
1150  return Cost;
1151 }
1152 
1154  MaybeAlign Alignment,
1155  unsigned AddressSpace,
1157  const Instruction *I) {
1158 
1159  InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Src, nullptr);
1160  if (!CostFactor.isValid())
1161  return InstructionCost::getMax();
1162 
1163  if (TLI->getValueType(DL, Src, true) == MVT::Other)
1164  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
1165  CostKind);
1166  // Legalize the type.
1167  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
1168  assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
1169  "Invalid Opcode");
1170 
1171  InstructionCost Cost =
1172  BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
1173  // TODO: Handle other cost kinds.
1175  return Cost;
1176 
1177  Cost *= CostFactor;
1178 
1179  bool IsAltivecType = ST->hasAltivec() &&
1180  (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
1181  LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
1182  bool IsVSXType = ST->hasVSX() &&
1183  (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
1184 
1185  // VSX has 32b/64b load instructions. Legalization can handle loading of
1186  // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and
1187  // PPCTargetLowering can't compute the cost appropriately. So here we
1188  // explicitly check this case.
1189  unsigned MemBytes = Src->getPrimitiveSizeInBits();
1190  if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType &&
1191  (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32)))
1192  return 1;
1193 
1194  // Aligned loads and stores are easy.
1195  unsigned SrcBytes = LT.second.getStoreSize();
1196  if (!SrcBytes || !Alignment || *Alignment >= SrcBytes)
1197  return Cost;
1198 
1199  // If we can use the permutation-based load sequence, then this is also
1200  // relatively cheap (not counting loop-invariant instructions): one load plus
1201  // one permute (the last load in a series has extra cost, but we're
1202  // neglecting that here). Note that on the P7, we could do unaligned loads
1203  // for Altivec types using the VSX instructions, but that's more expensive
1204  // than using the permutation-based load sequence. On the P8, that's no
1205  // longer true.
1206  if (Opcode == Instruction::Load && (!ST->hasP8Vector() && IsAltivecType) &&
1207  *Alignment >= LT.second.getScalarType().getStoreSize())
1208  return Cost + LT.first; // Add the cost of the permutations.
1209 
1210  // For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the
1211  // P7, unaligned vector loads are more expensive than the permutation-based
1212  // load sequence, so that might be used instead, but regardless, the net cost
1213  // is about the same (not counting loop-invariant instructions).
1214  if (IsVSXType || (ST->hasVSX() && IsAltivecType))
1215  return Cost;
1216 
1217  // Newer PPC supports unaligned memory access.
1218  if (TLI->allowsMisalignedMemoryAccesses(LT.second, 0))
1219  return Cost;
1220 
1221  // PPC in general does not support unaligned loads and stores. They'll need
1222  // to be decomposed based on the alignment factor.
1223 
1224  // Add the cost of each scalar load or store.
1225  assert(Alignment);
1226  Cost += LT.first * ((SrcBytes / Alignment->value()) - 1);
1227 
1228  // For a vector type, there is also scalarization overhead (only for
1229  // stores, loads are expanded using the vector-load + permutation sequence,
1230  // which is much less expensive).
1231  if (Src->isVectorTy() && Opcode == Instruction::Store)
1232  for (int i = 0, e = cast<FixedVectorType>(Src)->getNumElements(); i < e;
1233  ++i)
1234  Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
1235 
1236  return Cost;
1237 }
1238 
1240  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1241  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1242  bool UseMaskForCond, bool UseMaskForGaps) {
1243  InstructionCost CostFactor =
1244  vectorCostAdjustmentFactor(Opcode, VecTy, nullptr);
1245  if (!CostFactor.isValid())
1246  return InstructionCost::getMax();
1247 
1248  if (UseMaskForCond || UseMaskForGaps)
1249  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
1250  Alignment, AddressSpace, CostKind,
1251  UseMaskForCond, UseMaskForGaps);
1252 
1253  assert(isa<VectorType>(VecTy) &&
1254  "Expect a vector type for interleaved memory op");
1255 
1256  // Legalize the type.
1257  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, VecTy);
1258 
1259  // Firstly, the cost of load/store operation.
1260  InstructionCost Cost = getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment),
1262 
1263  // PPC, for both Altivec/VSX, support cheap arbitrary permutations
1264  // (at least in the sense that there need only be one non-loop-invariant
1265  // instruction). For each result vector, we need one shuffle per incoming
1266  // vector (except that the first shuffle can take two incoming vectors
1267  // because it does not need to take itself).
1268  Cost += Factor*(LT.first-1);
1269 
1270  return Cost;
1271 }
1272 
1277 }
1278 
1280  const Function *Callee,
1281  const ArrayRef<Type *> &Types) const {
1282 
1283  // We need to ensure that argument promotion does not
1284  // attempt to promote pointers to MMA types (__vector_pair
1285  // and __vector_quad) since these types explicitly cannot be
1286  // passed as arguments. Both of these types are larger than
1287  // the 128-bit Altivec vectors and have a scalar size of 1 bit.
1288  if (!BaseT::areTypesABICompatible(Caller, Callee, Types))
1289  return false;
1290 
1291  return llvm::none_of(Types, [](Type *Ty) {
1292  if (Ty->isSized())
1293  return Ty->isIntOrIntVectorTy(1) && Ty->getPrimitiveSizeInBits() > 128;
1294  return false;
1295  });
1296 }
1297 
1299  LoopInfo *LI, DominatorTree *DT,
1300  AssumptionCache *AC, TargetLibraryInfo *LibInfo) {
1301  // Process nested loops first.
1302  for (Loop *I : *L)
1303  if (canSaveCmp(I, BI, SE, LI, DT, AC, LibInfo))
1304  return false; // Stop search.
1305 
1306  HardwareLoopInfo HWLoopInfo(L);
1307 
1308  if (!HWLoopInfo.canAnalyze(*LI))
1309  return false;
1310 
1311  if (!isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo))
1312  return false;
1313 
1314  if (!HWLoopInfo.isHardwareLoopCandidate(*SE, *LI, *DT))
1315  return false;
1316 
1317  *BI = HWLoopInfo.ExitBranch;
1318  return true;
1319 }
1320 
1323  // PowerPC default behaviour here is "instruction number 1st priority".
1324  // If LsrNoInsnsCost is set, call default implementation.
1325  if (!LsrNoInsnsCost)
1326  return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls,
1327  C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
1328  std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls,
1329  C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost);
1330  else
1332 }
1333 
1335  return false;
1336 }
1337 
1339  const PPCTargetMachine &TM = ST->getTargetMachine();
1340  // XCOFF hasn't implemented lowerRelativeReference, disable non-ELF for now.
1341  if (!TM.isELFv2ABI())
1342  return false;
1344 }
1345 
1348  switch (Inst->getIntrinsicID()) {
1349  case Intrinsic::ppc_altivec_lvx:
1350  case Intrinsic::ppc_altivec_lvxl:
1351  case Intrinsic::ppc_altivec_lvebx:
1352  case Intrinsic::ppc_altivec_lvehx:
1353  case Intrinsic::ppc_altivec_lvewx:
1354  case Intrinsic::ppc_vsx_lxvd2x:
1355  case Intrinsic::ppc_vsx_lxvw4x:
1356  case Intrinsic::ppc_vsx_lxvd2x_be:
1357  case Intrinsic::ppc_vsx_lxvw4x_be:
1358  case Intrinsic::ppc_vsx_lxvl:
1359  case Intrinsic::ppc_vsx_lxvll:
1360  case Intrinsic::ppc_vsx_lxvp: {
1361  Info.PtrVal = Inst->getArgOperand(0);
1362  Info.ReadMem = true;
1363  Info.WriteMem = false;
1364  return true;
1365  }
1366  case Intrinsic::ppc_altivec_stvx:
1367  case Intrinsic::ppc_altivec_stvxl:
1368  case Intrinsic::ppc_altivec_stvebx:
1369  case Intrinsic::ppc_altivec_stvehx:
1370  case Intrinsic::ppc_altivec_stvewx:
1371  case Intrinsic::ppc_vsx_stxvd2x:
1372  case Intrinsic::ppc_vsx_stxvw4x:
1373  case Intrinsic::ppc_vsx_stxvd2x_be:
1374  case Intrinsic::ppc_vsx_stxvw4x_be:
1375  case Intrinsic::ppc_vsx_stxvl:
1376  case Intrinsic::ppc_vsx_stxvll:
1377  case Intrinsic::ppc_vsx_stxvp: {
1378  Info.PtrVal = Inst->getArgOperand(1);
1379  Info.ReadMem = false;
1380  Info.WriteMem = true;
1381  return true;
1382  }
1383  default:
1384  break;
1385  }
1386 
1387  return false;
1388 }
1389 
1390 bool PPCTTIImpl::hasActiveVectorLength(unsigned Opcode, Type *DataType,
1391  Align Alignment) const {
1392  // Only load and stores instructions can have variable vector length on Power.
1393  if (Opcode != Instruction::Load && Opcode != Instruction::Store)
1394  return false;
1395  // Loads/stores with length instructions use bits 0-7 of the GPR operand and
1396  // therefore cannot be used in 32-bit mode.
1397  if ((!ST->hasP9Vector() && !ST->hasP10Vector()) || !ST->isPPC64())
1398  return false;
1399  if (isa<FixedVectorType>(DataType)) {
1400  unsigned VecWidth = DataType->getPrimitiveSizeInBits();
1401  return VecWidth == 128;
1402  }
1403  Type *ScalarTy = DataType->getScalarType();
1404 
1405  if (ScalarTy->isPointerTy())
1406  return true;
1407 
1408  if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
1409  return true;
1410 
1411  if (!ScalarTy->isIntegerTy())
1412  return false;
1413 
1414  unsigned IntWidth = ScalarTy->getIntegerBitWidth();
1415  return IntWidth == 8 || IntWidth == 16 || IntWidth == 32 || IntWidth == 64;
1416 }
1417 
1419  Align Alignment,
1420  unsigned AddressSpace,
1422  const Instruction *I) {
1423  InstructionCost Cost = BaseT::getVPMemoryOpCost(Opcode, Src, Alignment,
1424  AddressSpace, CostKind, I);
1425  if (TLI->getValueType(DL, Src, true) == MVT::Other)
1426  return Cost;
1427  // TODO: Handle other cost kinds.
1429  return Cost;
1430 
1431  assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
1432  "Invalid Opcode");
1433 
1434  auto *SrcVTy = dyn_cast<FixedVectorType>(Src);
1435  assert(SrcVTy && "Expected a vector type for VP memory operations");
1436 
1437  if (hasActiveVectorLength(Opcode, Src, Alignment)) {
1438  std::pair<InstructionCost, MVT> LT =
1439  TLI->getTypeLegalizationCost(DL, SrcVTy);
1440 
1441  InstructionCost CostFactor =
1442  vectorCostAdjustmentFactor(Opcode, Src, nullptr);
1443  if (!CostFactor.isValid())
1444  return InstructionCost::getMax();
1445 
1446  InstructionCost Cost = LT.first * CostFactor;
1447  assert(Cost.isValid() && "Expected valid cost");
1448 
1449  // On P9 but not on P10, if the op is misaligned then it will cause a
1450  // pipeline flush. Otherwise the VSX masked memops cost the same as unmasked
1451  // ones.
1452  const Align DesiredAlignment(16);
1453  if (Alignment >= DesiredAlignment || ST->getCPUDirective() != PPC::DIR_PWR9)
1454  return Cost;
1455 
1456  // Since alignment may be under estimated, we try to compute the probability
1457  // that the actual address is aligned to the desired boundary. For example
1458  // an 8-byte aligned load is assumed to be actually 16-byte aligned half the
1459  // time, while a 4-byte aligned load has a 25% chance of being 16-byte
1460  // aligned.
1461  float AlignmentProb = ((float)Alignment.value()) / DesiredAlignment.value();
1462  float MisalignmentProb = 1.0 - AlignmentProb;
1463  return (MisalignmentProb * P9PipelineFlushEstimate) +
1464  (AlignmentProb * *Cost.getValue());
1465  }
1466 
1467  // Usually we should not get to this point, but the following is an attempt to
1468  // model the cost of legalization. Currently we can only lower intrinsics with
1469  // evl but no mask, on Power 9/10. Otherwise, we must scalarize.
1470  return getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
1471 }
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:594
llvm::PPCTTIImpl::VSXRC
@ VSXRC
Definition: PPCTargetTransformInfo.h:94
llvm::ISD::STRICT_FSETCC
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
Definition: ISDOpcodes.h:475
llvm::Type::isSized
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
llvm::BasicTTIImplBase< PPCTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:487
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm::PPCSubtarget::hasPOPCNTD
POPCNTDKind hasPOPCNTD() const
Definition: PPCSubtarget.h:357
llvm::PPCTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: PPCTargetTransformInfo.cpp:802
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:420
llvm::BasicTTIImplBase< PPCTTIImpl >::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: BasicTTIImpl.h:462
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:332
llvm::ISD::STRICT_FSQRT
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:411
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1619
llvm::LoopBase::getExitBlocks
void getExitBlocks(SmallVectorImpl< BlockT * > &ExitBlocks) const
Return all of the successor blocks of this loop.
Definition: LoopInfoImpl.h:61
llvm::PPCTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: PPCTargetTransformInfo.cpp:924
llvm::PPCTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: PPCTargetTransformInfo.cpp:170
llvm::HardwareLoopInfo::LoopDecrement
Value * LoopDecrement
Definition: TargetTransformInfo.h:102
llvm::InstructionCost::getValue
Optional< CostType > getValue() const
This function is intended to be used as sparingly as possible, since the class provides the full rang...
Definition: InstructionCost.h:87
InstCombiner.h
llvm::PPCTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: PPCTargetTransformInfo.cpp:990
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::BasicBlock::iterator
InstListType::iterator iterator
Instruction iterators...
Definition: BasicBlock.h:87
llvm::InstCombiner::getDominatorTree
DominatorTree & getDominatorTree() const
Definition: InstCombiner.h:370
llvm::InlineAsm::ConstraintInfoVector
std::vector< ConstraintInfo > ConstraintInfoVector
Definition: InlineAsm.h:118
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:218
ceil
We have fiadd patterns now but the followings have the same cost and complexity We need a way to specify the later is more profitable def def The FP stackifier should handle simple permutates to reduce number of shuffle e g ceil
Definition: README-FPStack.txt:54
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:936
llvm::ISD::STRICT_FMAXNUM
@ STRICT_FMAXNUM
Definition: ISDOpcodes.h:423
llvm::PPCTTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: PPCTargetTransformInfo.cpp:200
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:122
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:594
llvm::ISD::STRICT_FMINNUM
@ STRICT_FMINNUM
Definition: ISDOpcodes.h:424
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::TargetTransformInfoImplCRTPBase< PPCTTIImpl >::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:970
llvm::PPC::DIR_PWR_FUTURE
@ DIR_PWR_FUTURE
Definition: PPCSubtarget.h:64
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:309
llvm::TLSModel::GeneralDynamic
@ GeneralDynamic
Definition: CodeGen.h:43
llvm::PPCTTIImpl::isLSRCostLess
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2)
Definition: PPCTargetTransformInfo.cpp:1321
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::InstCombiner::Builder
BuilderTy & Builder
Definition: InstCombiner.h:58
llvm::CodeMetrics
Utility to calculate the size and a few similar metrics for a set of basic blocks.
Definition: CodeMetrics.h:30
llvm::PPCTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: PPCTargetTransformInfo.cpp:1044
llvm::TargetTransformInfoImplBase::isLSRCostLess
bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const
Definition: TargetTransformInfoImpl.h:213
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1490
llvm::PPCSubtarget::hasP8Vector
bool hasP8Vector() const
Definition: PPCSubtarget.h:281
llvm::PPCSubtarget::isLittleEndian
bool isLittleEndian() const
Definition: PPCSubtarget.h:261
llvm::CastInst::Create
static CastInst * Create(Instruction::CastOps, Value *S, Type *Ty, const Twine &Name="", Instruction *InsertBefore=nullptr)
Provides a way to construct any of the CastInst subclasses using an opcode instead of the subclass's ...
Definition: Instructions.cpp:3180
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:919
llvm::PPCSubtarget::hasVSX
bool hasVSX() const
Definition: PPCSubtarget.h:279
llvm::BasicTTIImplBase< PPCTTIImpl >::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: BasicTTIImpl.h:777
Local.h
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
DisablePPCConstHoist
static cl::opt< bool > DisablePPCConstHoist("disable-ppc-constant-hoisting", cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden)
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:99
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:482
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:422
llvm::isShiftedMask_32
constexpr bool isShiftedMask_32(uint32_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (32 bit ver...
Definition: MathExtras.h:479
llvm::PPCSubtarget::hasP9Vector
bool hasP9Vector() const
Definition: PPCSubtarget.h:284
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:98
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:483
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1423
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:537
llvm::getOrEnforceKnownAlignment
Align getOrEnforceKnownAlignment(Value *V, MaybeAlign PrefAlign, const DataLayout &DL, const Instruction *CxtI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr)
Try to ensure that the alignment of V is at least PrefAlign bytes.
Definition: Local.cpp:1356
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::Optional
Definition: APInt.h:33
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::PPCTTIImpl::vectorCostAdjustmentFactor
InstructionCost vectorCostAdjustmentFactor(unsigned Opcode, Type *Ty1, Type *Ty2)
Definition: PPCTargetTransformInfo.cpp:959
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::PPCTTIImpl::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
Definition: PPCTargetTransformInfo.cpp:724
llvm::PPCSubtarget::getTargetMachine
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:226
llvm::IRBuilderBase::CreateInsertElement
Value * CreateInsertElement(Type *VecTy, Value *NewElt, Value *Idx, const Twine &Name="")
Definition: IRBuilder.h:2289
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1808
llvm::PPCTTIImpl::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: PPCTargetTransformInfo.cpp:876
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::Intrinsic::not_intrinsic
@ not_intrinsic
Definition: Intrinsics.h:45
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:376
llvm::PPCSubtarget::vectorsUseTwoUnits
bool vectorsUseTwoUnits() const
Definition: PPCSubtarget.h:304
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::MVT::v2f64
@ v2f64
Definition: MachineValueType.h:172
llvm::TargetTransformInfo::UnrollingPreferences::AllowExpensiveTripCount
bool AllowExpensiveTripCount
Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...
Definition: TargetTransformInfo.h:492
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
llvm::TargetTransformInfo::LSRCost::Insns
unsigned Insns
TODO: Some of these could be merged.
Definition: TargetTransformInfo.h:419
llvm::PPCTTIImpl::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR()
Definition: PPCTargetTransformInfo.cpp:1334
llvm::CastInst::getDestTy
Type * getDestTy() const
Return the destination type, as a convenience.
Definition: InstrTypes.h:683
F
#define F(x, y, z)
Definition: MD5.cpp:55
KnownBits.h
llvm::LoopBase::block_end
block_iterator block_end() const
Definition: LoopInfo.h:177
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:421
floor
We have fiadd patterns now but the followings have the same cost and complexity We need a way to specify the later is more profitable def def The FP stackifier should handle simple permutates to reduce number of shuffle e g floor
Definition: README-FPStack.txt:54
llvm::ISD::STRICT_FROUND
@ STRICT_FROUND
Definition: ISDOpcodes.h:427
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
llvm::PPC::DIR_PWR8
@ DIR_PWR8
Definition: PPCSubtarget.h:61
llvm::TargetSchedModel::init
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
Definition: TargetSchedule.cpp:62
llvm::PPCTTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: PPCTargetTransformInfo.cpp:68
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:425
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:923
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::PPCTTIImpl::GPRRC
@ GPRRC
Definition: PPCTargetTransformInfo.h:94
CommandLine.h
CodeMetrics.h
TargetLowering.h
llvm::PPC::DIR_A2
@ DIR_A2
Definition: PPCSubtarget.h:50
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
Definition: TargetLowering.h:1156
llvm::BasicTTIImplBase< PPCTTIImpl >::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: BasicTTIImpl.h:513
llvm::TargetSchedModel::getIssueWidth
unsigned getIssueWidth() const
Maximum number of micro-ops that may be scheduled per cycle.
Definition: TargetSchedule.h:98
llvm::ISD::STRICT_FRINT
@ STRICT_FRINT
Definition: ISDOpcodes.h:421
llvm::BasicTTIImplBase< PPCTTIImpl >::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:1139
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:871
llvm::PPCTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: PPCTargetTransformInfo.cpp:850
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1091
llvm::User
Definition: User.h:44
llvm::LibFunc
LibFunc
Definition: TargetLibraryInfo.h:35
llvm::ISD::STRICT_FNEARBYINT
@ STRICT_FNEARBYINT
Definition: ISDOpcodes.h:422
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::PPC::DIR_E500mc
@ DIR_E500mc
Definition: PPCSubtarget.h:52
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
LsrNoInsnsCost
static cl::opt< bool > LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false), cl::desc("Do not add instruction count to lsr cost model"))
round
static uint64_t round(uint64_t Acc, uint64_t Input)
Definition: xxhash.cpp:56
llvm::isShiftedMask_64
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:485
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:921
llvm::PPC::DIR_440
@ DIR_440
Definition: PPCSubtarget.h:43
llvm::LoopBase::blocks
iterator_range< block_iterator > blocks() const
Definition: LoopInfo.h:178
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:925
TargetLibraryInfo.h
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
llvm::PPCSubtarget::isISA3_0
bool isISA3_0() const
Definition: PPCSubtarget.h:337
llvm::InlineAsm::isInput
@ isInput
Definition: InlineAsm.h:94
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::TargetLibraryInfo::getLibFunc
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
Definition: TargetLibraryInfo.h:294
llvm::Instruction
Definition: Instruction.h:42
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfoImplBase::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
Definition: TargetTransformInfoImpl.h:381
llvm::PPCSubtarget::isPPC64
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Definition: PPCSubtarget.cpp:254
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1478
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:920
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:919
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:33
llvm::UndefValue::get
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
Definition: Constants.cpp:1769
llvm::PPCTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: PPCTargetTransformInfo.cpp:1153
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:919
llvm::PPCTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: PPCTargetTransformInfo.cpp:818
llvm::CodeMetrics::collectEphemeralValues
static void collectEphemeralValues(const Loop *L, AssumptionCache *AC, SmallPtrSetImpl< const Value * > &EphValues)
Collect a loop's ephemeral values (those used only by an assume or similar intrinsics in the loop).
Definition: CodeMetrics.cpp:70
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::PPCTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: PPCTargetTransformInfo.cpp:1082
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:919
llvm::PPCTTIImpl::FPRRC
@ FPRRC
Definition: PPCTargetTransformInfo.h:94
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::CastInst::getSrcTy
Type * getSrcTy() const
Return the source type, as a convenience.
Definition: InstrTypes.h:681
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::BasicTTIImplBase< PPCTTIImpl >::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1091
llvm::BasicTTIImplBase< PPCTTIImpl >::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:921
llvm::None
const NoneType None
Definition: None.h:24
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::Type::getIntegerBitWidth
unsigned getIntegerBitWidth() const
Definition: DerivedTypes.h:97
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:594
llvm::maxnum
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1306
llvm::PPCTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: PPCTargetTransformInfo.cpp:890
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::LoopBase::block_begin
block_iterator block_begin() const
Definition: LoopInfo.h:176
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:191
llvm::ScalarEvolution::getSmallConstantTripCount
unsigned getSmallConstantTripCount(const Loop *L)
Returns the exact trip count of the loop if we can compute it, and the result is a small constant.
Definition: ScalarEvolution.cpp:7682
CacheLineSize
static cl::opt< unsigned > CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64), cl::desc("The loop prefetch cache line size"))
llvm::InlineAsm
Definition: InlineAsm.h:31
llvm::ISD::STRICT_FSETCCS
@ STRICT_FSETCCS
Definition: ISDOpcodes.h:476
llvm::cl::opt< bool >
llvm::LoopBase< BasicBlock, Loop >::block_iterator
ArrayRef< BasicBlock * >::const_iterator block_iterator
Definition: LoopInfo.h:175
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1974
llvm::IRBuilderBase::CreateBitCast
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1952
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:305
llvm::PPCTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: PPCTargetTransformInfo.cpp:1274
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
TargetSchedule.h
llvm::MVT::v16i8
@ v16i8
Definition: MachineValueType.h:80
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::StringRef::equals_insensitive
LLVM_NODISCARD bool equals_insensitive(StringRef RHS) const
Check for string equality, ignoring case.
Definition: StringRef.h:194
llvm::PPCSubtarget::POPCNTD_Unavailable
@ POPCNTD_Unavailable
Definition: PPCSubtarget.h:74
llvm::PointerType::getUnqual
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Definition: DerivedTypes.h:651
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::InstCombiner::getAssumptionCache
AssumptionCache & getAssumptionCache() const
Definition: InstCombiner.h:368
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MVT::v2i64
@ v2i64
Definition: MachineValueType.h:118
uint64_t
llvm::TLSModel::LocalDynamic
@ LocalDynamic
Definition: CodeGen.h:44
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:416
llvm::InstCombiner::getDataLayout
const DataLayout & getDataLayout() const
Definition: InstCombiner.h:371
llvm::PPCSubtarget::hasP9Altivec
bool hasP9Altivec() const
Definition: PPCSubtarget.h:285
llvm::PPCTTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: PPCTargetTransformInfo.cpp:59
llvm::IRBuilderBase::getInt32
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:461
llvm::ISD::STRICT_LRINT
@ STRICT_LRINT
Definition: ISDOpcodes.h:432
llvm::TargetLoweringBase::getMaxExpandSizeMemcmp
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
Definition: TargetLowering.h:1664
llvm::DataLayout::isLittleEndian
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:244
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::PPCTTIImpl::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
Definition: PPCTargetTransformInfo.cpp:1346
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:534
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:430
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:926
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:898
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Metrics
Machine Trace Metrics
Definition: MachineTraceMetrics.cpp:53
llvm::PPCTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef< int > Mask, int Index, Type *SubTp, ArrayRef< const Value * > Args=None)
Definition: PPCTargetTransformInfo.cpp:1014
llvm::Type::isHalfTy
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:142
llvm::MVT::v4f32
@ v4f32
Definition: MachineValueType.h:157
llvm::InlineAsm::ConstraintInfo
Definition: InlineAsm.h:120
llvm::ISD::STRICT_LROUND
@ STRICT_LROUND
Definition: ISDOpcodes.h:430
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
Definition: PPCISelLowering.cpp:16636
llvm::PPCTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: PPCTargetTransformInfo.cpp:1239
memcpy
<%struct.s * > cast struct s *S to sbyte *< sbyte * > sbyte uint cast struct s *agg result to sbyte *< sbyte * > sbyte uint cast struct s *memtmp to sbyte *< sbyte * > sbyte uint ret void llc ends up issuing two memcpy or custom lower memcpy(of small size) to be ldmia/stmia. I think option 2 is better but the current register allocator cannot allocate a chunk of registers at a time. A feasible temporary solution is to use specific physical registers at the lowering time for small(<
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::PPCTTIImpl::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: PPCTargetTransformInfo.cpp:1338
llvm::PPCTTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: PPCTargetTransformInfo.cpp:846
llvm::IRBuilderBase::CreateExtractElement
Value * CreateExtractElement(Value *Vec, Value *Idx, const Twine &Name="")
Definition: IRBuilder.h:2276
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:426
llvm::BasicTTIImplBase< PPCTTIImpl >::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: BasicTTIImpl.h:1240
llvm::TargetTransformInfo::PSK_SlowHardware
@ PSK_SlowHardware
Definition: TargetTransformInfo.h:594
SmallCTRLoopThreshold
static cl::opt< unsigned > SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden, cl::desc("Loops with a constant trip count smaller than " "this value will not use the count register."))
llvm::ISD::STRICT_LLRINT
@ STRICT_LLRINT
Definition: ISDOpcodes.h:433
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:890
llvm::PPCTTIImpl::useColdCCForColdCall
bool useColdCCForColdCall(Function &F)
Definition: PPCTargetTransformInfo.cpp:826
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:773
llvm::PPCSubtarget::hasDirectMove
bool hasDirectMove() const
Definition: PPCSubtarget.h:317
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:261
llvm::TargetTransformInfoImplBase::getVPMemoryOpCost
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
Definition: TargetTransformInfoImpl.h:579
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1086
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
llvm::ISD::STRICT_FTRUNC
@ STRICT_FTRUNC
Definition: ISDOpcodes.h:429
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::PPCTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: PPCTargetTransformInfo.cpp:235
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:927
EnablePPCColdCC
static cl::opt< bool > EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false), cl::desc("Enable using coldcc calling conv for cold " "internal functions"))
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
trunc
We have fiadd patterns now but the followings have the same cost and complexity We need a way to specify the later is more profitable def def The FP stackifier should handle simple permutates to reduce number of shuffle e g trunc
Definition: README-FPStack.txt:63
llvm::PPCTTIImpl::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo)
Definition: PPCTargetTransformInfo.cpp:1298
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1728
llvm::CastInst
This is the base class for all instructions that perform data casts.
Definition: InstrTypes.h:429
llvm::PPCTTIImpl::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: PPCTargetTransformInfo.cpp:861
llvm::InstructionCost::isValid
bool isValid() const
Definition: InstructionCost.h:79
llvm::MVT::v4i32
@ v4i32
Definition: MachineValueType.h:103
llvm::BasicTTIImplBase< PPCTTIImpl >::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: BasicTTIImpl.h:585
llvm::ifs::IFSSymbolType::Func
@ Func
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:176
llvm::PPC::DIR_PWR7
@ DIR_PWR7
Definition: PPCSubtarget.h:60
llvm::PPCTTIImpl::getVPMemoryOpCost
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: PPCTargetTransformInfo.cpp:1418
llvm::PPCTTIImpl::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions)
Definition: PPCTargetTransformInfo.cpp:830
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
llvm::BasicBlock::getContext
LLVMContext & getContext() const
Get the context in which this basic block lives.
Definition: BasicBlock.cpp:35
llvm::ISD::FSQRT
@ FSQRT
Definition: ISDOpcodes.h:906
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::PPCTTIImpl::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: PPCTargetTransformInfo.cpp:328
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::minnum
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1295
llvm::ISD::STRICT_FMA
@ STRICT_FMA
Definition: ISDOpcodes.h:405
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:937
llvm::Type::getInt64Ty
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:240
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:423
llvm::Type::isFloatTy
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:148
llvm::PPCSubtarget::useSoftFloat
bool useSoftFloat() const
Definition: PPCSubtarget.h:245
llvm::TargetTransformInfoImplBase::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:388
llvm::InstructionCost::getMax
static InstructionCost getMax()
Definition: InstructionCost.h:71
CostTable.h
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:295
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:917
llvm::Type::isIntOrIntVectorTy
bool isIntOrIntVectorTy() const
Return true if this is an integer type or a vector of integer types.
Definition: Type.h:197
llvm::MVT::v8i16
@ v8i16
Definition: MachineValueType.h:92
llvm::TypeSize
Definition: TypeSize.h:421
llvm::ISD::STRICT_FCEIL
@ STRICT_FCEIL
Definition: ISDOpcodes.h:425
llvm::BasicTTIImplBase< PPCTTIImpl >::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:1224
llvm::TargetLoweringBase::isOperationExpand
bool isOperationExpand(unsigned Op, EVT VT) const
Return true if the specified operation is illegal on this target or unlikely to be made legal with cu...
Definition: TargetLowering.h:1259
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:222
llvm::Type::isDoubleTy
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:151
llvm::PPCTTIImpl::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: PPCTargetTransformInfo.cpp:1390
powi
This is blocked on not handling X *X *X powi(X, 3)(see note above). The issue is that we end up getting t
llvm::log2
static double log2(double V)
Definition: AMDGPULibCalls.cpp:802
llvm::Type::isPPC_FP128Ty
bool isPPC_FP128Ty() const
Return true if this is powerpc long double.
Definition: Type.h:160
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:424
llvm::TLSModel::Model
Model
Definition: CodeGen.h:42
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
PPCTargetTransformInfo.h
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:919
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:94
llvm::PPC::DIR_E5500
@ DIR_E5500
Definition: PPCSubtarget.h:53
llvm::InstructionCost::getInvalid
static InstructionCost getInvalid(CostType Val=0)
Definition: InstructionCost.h:73
llvm::ISD::STRICT_FFLOOR
@ STRICT_FFLOOR
Definition: ISDOpcodes.h:426
llvm::PPCTTIImpl::getPrefetchDistance
unsigned getPrefetchDistance() const override
Definition: PPCTargetTransformInfo.cpp:920
llvm::PPCTTIImpl::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: PPCTargetTransformInfo.cpp:839
memAddrUsesCTR
static bool memAddrUsesCTR(const Value *MemAddr, const PPCTargetMachine &TM, SmallPtrSetImpl< const Value * > &Visited)
Definition: PPCTargetTransformInfo.cpp:348
llvm::PPCSubtarget::hasAltivec
bool hasAltivec() const
Definition: PPCSubtarget.h:275
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:919
isMMAType
static bool isMMAType(Type *Ty)
Definition: PPCTargetTransformInfo.cpp:323
llvm::PPCTTIImpl::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: PPCTargetTransformInfo.cpp:1279
llvm::CallBase::getArgOperand
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1341
llvm::BasicTTIImplBase< PPCTTIImpl >::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
Definition: BasicTTIImpl.h:1380
llvm::PPCTTIImpl::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: PPCTargetTransformInfo.cpp:903
TargetTransformInfo.h
llvm::PPCTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: PPCTargetTransformInfo.cpp:1064
llvm::BasicTTIImplBase< PPCTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1180
llvm::ISD::STRICT_LLROUND
@ STRICT_LLROUND
Definition: ISDOpcodes.h:431
llvm::PPC::DIR_PWR9
@ DIR_PWR9
Definition: PPCSubtarget.h:62
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:45
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:69
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:924
llvm::SmallPtrSetImpl< const Value * >
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::PPCSubtarget::getCPUDirective
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:205
llvm::TargetLibraryInfo::hasOptimizedCodeGen
bool hasOptimizedCodeGen(LibFunc F) const
Tests if the function is both available and a candidate for optimized code generation.
Definition: TargetLibraryInfo.h:343
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:262
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3243
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::cl::desc
Definition: CommandLine.h:405
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1455
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3099
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:918
llvm::PPCTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: PPCTargetTransformInfo.cpp:1035
llvm::PPCSubtarget::POPCNTD_Slow
@ POPCNTD_Slow
Definition: PPCSubtarget.h:75
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:523
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:101
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
llvm::Directive
Definition: DirectiveEmitter.h:100
llvm::Type::isFP128Ty
bool isFP128Ty() const
Return true if this is 'fp128'.
Definition: Type.h:157
Debug.h
llvm::PPC::DIR_PWR10
@ DIR_PWR10
Definition: PPCSubtarget.h:63
llvm::PPCTTIImpl::VRRC
@ VRRC
Definition: PPCTargetTransformInfo.h:94
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:164
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::PPCSubtarget::hasP10Vector
bool hasP10Vector() const
Definition: PPCSubtarget.h:286
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::TargetTransformInfoImplBase::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfoImpl.h:729