LLVM  14.0.0git
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RISCVISelLowering.cpp File Reference
#include "RISCVISelLowering.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "RISCVGenAsmMatcher.inc"
#include "RISCVGenSearchableTables.inc"
Include dependency graph for RISCVISelLowering.cpp:

Go to the source code of this file.

Classes

struct  VIDSequence
 
struct  RISCVBitmanipPat
 

Namespaces

 llvm
 ---------------------— PointerInfo ------------------------------------—
 
 llvm::RISCVVIntrinsicsTable
 

Macros

#define DEBUG_TYPE   "riscv-lower"
 
#define NODE_NAME_CASE(NODE)
 
#define GET_REGISTER_MATCHER
 
#define GET_RISCVVIntrinsicsTable_IMPL
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
static void translateSetCCForBranch (const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG)
 
static bool useRVVForFixedLengthVectorVT (MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (const TargetLowering &TLI, MVT VT, const RISCVSubtarget &Subtarget)
 
static MVT getContainerForFixedLengthVector (SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
 
static SDValue convertToScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue convertFromScalableVector (EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultVLOps (MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static std::pair< SDValue, SDValuegetDefaultScalableVLOps (MVT VecVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG)
 
static SDValue lowerSPLAT_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static Optional< VIDSequenceisSimpleVIDSequence (SDValue Op)
 
static SDValue lowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue splatPartsI64WithVL (const SDLoc &DL, MVT VT, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG)
 
static SDValue splatSplitI64WithVL (const SDLoc &DL, MVT VT, SDValue Scalar, SDValue VL, SelectionDAG &DAG)
 
static SDValue lowerScalarSplat (SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue lowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue getRVVFPExtendOrRound (SDValue Op, MVT VT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue lowerVectorIntrinsicSplats (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static MVT getLMUL1VT (MVT VT)
 
static unsigned getRVVReductionOp (unsigned ISDOpcode)
 
static std::tuple< unsigned, SDValue, SDValuegetRVVFPReductionOpAndOperands (SDValue Op, SelectionDAG &DAG, EVT EltVT)
 
static RISCVISD::NodeType getRISCVWOpcode (unsigned Opcode)
 
static SDValue customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
 
static SDValue customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
 
static Optional< RISCVBitmanipPatmatchRISCVBitmanipPat (SDValue Op, ArrayRef< uint64_t > BitmanipMasks)
 
static Optional< RISCVBitmanipPatmatchGREVIPat (SDValue Op)
 
static SDValue combineORToGREV (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineORToGORC (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static Optional< RISCVBitmanipPatmatchSHFLPat (SDValue Op)
 
static SDValue combineORToSHFL (SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue transformAddShlImm (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue combineGREVI_GORCI (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes)
 
static SDValue combineSelectAndUseCommutative (SDNode *N, SelectionDAG &DAG, bool AllOnes)
 
static SDValue performADDCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performSUBCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue performANDCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue performORCombine (SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
 
static SDValue performXORCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue performANY_EXTENDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget)
 
static void computeGREV (APInt &Src, unsigned ShAmt)
 
static MachineBasicBlockemitReadCycleWidePseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlockemitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlockemitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static bool isSelectPseudo (MachineInstr &MI)
 
static MachineBasicBlockemitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB, const RISCVSubtarget &Subtarget)
 
static bool CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
 
static unsigned allocateRVVReg (MVT ValVT, unsigned ValNo, Optional< unsigned > FirstMaskArgument, CCState &State, const RISCVTargetLowering &TLI)
 
static bool CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, Optional< unsigned > FirstMaskArgument)
 
template<typename ArgTy >
static Optional< unsigned > preAssignMask (const ArgTy &Args)
 
static SDValue convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const RISCVTargetLowering &TLI)
 
static SDValue convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget)
 
static SDValue unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static bool CC_RISCV_FastCC (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, Optional< unsigned > FirstMaskArgument)
 
static bool CC_RISCV_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
static Align getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
 
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)
 

Variables

static const MCPhysReg ArgGPRs []
 
static const MCPhysReg ArgFPR16s []
 
static const MCPhysReg ArgFPR32s []
 
static const MCPhysReg ArgFPR64s []
 
static const MCPhysReg ArgVRs []
 
static const MCPhysReg ArgVRM2s []
 
static const MCPhysReg ArgVRM4s []
 
static const MCPhysReg ArgVRM8s [] = {RISCV::V8M8, RISCV::V16M8}
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 42 of file RISCVISelLowering.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 9430 of file RISCVISelLowering.cpp.

◆ GET_RISCVVIntrinsicsTable_IMPL

#define GET_RISCVVIntrinsicsTable_IMPL

Definition at line 9452 of file RISCVISelLowering.cpp.

◆ NODE_NAME_CASE

#define NODE_NAME_CASE (   NODE)
Value:
return "RISCVISD::" #NODE;

Function Documentation

◆ allocateRVVReg()

static unsigned allocateRVVReg ( MVT  ValVT,
unsigned  ValNo,
Optional< unsigned >  FirstMaskArgument,
CCState State,
const RISCVTargetLowering TLI 
)
static

◆ CC_RISCV()

static bool CC_RISCV ( const DataLayout DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
bool  IsFixed,
bool  IsRet,
Type OrigTy,
const RISCVTargetLowering TLI,
Optional< unsigned >  FirstMaskArgument 
)
static

Definition at line 7405 of file RISCVISelLowering.cpp.

References ABI, llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), Align, llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, llvm::array_lengthof(), assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasStdExtV(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, Reg, llvm::report_fatal_error(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().

◆ CC_RISCV_FastCC()

static bool CC_RISCV_FastCC ( const DataLayout DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
bool  IsFixed,
bool  IsRet,
Type OrigTy,
const RISCVTargetLowering TLI,
Optional< unsigned >  FirstMaskArgument 
)
static

◆ CC_RISCV_GHC()

static bool CC_RISCV_GHC ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State 
)
static

◆ CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen,
CCState State,
CCValAssign  VA1,
ISD::ArgFlagsTy  ArgFlags1,
unsigned  ValNo2,
MVT  ValVT2,
MVT  LocVT2,
ISD::ArgFlagsTy  ArgFlags2 
)
static

◆ combineGREVI_GORCI()

static SDValue combineGREVI_GORCI ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineORToGORC()

static SDValue combineORToGORC ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineORToGREV()

static SDValue combineORToGREV ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineORToSHFL()

static SDValue combineORToSHFL ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode N,
SDValue  Slct,
SDValue  OtherOp,
SelectionDAG DAG,
bool  AllOnes 
)
static

◆ combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode N,
SelectionDAG DAG,
bool  AllOnes 
)
static

◆ computeGREV()

static void computeGREV ( APInt Src,
unsigned  ShAmt 
)
static

Definition at line 6823 of file RISCVISelLowering.cpp.

References x.

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode().

◆ convertFromScalableVector()

static SDValue convertFromScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL,
const RISCVSubtarget Subtarget 
)
static

◆ convertToScalableVector()

static SDValue convertToScalableVector ( EVT  VT,
SDValue  V,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL,
const RISCVSubtarget Subtarget 
)
static

◆ customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode N,
SelectionDAG DAG,
unsigned  ExtOpc = ISD::ANY_EXTEND 
)
static

◆ customLegalizeToWOpWithSExt()

static SDValue customLegalizeToWOpWithSExt ( SDNode N,
SelectionDAG DAG 
)
static

◆ emitBuildPairF64Pseudo()

static MachineBasicBlock* emitBuildPairF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitReadCycleWidePseudo()

static MachineBasicBlock* emitReadCycleWidePseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitSelectPseudo()

static MachineBasicBlock* emitSelectPseudo ( MachineInstr MI,
MachineBasicBlock BB,
const RISCVSubtarget Subtarget 
)
static

◆ emitSplitF64Pseudo()

static MachineBasicBlock* emitSplitF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ getContainerForFixedLengthVector() [1/2]

static MVT getContainerForFixedLengthVector ( const TargetLowering TLI,
MVT  VT,
const RISCVSubtarget Subtarget 
)
static

◆ getContainerForFixedLengthVector() [2/2]

static MVT getContainerForFixedLengthVector ( SelectionDAG DAG,
MVT  VT,
const RISCVSubtarget Subtarget 
)
static

◆ getDefaultScalableVLOps()

static std::pair<SDValue, SDValue> getDefaultScalableVLOps ( MVT  VecVT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 1432 of file RISCVISelLowering.cpp.

References assert(), DL, getDefaultVLOps(), and llvm::MVT::isScalableVector().

◆ getDefaultVLOps()

static std::pair<SDValue, SDValue> getDefaultVLOps ( MVT  VecVT,
MVT  ContainerVT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  XLen,
AtomicRMWInst::BinOp  BinOp 
)
static

◆ getLMUL1VT()

static MVT getLMUL1VT ( MVT  VT)
static

◆ getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT,
SelectionDAG DAG 
)
static

◆ getRISCVWOpcode()

static RISCVISD::NodeType getRISCVWOpcode ( unsigned  Opcode)
static

◆ getRVVFPExtendOrRound()

static SDValue getRVVFPExtendOrRound ( SDValue  Op,
MVT  VT,
MVT  ContainerVT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ getRVVFPReductionOpAndOperands()

static std::tuple<unsigned, SDValue, SDValue> getRVVFPReductionOpAndOperands ( SDValue  Op,
SelectionDAG DAG,
EVT  EltVT 
)
static

◆ getRVVReductionOp()

static unsigned getRVVReductionOp ( unsigned  ISDOpcode)
static

◆ getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 2851 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetBlockAddress(), and N.

◆ getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 2857 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetConstantPool(), and N.

◆ getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 2846 of file RISCVISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

◆ getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 2863 of file RISCVISelLowering.cpp.

References llvm::SelectionDAG::getTargetJumpTable(), and N.

◆ isSelectPseudo()

static bool isSelectPseudo ( MachineInstr MI)
static

Definition at line 7135 of file RISCVISelLowering.cpp.

References MI.

Referenced by emitSelectPseudo().

◆ isSimpleVIDSequence()

static Optional<VIDSequence> isSimpleVIDSequence ( SDValue  Op)
static

Definition at line 1518 of file RISCVISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::None, and llvm::SignExtend64().

Referenced by lowerBUILD_VECTOR().

◆ lowerBUILD_VECTOR()

static SDValue lowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 1595 of file RISCVISelLowering.cpp.

References llvm::abs(), llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::tgtok::Bits, llvm::MVT::bitsLE(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), llvm::count_if(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::RISCVSubtarget::is64Bit(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt< 32 >(), llvm::MVT::isInteger(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::SDValue::isUndef(), llvm::Log2_32(), llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), llvm::max(), llvm::min(), llvm::ISD::MUL, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::SelectionDAG::shouldOptForSize(), llvm::SignExtend64(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::size(), llvm::ISD::SRL, llvm::ISD::SUB, llvm::transform(), llvm::MVT::v1i8, llvm::MVT::v8i1, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VID_VL, llvm::RISCVISD::VMCLR_VL, llvm::RISCVISD::VMSET_VL, llvm::RISCVISD::VMV_V_X_VL, and llvm::ISD::VSELECT.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerFP_TO_INT_SAT()

static SDValue lowerFP_TO_INT_SAT ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ lowerScalarSplat()

static SDValue lowerScalarSplat ( SDValue  Scalar,
SDValue  VL,
MVT  VT,
SDLoc  DL,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerSPLAT_VECTOR()

static SDValue lowerSPLAT_VECTOR ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ lowerVECTOR_SHUFFLE()

static SDValue lowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

Definition at line 1963 of file RISCVISelLowering.cpp.

References llvm::all_of(), assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::begin(), llvm::MVT::bitsGT(), llvm::MVT::changeTypeToInteger(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, convertFromScalableVector(), convertToScalableVector(), DL, llvm::enumerate(), llvm::TypeSize::Fixed(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatValue(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i1, llvm::MVT::i16, int, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), lowerScalarSplat(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), Offset, llvm::MVT::Other, llvm::ISD::SEXTLOAD, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::size(), std::swap(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_V_X_VL, llvm::RISCVISD::VRGATHER_VV_VL, llvm::RISCVISD::VRGATHER_VX_VL, llvm::RISCVISD::VRGATHEREI16_VV_VL, llvm::ISD::VSELECT, and llvm::RISCVISD::VSELECT_VL.

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ lowerVectorIntrinsicSplats()

static SDValue lowerVectorIntrinsicSplats ( SDValue  Op,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ matchGREVIPat()

static Optional<RISCVBitmanipPat> matchGREVIPat ( SDValue  Op)
static

Definition at line 5726 of file RISCVISelLowering.cpp.

References matchRISCVBitmanipPat().

Referenced by combineORToGORC(), and combineORToGREV().

◆ matchRISCVBitmanipPat()

static Optional<RISCVBitmanipPat> matchRISCVBitmanipPat ( SDValue  Op,
ArrayRef< uint64_t BitmanipMasks 
)
static

◆ matchSHFLPat()

static Optional<RISCVBitmanipPat> matchSHFLPat ( SDValue  Op)
static

Definition at line 5832 of file RISCVISelLowering.cpp.

References matchRISCVBitmanipPat().

Referenced by combineORToSHFL().

◆ performADDCombine()

static SDValue performADDCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performANDCombine()

static SDValue performANDCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ performANY_EXTENDCombine()

static SDValue performANY_EXTENDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const RISCVSubtarget Subtarget 
)
static

◆ performORCombine()

static SDValue performORCombine ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ performSUBCombine()

static SDValue performSUBCombine ( SDNode N,
SelectionDAG DAG 
)
static

Definition at line 6077 of file RISCVISelLowering.cpp.

References combineSelectAndUse(), and N.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performXORCombine()

static SDValue performXORCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ preAssignMask()

template<typename ArgTy >
static Optional<unsigned> preAssignMask ( const ArgTy &  Args)
static

◆ splatPartsI64WithVL()

static SDValue splatPartsI64WithVL ( const SDLoc DL,
MVT  VT,
SDValue  Lo,
SDValue  Hi,
SDValue  VL,
SelectionDAG DAG 
)
static

◆ splatSplitI64WithVL()

static SDValue splatSplitI64WithVL ( const SDLoc DL,
MVT  VT,
SDValue  Scalar,
SDValue  VL,
SelectionDAG DAG 
)
static

◆ STATISTIC()

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)

◆ transformAddShlImm()

static SDValue transformAddShlImm ( SDNode N,
SelectionDAG DAG,
const RISCVSubtarget Subtarget 
)
static

◆ translateSetCCForBranch()

static void translateSetCCForBranch ( const SDLoc DL,
SDValue LHS,
SDValue RHS,
ISD::CondCode CC,
SelectionDAG DAG 
)
static

◆ unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL,
const RISCVTargetLowering TLI 
)
static

◆ useRVVForFixedLengthVectorVT()

static bool useRVVForFixedLengthVectorVT ( MVT  VT,
const RISCVSubtarget Subtarget 
)
static

Variable Documentation

◆ ArgFPR16s

const MCPhysReg ArgFPR16s[]
static
Initial value:
= {
RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
}

Definition at line 7320 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgFPR32s

const MCPhysReg ArgFPR32s[]
static
Initial value:
= {
RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
}

Definition at line 7324 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgFPR64s

const MCPhysReg ArgFPR64s[]
static
Initial value:
= {
RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
}

Definition at line 7328 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgGPRs

const MCPhysReg ArgGPRs[]
static
Initial value:
= {
RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
}

Definition at line 7316 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV(), CC_RISCVAssign2XLen(), llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ ArgVRM2s

const MCPhysReg ArgVRM2s[]
static
Initial value:
= {RISCV::V8M2, RISCV::V10M2, RISCV::V12M2,
RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
RISCV::V20M2, RISCV::V22M2}

Definition at line 7337 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRM4s

const MCPhysReg ArgVRM4s[]
static
Initial value:
= {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
RISCV::V20M4}

Definition at line 7340 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRM8s

const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}
static

Definition at line 7342 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

◆ ArgVRs

const MCPhysReg ArgVRs[]
static
Initial value:
= {
RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23}

Definition at line 7333 of file RISCVISelLowering.cpp.

Referenced by allocateRVVReg().

NODE
#define NODE(name)