59 #define DEBUG_TYPE "mcasmparser"
64 "mwarn-missing-parenthesis",
65 cl::desc(
"Warn for missing parenthesis around predicate registers"),
68 "merror-missing-parenthesis",
69 cl::desc(
"Error for missing parenthesis around predicate registers"),
72 "mwarn-sign-mismatch",
73 cl::desc(
"Warn for mismatching a signed and unsigned value"),
76 "mwarn-noncontigious-register",
79 "merror-noncontigious-register",
80 cl::desc(
"Error for register names that aren't contigious"),
85 struct HexagonOperand;
111 bool equalIsAsmAssignment()
override {
return false; }
112 bool isLabel(
AsmToken &Token)
override;
116 bool ParseDirectiveFalign(
unsigned Size,
SMLoc L);
118 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
120 SMLoc &EndLoc)
override;
121 bool ParseDirectiveSubsection(
SMLoc L);
122 bool ParseDirectiveComm(
bool IsLocal,
SMLoc L);
123 bool RegisterMatchesArch(
unsigned MatchNum)
const;
125 bool matchBundleOptions();
126 bool handleNoncontigiousRegister(
bool Contigious,
SMLoc &Loc);
128 void canonicalizeImmediates(
MCInst &MCI);
131 bool MatchingInlineAsm);
132 void eatToEndOfPacket();
133 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
136 bool MatchingInlineAsm)
override;
139 unsigned Kind)
override;
140 bool OutOfRange(
SMLoc IDLoc,
long long Val,
long long Max);
149 #define GET_ASSEMBLER_HEADER
150 #include "HexagonGenAsmMatcher.inc"
160 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
174 bool parseExpression(
MCExpr const *&Expr);
184 bool ParseDirective(
AsmToken DirectiveID)
override;
193 SMLoc StartLoc, EndLoc;
217 HexagonOperand(
const HexagonOperand &o)
220 StartLoc = o.StartLoc;
236 SMLoc getStartLoc()
const override {
return StartLoc; }
239 SMLoc getEndLoc()
const override {
return EndLoc; }
241 unsigned getReg()
const override {
246 const MCExpr *getImm()
const {
247 assert(
Kind == Immediate &&
"Invalid access!");
251 bool isToken()
const override {
return Kind == Token; }
252 bool isImm()
const override {
return Kind == Immediate; }
256 bool CheckImmRange(
int immBits,
int zeroBits,
bool isSigned,
257 bool isRelocatable,
bool Extendable)
const {
258 if (
Kind == Immediate) {
263 if (myMCExpr->evaluateAsAbsolute(Res)) {
264 int bits = immBits + zeroBits;
267 if (Res & ((1 << zeroBits) - 1))
270 if (Res < (1LL << (
bits - 1)) && Res >= -(1LL << (
bits - 1)))
278 const int64_t high_bit_set = 1ULL << 63;
280 return (((
uint64_t)Res & mask) == mask);
292 bool isa30_2Imm()
const {
return CheckImmRange(30, 2,
true,
true,
true); }
293 bool isb30_2Imm()
const {
return CheckImmRange(30, 2,
true,
true,
true); }
294 bool isb15_2Imm()
const {
return CheckImmRange(15, 2,
true,
true,
false); }
295 bool isb13_2Imm()
const {
return CheckImmRange(13, 2,
true,
true,
false); }
297 bool ism32_0Imm()
const {
return true; }
299 bool isf32Imm()
const {
return false; }
300 bool isf64Imm()
const {
return false; }
301 bool iss32_0Imm()
const {
return true; }
302 bool iss31_1Imm()
const {
return true; }
303 bool iss30_2Imm()
const {
return true; }
304 bool iss29_3Imm()
const {
return true; }
305 bool iss27_2Imm()
const {
return CheckImmRange(27, 2,
true,
true,
false); }
306 bool iss10_0Imm()
const {
return CheckImmRange(10, 0,
true,
false,
false); }
307 bool iss10_6Imm()
const {
return CheckImmRange(10, 6,
true,
false,
false); }
308 bool iss9_0Imm()
const {
return CheckImmRange(9, 0,
true,
false,
false); }
309 bool iss8_0Imm()
const {
return CheckImmRange(8, 0,
true,
false,
false); }
310 bool iss8_0Imm64()
const {
return CheckImmRange(8, 0,
true,
true,
false); }
311 bool iss7_0Imm()
const {
return CheckImmRange(7, 0,
true,
false,
false); }
312 bool iss6_0Imm()
const {
return CheckImmRange(6, 0,
true,
false,
false); }
313 bool iss6_3Imm()
const {
return CheckImmRange(6, 3,
true,
false,
false); }
314 bool iss4_0Imm()
const {
return CheckImmRange(4, 0,
true,
false,
false); }
315 bool iss4_1Imm()
const {
return CheckImmRange(4, 1,
true,
false,
false); }
316 bool iss4_2Imm()
const {
return CheckImmRange(4, 2,
true,
false,
false); }
317 bool iss4_3Imm()
const {
return CheckImmRange(4, 3,
true,
false,
false); }
318 bool iss3_0Imm()
const {
return CheckImmRange(3, 0,
true,
false,
false); }
320 bool isu64_0Imm()
const {
return CheckImmRange(64, 0,
false,
true,
true); }
321 bool isu32_0Imm()
const {
return true; }
322 bool isu31_1Imm()
const {
return true; }
323 bool isu30_2Imm()
const {
return true; }
324 bool isu29_3Imm()
const {
return true; }
325 bool isu26_6Imm()
const {
return CheckImmRange(26, 6,
false,
true,
false); }
326 bool isu16_0Imm()
const {
return CheckImmRange(16, 0,
false,
true,
false); }
327 bool isu16_1Imm()
const {
return CheckImmRange(16, 1,
false,
true,
false); }
328 bool isu16_2Imm()
const {
return CheckImmRange(16, 2,
false,
true,
false); }
329 bool isu16_3Imm()
const {
return CheckImmRange(16, 3,
false,
true,
false); }
330 bool isu11_3Imm()
const {
return CheckImmRange(11, 3,
false,
false,
false); }
331 bool isu10_0Imm()
const {
return CheckImmRange(10, 0,
false,
false,
false); }
332 bool isu9_0Imm()
const {
return CheckImmRange(9, 0,
false,
false,
false); }
333 bool isu8_0Imm()
const {
return CheckImmRange(8, 0,
false,
false,
false); }
334 bool isu7_0Imm()
const {
return CheckImmRange(7, 0,
false,
false,
false); }
335 bool isu6_0Imm()
const {
return CheckImmRange(6, 0,
false,
false,
false); }
336 bool isu6_1Imm()
const {
return CheckImmRange(6, 1,
false,
false,
false); }
337 bool isu6_2Imm()
const {
return CheckImmRange(6, 2,
false,
false,
false); }
338 bool isu6_3Imm()
const {
return CheckImmRange(6, 3,
false,
false,
false); }
339 bool isu5_0Imm()
const {
return CheckImmRange(5, 0,
false,
false,
false); }
340 bool isu5_2Imm()
const {
return CheckImmRange(5, 2,
false,
false,
false); }
341 bool isu5_3Imm()
const {
return CheckImmRange(5, 3,
false,
false,
false); }
342 bool isu4_0Imm()
const {
return CheckImmRange(4, 0,
false,
false,
false); }
343 bool isu4_2Imm()
const {
return CheckImmRange(4, 2,
false,
false,
false); }
344 bool isu3_0Imm()
const {
return CheckImmRange(3, 0,
false,
false,
false); }
345 bool isu3_1Imm()
const {
return CheckImmRange(3, 1,
false,
false,
false); }
346 bool isu2_0Imm()
const {
return CheckImmRange(2, 0,
false,
false,
false); }
347 bool isu1_0Imm()
const {
return CheckImmRange(1, 0,
false,
false,
false); }
349 bool isn1Const()
const {
353 if (!getImm()->evaluateAsAbsolute(
Value))
357 bool iss11_0Imm()
const {
358 return CheckImmRange(11 + 26, 0,
true,
true,
true);
360 bool iss11_1Imm()
const {
361 return CheckImmRange(11 + 26, 1,
true,
true,
true);
363 bool iss11_2Imm()
const {
364 return CheckImmRange(11 + 26, 2,
true,
true,
true);
366 bool iss11_3Imm()
const {
367 return CheckImmRange(11 + 26, 3,
true,
true,
true);
369 bool isu32_0MustExt()
const {
return isImm(); }
371 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
372 assert(
N == 1 &&
"Invalid number of operands!");
376 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
377 assert(
N == 1 &&
"Invalid number of operands!");
381 void addSignedImmOperands(
MCInst &Inst,
unsigned N)
const {
382 assert(
N == 1 &&
"Invalid number of operands!");
393 if ((Extended < 0) != (
Value < 0))
400 void addn1ConstOperands(
MCInst &Inst,
unsigned N)
const {
401 addImmOperands(Inst,
N);
413 HexagonOperand *
Op =
new HexagonOperand(Token,
Context);
414 Op->Tok.Data = Str.data();
415 Op->Tok.Length = Str.size();
418 return std::unique_ptr<HexagonOperand>(
Op);
421 static std::unique_ptr<HexagonOperand>
424 Op->Reg.RegNum = RegNum;
427 return std::unique_ptr<HexagonOperand>(
Op);
430 static std::unique_ptr<HexagonOperand>
432 HexagonOperand *
Op =
new HexagonOperand(Immediate,
Context);
436 return std::unique_ptr<HexagonOperand>(
Op);
445 getImm()->print(OS,
nullptr);
452 OS <<
"'" << getToken() <<
"'";
472 MII, STI, getContext(), MCB, &
Check,
true);
491 bool HexagonAsmParser::matchBundleOptions() {
497 char const *MemNoShuffMsg =
498 "invalid instruction packet: mem_noshuf specifier not "
499 "supported with this architecture";
502 if (
Option.compare_insensitive(
"endloop01") == 0) {
505 }
else if (
Option.compare_insensitive(
"endloop0") == 0) {
507 }
else if (
Option.compare_insensitive(
"endloop1") == 0) {
509 }
else if (
Option.compare_insensitive(
"mem_noshuf") == 0) {
510 if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
513 return getParser().Error(IDLoc, MemNoShuffMsg);
514 }
else if (
Option.compare_insensitive(
"mem_no_order") == 0) {
518 "' is not a valid bundle option");
526 void HexagonAsmParser::canonicalizeImmediates(
MCInst &MCI) {
531 int64_t
Value(
I.getImm());
535 if (
I.isExpr() && cast<HexagonMCExpr>(
I.getExpr())->signMismatch() &&
537 Warning(MCI.getLoc(),
"Signed/Unsigned mismatch");
543 bool HexagonAsmParser::matchOneInstruction(
MCInst &MCI,
SMLoc IDLoc,
546 bool MatchingInlineAsm) {
549 MatchInstructionImpl(InstOperands, MCI,
ErrorInfo, MatchingInlineAsm);
550 if (
result == Match_Success) {
552 canonicalizeImmediates(MCI);
553 result = processInstruction(MCI, InstOperands, IDLoc);
571 case Match_MissingFeature:
572 return Error(IDLoc,
"invalid instruction");
573 case Match_MnemonicFail:
574 return Error(IDLoc,
"unrecognized instruction");
575 case Match_InvalidOperand:
577 case Match_InvalidTiedOperand:
578 SMLoc ErrorLoc = IDLoc;
581 return Error(IDLoc,
"too few operands for instruction");
583 ErrorLoc = (
static_cast<HexagonOperand *
>(InstOperands[
ErrorInfo].get()))
585 if (ErrorLoc ==
SMLoc())
588 return Error(ErrorLoc,
"invalid operand for instruction");
593 void HexagonAsmParser::eatToEndOfPacket() {
602 bool HexagonAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
606 bool MatchingInlineAsm) {
611 HexagonOperand &FirstOperand =
static_cast<HexagonOperand &
>(*
Operands[0]);
612 if (FirstOperand.isToken() && FirstOperand.getToken() ==
"{") {
613 assert(
Operands.size() == 1 &&
"Brackets should be by themselves");
615 getParser().Error(IDLoc,
"Already in a packet");
622 if (FirstOperand.isToken() && FirstOperand.getToken() ==
"}") {
623 assert(
Operands.size() == 1 &&
"Brackets should be by themselves");
625 getParser().Error(IDLoc,
"Not in a packet");
629 if (matchBundleOptions())
631 return finishBundle(IDLoc, Out);
633 MCInst *SubInst = getParser().getContext().createMCInst();
635 MatchingInlineAsm)) {
641 getParser().getContext(), MII, MCB, *SubInst);
644 return finishBundle(IDLoc, Out);
649 bool HexagonAsmParser::ParseDirective(
AsmToken DirectiveID) {
651 if (IDVal.
lower() ==
".falign")
652 return ParseDirectiveFalign(256, DirectiveID.
getLoc());
653 if ((IDVal.
lower() ==
".lcomm") || (IDVal.
lower() ==
".lcommon"))
654 return ParseDirectiveComm(
true, DirectiveID.
getLoc());
655 if ((IDVal.
lower() ==
".comm") || (IDVal.
lower() ==
".common"))
656 return ParseDirectiveComm(
false, DirectiveID.
getLoc());
657 if (IDVal.
lower() ==
".subsection")
658 return ParseDirectiveSubsection(DirectiveID.
getLoc());
662 bool HexagonAsmParser::ParseDirectiveSubsection(
SMLoc L) {
663 const MCExpr *Subsection =
nullptr;
667 "Invalid subsection directive");
668 getParser().parseExpression(Subsection);
670 if (!Subsection->evaluateAsAbsolute(Res))
671 return Error(L,
"Cannot evaluate subsection number");
674 return TokError(
"unexpected token in directive");
680 if ((Res < 0) && (Res > -8193))
684 getStreamer().SubSection(Subsection);
689 bool HexagonAsmParser::ParseDirectiveFalign(
unsigned Size,
SMLoc L) {
691 int64_t MaxBytesToFill = 15;
699 if (!getParser().parseExpression(
Value)) {
701 auto *MCE = cast<MCConstantExpr>(
Value);
702 uint64_t IntValue = MCE->getValue();
704 return Error(ExprLoc,
"literal value out of range (256) for falign");
705 MaxBytesToFill = IntValue;
708 return Error(ExprLoc,
"not a valid expression for falign directive");
712 getTargetStreamer().emitFAlign(16, MaxBytesToFill);
724 bool HexagonAsmParser::ParseDirectiveComm(
bool IsLocal,
SMLoc Loc) {
727 if (getStreamer().hasRawTextSupport())
731 if (getParser().parseIdentifier(
Name))
732 return TokError(
"expected identifier in directive");
737 return TokError(
"unexpected token in directive");
741 SMLoc SizeLoc = getLexer().getLoc();
742 if (getParser().parseAbsoluteExpression(
Size))
746 SMLoc ByteAlignmentLoc;
749 ByteAlignmentLoc = getLexer().getLoc();
753 return Error(ByteAlignmentLoc,
"alignment must be a power of 2");
756 int64_t AccessAlignment = 0;
760 SMLoc AccessAlignmentLoc;
762 AccessAlignmentLoc = getLexer().getLoc();
763 if (getParser().parseAbsoluteExpression(AccessAlignment))
767 return Error(AccessAlignmentLoc,
"access alignment must be a power of 2");
771 return TokError(
"unexpected token in '.comm' or '.lcomm' directive");
778 return Error(SizeLoc,
"invalid '.comm' or '.lcomm' directive size, can't "
779 "be less than zero");
785 return Error(ByteAlignmentLoc,
"invalid '.comm' or '.lcomm' directive "
786 "alignment, can't be less than zero");
789 return Error(Loc,
"invalid symbol redefinition");
805 bool HexagonAsmParser::RegisterMatchesArch(
unsigned MatchNum)
const {
806 if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].
contains(MatchNum))
807 if (!getSTI().getFeatureBits()[Hexagon::ArchV62])
819 #define GET_MATCHER_IMPLEMENTATION
820 #define GET_REGISTER_MATCHER
821 #include "HexagonGenAsmMatcher.inc"
830 return static_cast<HexagonOperand &
>(Operand).getToken().equals_insensitive(
843 AsmToken const &Token = getParser().getTok();
848 std::pair<StringRef, StringRef> HeadTail =
String.split(
'.');
849 if (!HeadTail.first.empty())
851 HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));
852 if (!HeadTail.second.empty())
853 Operands.push_back(HexagonOperand::CreateToken(
854 getContext(),
String.substr(HeadTail.first.size(), 1), Loc));
856 }
while (!
String.empty());
865 if (!ParseRegister(
Register, Begin, End)) {
876 Warning(Begin,
"Missing parenthesis around predicate register");
877 static char const *LParen =
"(";
878 static char const *RParen =
")";
880 HexagonOperand::CreateToken(getContext(), LParen, Begin));
882 HexagonOperand::CreateReg(getContext(),
Register, Begin, End));
888 HexagonOperand::CreateToken(getContext(), RParen, Begin));
894 Warning(Begin,
"Missing parenthesis around predicate register");
895 static char const *LParen =
"(";
896 static char const *RParen =
")";
898 getContext(), LParen, Begin));
900 HexagonOperand::CreateReg(getContext(),
Register, Begin, End));
906 HexagonOperand::CreateToken(getContext(), RParen, Begin));
912 HexagonOperand::CreateReg(getContext(),
Register, Begin, End));
918 bool HexagonAsmParser::isLabel(
AsmToken &Token) {
923 if (Token.
is(AsmToken::TokenKind::LCurly) ||
924 Token.
is(AsmToken::TokenKind::RCurly))
932 if (!matchRegister(
String.lower()))
937 std::string Collapsed = std::string(Raw);
940 std::pair<StringRef, StringRef> DotSplit = Whole.
split(
'.');
941 if (!matchRegister(DotSplit.first.lower()))
946 bool HexagonAsmParser::handleNoncontigiousRegister(
bool Contigious,
949 Error(Loc,
"Register name is not contigious");
953 Warning(Loc,
"Register name is not contigious");
957 bool HexagonAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
966 StartLoc = getLexer().getLoc();
970 bool NeededWorkaround =
false;
976 Lookahead.push_back(Token);
979 Lookahead.back().getString().data() +
980 Lookahead.back().getString().size();
986 Again = (Contigious &&
Type) || (Workaround &&
Type);
987 NeededWorkaround = NeededWorkaround || (Again && !(Contigious &&
Type));
989 std::string Collapsed = std::string(RawString);
992 std::pair<StringRef, StringRef> DotSplit = FullString.
split(
'.');
993 unsigned DotReg = matchRegister(DotSplit.first.lower());
994 if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
995 if (DotSplit.second.empty()) {
998 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1003 size_t First = RawString.find(
'.');
1007 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1012 std::pair<StringRef, StringRef> ColonSplit =
StringRef(FullString).
split(
':');
1013 unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1014 if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1020 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1024 while (!Lookahead.empty()) {
1044 bool HexagonAsmParser::parseExpression(
MCExpr const *&Expr) {
1048 static char const *
Comma =
",";
1052 switch (Tokens.back().getKind()) {
1053 case AsmToken::TokenKind::Hash:
1054 if (Tokens.size() > 1)
1055 if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {
1056 Tokens.
insert(Tokens.end() - 2,
1061 case AsmToken::TokenKind::RCurly:
1062 case AsmToken::TokenKind::EndOfStatement:
1070 while (!Tokens.empty()) {
1071 Lexer.
UnLex(Tokens.back());
1075 return getParser().parseExpression(Expr, Loc);
1079 if (implicitExpressionLocation(
Operands)) {
1082 MCExpr const *Expr =
nullptr;
1083 bool Error = parseExpression(Expr);
1087 HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));
1108 Operands.push_back(HexagonOperand::CreateToken(
1115 Operands.push_back(HexagonOperand::CreateToken(
1131 Operands.push_back(HexagonOperand::CreateToken(
1133 Operands.push_back(HexagonOperand::CreateToken(
1139 bool MustNotExtend =
false;
1140 bool ImplicitExpression = implicitExpressionLocation(
Operands);
1142 if (!ImplicitExpression)
1143 Operands.push_back(HexagonOperand::CreateToken(
1146 bool MustExtend =
false;
1147 bool HiOnly =
false;
1148 bool LoOnly =
false;
1152 }
else if (ImplicitExpression)
1153 MustNotExtend =
true;
1157 if (
String.lower() ==
"hi") {
1159 }
else if (
String.lower() ==
"lo") {
1162 if (HiOnly || LoOnly) {
1172 MCExpr const *Expr =
nullptr;
1173 if (parseExpression(Expr))
1178 if (Expr->evaluateAsAbsolute(
Value)) {
1182 if (HiOnly || LoOnly)
1188 if (!
Value.isAbsolute()) {
1189 switch (
Value.getAccessVariant()) {
1190 case MCSymbolRefExpr::VariantKind::VK_TPREL:
1191 case MCSymbolRefExpr::VariantKind::VK_DTPREL:
1193 MustNotExtend = !MustExtend;
1204 std::unique_ptr<HexagonOperand> Operand =
1205 HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);
1212 if (parseExpressionOrOperand(
Operands))
1220 getLexer().UnLex(
ID);
1239 HexagonOperand *
Op =
static_cast<HexagonOperand *
>(&AsmOp);
1244 return Op->isImm() &&
Op->Imm.Val->evaluateAsAbsolute(
Value) &&
Value == 0
1246 : Match_InvalidOperand;
1250 return Op->isImm() &&
Op->Imm.Val->evaluateAsAbsolute(
Value) &&
Value == 1
1252 : Match_InvalidOperand;
1255 if (
Op->Kind == HexagonOperand::Token &&
Kind != InvalidMatchClass) {
1257 if (matchTokenString(myStringRef.
lower()) == (MatchClassKind)
Kind)
1258 return Match_Success;
1259 if (matchTokenString(myStringRef.
upper()) == (MatchClassKind)
Kind)
1260 return Match_Success;
1267 return Match_InvalidOperand;
1271 bool HexagonAsmParser::OutOfRange(
SMLoc IDLoc,
long long Val,
long long Max) {
1274 ES <<
"value " << Val <<
"(" <<
format_hex(Val, 0) <<
") out of range: ";
1278 ES <<
Max <<
"-" << (-
Max - 1);
1282 int HexagonAsmParser::processInstruction(
MCInst &Inst,
1287 const std::string r =
"r";
1288 const std::string v =
"v";
1289 const std::string Colon =
":";
1290 using RegPairVals = std::pair<unsigned, unsigned>;
1291 auto GetRegPair = [
this, r](RegPairVals RegPair) {
1292 const std::string R1 = r + utostr(RegPair.first);
1293 const std::string
R2 = r + utostr(RegPair.second);
1295 return std::make_pair(matchRegister(R1), matchRegister(
R2));
1297 auto GetScalarRegs = [RI, GetRegPair](
unsigned RegPair) {
1299 const RegPairVals RegPair_ = std::make_pair(
Lower + 1,
Lower);
1301 return GetRegPair(RegPair_);
1303 auto GetVecRegs = [GetRegPair](
unsigned VecRegPair) {
1304 const RegPairVals RegPair =
1307 return GetRegPair(RegPair);
1316 "Found pseudo instruction with no expansion");
1322 case Hexagon::J2_trap1:
1323 if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
1326 if (
Rx.getReg() != Hexagon::R0 || Ry.
getReg() != Hexagon::R0) {
1327 Error(IDLoc,
"trap1 can only have register r0 as operand");
1328 return Match_InvalidOperand;
1333 case Hexagon::A2_iconst: {
1345 case Hexagon::M4_mpyrr_addr:
1346 case Hexagon::S4_addi_asl_ri:
1347 case Hexagon::S4_addi_lsr_ri:
1348 case Hexagon::S4_andi_asl_ri:
1349 case Hexagon::S4_andi_lsr_ri:
1350 case Hexagon::S4_ori_asl_ri:
1351 case Hexagon::S4_ori_lsr_ri:
1352 case Hexagon::S4_or_andix:
1353 case Hexagon::S4_subi_asl_ri:
1354 case Hexagon::S4_subi_lsr_ri: {
1358 return Match_InvalidOperand;
1362 case Hexagon::C2_cmpgei: {
1372 case Hexagon::C2_cmpgeui: {
1398 case Hexagon::A2_tfrp: {
1400 const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.
getReg());
1401 MO.
setReg(RegPair.first);
1407 case Hexagon::A2_tfrpt:
1408 case Hexagon::A2_tfrpf: {
1410 const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.
getReg());
1411 MO.
setReg(RegPair.first);
1414 ? Hexagon::C2_ccombinewt
1415 : Hexagon::C2_ccombinewf);
1418 case Hexagon::A2_tfrptnew:
1419 case Hexagon::A2_tfrpfnew: {
1421 const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.
getReg());
1422 MO.
setReg(RegPair.first);
1425 ? Hexagon::C2_ccombinewnewt
1426 : Hexagon::C2_ccombinewnewf);
1431 case Hexagon::V6_vassignp: {
1433 const std::pair<unsigned, unsigned> RegPair = GetVecRegs(MO.
getReg());
1434 MO.
setReg(RegPair.first);
1445 case Hexagon::CONST64:
1455 std::string myCharStr;
1465 std::string myImmStr = utohexstr(
static_cast<uint32_t>(
Value));
1466 myCharStr =
StringRef(
".gnu.linkonce.l4.CONST_00000000")
1471 std::string myImmStr = utohexstr(
Value);
1472 myCharStr =
StringRef(
".gnu.linkonce.l8.CONST_0000000000000000")
1480 }
else if (MO_1.
isExpr()) {
1482 myCharStr =
".lita";
1489 unsigned byteSize =
is32bit ? 4 : 8;
1490 getStreamer().emitCodeAlignment(byteSize, &getSTI(), byteSize);
1498 Sym = getContext().getOrCreateSymbol(
StringRef(myCharStr.c_str() + 16));
1500 getStreamer().emitLabel(Sym);
1501 getStreamer().emitSymbolAttribute(Sym,
MCSA_Global);
1502 getStreamer().emitIntValue(
Value, byteSize);
1504 }
else if (MO_1.
isExpr()) {
1505 const char *StringStart =
nullptr;
1506 const char *StringEnd =
nullptr;
1507 if (*
Operands[4]->getStartLoc().getPointer() ==
'#') {
1508 StringStart =
Operands[5]->getStartLoc().getPointer();
1509 StringEnd =
Operands[6]->getStartLoc().getPointer();
1511 StringStart =
Operands[4]->getStartLoc().getPointer();
1512 StringEnd =
Operands[5]->getStartLoc().getPointer();
1515 unsigned size = StringEnd - StringStart;
1516 std::string DotConst =
".CONST_";
1517 Sym = getContext().getOrCreateSymbol(DotConst +
1522 getStreamer().emitLabel(Sym);
1523 getStreamer().emitSymbolAttribute(Sym,
MCSA_Local);
1524 getStreamer().emitValue(MO_1.
getExpr(), 4);
1534 TmpInst.
setOpcode(Hexagon::L2_loadrigp);
1536 TmpInst.
setOpcode(Hexagon::L2_loadrdgp);
1547 case Hexagon::A2_tfrpi: {
1559 case Hexagon::TFRI64_V4: {
1566 OutOfRange(IDLoc, s8, -128);
1584 case Hexagon::TFRI64_V2_ext: {
1591 if (s8 < -128 || s8 > 127)
1592 OutOfRange(IDLoc, s8, -128);
1599 case Hexagon::A4_combineii: {
1605 if (s8 < -128 || s8 > 127)
1606 OutOfRange(IDLoc, s8, -128);
1613 case Hexagon::S2_tableidxb_goodsyntax:
1617 case Hexagon::S2_tableidxh_goodsyntax: {
1627 TmpInst.
setOpcode(Hexagon::S2_tableidxh);
1637 case Hexagon::S2_tableidxw_goodsyntax: {
1647 TmpInst.
setOpcode(Hexagon::S2_tableidxw);
1657 case Hexagon::S2_tableidxd_goodsyntax: {
1667 TmpInst.
setOpcode(Hexagon::S2_tableidxd);
1677 case Hexagon::M2_mpyui:
1680 case Hexagon::M2_mpysmi: {
1689 return Match_InvalidOperand;
1692 return Match_InvalidOperand;
1706 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1712 return Match_InvalidOperand;
1724 TmpInst.
setOpcode(Hexagon::S2_asr_i_r_rnd);
1735 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1742 return Match_InvalidOperand;
1746 std::string R1 = r + utostr(RegPairNum + 1);
1748 Rss.
setReg(matchRegister(Reg1));
1750 std::string
R2 = r + utostr(RegPairNum);
1752 TmpInst.
setOpcode(Hexagon::A2_combinew);
1762 Inst.
setOpcode(Hexagon::S2_asr_i_p_rnd);
1767 case Hexagon::A4_boundscheck: {
1771 Inst.
setOpcode(Hexagon::A4_boundscheck_hi);
1772 std::string
Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1774 Rs.
setReg(matchRegister(RegPair));
1776 Inst.
setOpcode(Hexagon::A4_boundscheck_lo);
1777 std::string
Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1779 Rs.
setReg(matchRegister(RegPair));
1784 case Hexagon::A2_addsp: {
1789 std::string
Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1791 Rs.
setReg(matchRegister(RegPair));
1794 std::string
Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1796 Rs.
setReg(matchRegister(RegPair));
1801 case Hexagon::M2_vrcmpys_s1: {
1805 Inst.
setOpcode(Hexagon::M2_vrcmpys_s1_h);
1806 std::string
Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1808 Rt.
setReg(matchRegister(RegPair));
1810 Inst.
setOpcode(Hexagon::M2_vrcmpys_s1_l);
1811 std::string
Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1813 Rt.
setReg(matchRegister(RegPair));
1818 case Hexagon::M2_vrcmpys_acc_s1: {
1825 TmpInst.
setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
1826 std::string
Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1828 Rt.
setReg(matchRegister(RegPair));
1830 TmpInst.
setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
1831 std::string
Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1833 Rt.
setReg(matchRegister(RegPair));
1844 case Hexagon::M2_vrcmpys_s1rp: {
1848 Inst.
setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
1849 std::string
Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1851 Rt.
setReg(matchRegister(RegPair));
1853 Inst.
setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
1854 std::string
Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1856 Rt.
setReg(matchRegister(RegPair));
1861 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
1866 return Match_InvalidOperand;
1874 Inst.
setOpcode(Hexagon::S5_asrhub_rnd_sat);
1879 case Hexagon::S5_vasrhrnd_goodsyntax: {
1886 return Match_InvalidOperand;
1890 std::string R1 = r + utostr(RegPairNum + 1);
1892 Rss.
setReg(matchRegister(Reg1));
1894 std::string
R2 = r + utostr(RegPairNum);
1896 TmpInst.
setOpcode(Hexagon::A2_combinew);
1911 case Hexagon::A2_not: {
1923 case Hexagon::PS_loadrubabs:
1927 case Hexagon::PS_loadrbabs:
1931 case Hexagon::PS_loadruhabs:
1935 case Hexagon::PS_loadrhabs:
1939 case Hexagon::PS_loadriabs:
1943 case Hexagon::PS_loadrdabs:
1947 case Hexagon::PS_storerbabs:
1951 case Hexagon::PS_storerhabs:
1955 case Hexagon::PS_storerfabs:
1959 case Hexagon::PS_storeriabs:
1963 case Hexagon::PS_storerdabs:
1967 case Hexagon::PS_storerbnewabs:
1969 Inst.
setOpcode(Hexagon::S2_storerbnewgp);
1971 case Hexagon::PS_storerhnewabs:
1973 Inst.
setOpcode(Hexagon::S2_storerhnewgp);
1975 case Hexagon::PS_storerinewabs:
1977 Inst.
setOpcode(Hexagon::S2_storerinewgp);
1979 case Hexagon::A2_zxtb: {
1987 return Match_Success;