31#define DEBUG_TYPE "arm-pseudo"
35 cl::desc(
"Verify machine code after expanding ARM pseudos"));
37#define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
54 MachineFunctionProperties::Property::NoVRegs);
72 unsigned Opc,
bool IsExt);
110 unsigned StrexOp,
unsigned UxtOp,
117 char ARMExpandPseudo::ID = 0;
125void ARMExpandPseudo::TransferImpOps(
MachineInstr &OldMI,
131 assert(MO.isReg() && MO.getReg());
144 enum NEONRegSpacing {
155 struct NEONLdStTableEntry {
160 bool hasWritebackOperand;
169 bool copyAllListRegs;
172 bool operator<(
const NEONLdStTableEntry &TE)
const {
173 return PseudoOpc <
TE.PseudoOpc;
175 friend bool operator<(
const NEONLdStTableEntry &TE,
unsigned PseudoOpc) {
176 return TE.PseudoOpc < PseudoOpc;
179 const NEONLdStTableEntry &TE) {
180 return PseudoOpc <
TE.PseudoOpc;
186{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16,
true,
false,
false, EvenDblSpc, 1, 4 ,
true},
187{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD,
true,
true,
true, EvenDblSpc, 1, 4 ,
true},
188{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32,
true,
false,
false, EvenDblSpc, 1, 2 ,
true},
189{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD,
true,
true,
true, EvenDblSpc, 1, 2 ,
true},
190{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8,
true,
false,
false, EvenDblSpc, 1, 8 ,
true},
191{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD,
true,
true,
true, EvenDblSpc, 1, 8 ,
true},
193{ ARM::VLD1d16QPseudo, ARM::VLD1d16Q,
true,
false,
false, SingleSpc, 4, 4 ,
false},
194{ ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
195{ ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
196{ ARM::VLD1d16TPseudo, ARM::VLD1d16T,
true,
false,
false, SingleSpc, 3, 4 ,
false},
197{ ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed,
true,
true,
false, SingleSpc, 3, 4 ,
false},
198{ ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register,
true,
true,
true, SingleSpc, 3, 4 ,
false},
200{ ARM::VLD1d32QPseudo, ARM::VLD1d32Q,
true,
false,
false, SingleSpc, 4, 2 ,
false},
201{ ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
202{ ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
203{ ARM::VLD1d32TPseudo, ARM::VLD1d32T,
true,
false,
false, SingleSpc, 3, 2 ,
false},
204{ ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed,
true,
true,
false, SingleSpc, 3, 2 ,
false},
205{ ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register,
true,
true,
true, SingleSpc, 3, 2 ,
false},
207{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleSpc, 4, 1 ,
false},
208{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed,
true,
true,
false, SingleSpc, 4, 1 ,
false},
209{ ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register,
true,
true,
true, SingleSpc, 4, 1 ,
false},
210{ ARM::VLD1d64TPseudo, ARM::VLD1d64T,
true,
false,
false, SingleSpc, 3, 1 ,
false},
211{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed,
true,
true,
false, SingleSpc, 3, 1 ,
false},
212{ ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register,
true,
true,
true, SingleSpc, 3, 1 ,
false},
214{ ARM::VLD1d8QPseudo, ARM::VLD1d8Q,
true,
false,
false, SingleSpc, 4, 8 ,
false},
215{ ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
216{ ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
217{ ARM::VLD1d8TPseudo, ARM::VLD1d8T,
true,
false,
false, SingleSpc, 3, 8 ,
false},
218{ ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed,
true,
true,
false, SingleSpc, 3, 8 ,
false},
219{ ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register,
true,
true,
true, SingleSpc, 3, 8 ,
false},
221{ ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q,
true,
false,
false, SingleHighQSpc, 4, 4 ,
false},
222{ ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 4 ,
false},
223{ ARM::VLD1q16HighTPseudo, ARM::VLD1d16T,
true,
false,
false, SingleHighTSpc, 3, 4 ,
false},
224{ ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 4 ,
false},
225{ ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 4 ,
false},
226{ ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 4 ,
false},
228{ ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q,
true,
false,
false, SingleHighQSpc, 4, 2 ,
false},
229{ ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 2 ,
false},
230{ ARM::VLD1q32HighTPseudo, ARM::VLD1d32T,
true,
false,
false, SingleHighTSpc, 3, 2 ,
false},
231{ ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 2 ,
false},
232{ ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 2 ,
false},
233{ ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 2 ,
false},
235{ ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleHighQSpc, 4, 1 ,
false},
236{ ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 1 ,
false},
237{ ARM::VLD1q64HighTPseudo, ARM::VLD1d64T,
true,
false,
false, SingleHighTSpc, 3, 1 ,
false},
238{ ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 1 ,
false},
239{ ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 1 ,
false},
240{ ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 1 ,
false},
242{ ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q,
true,
false,
false, SingleHighQSpc, 4, 8 ,
false},
243{ ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 8 ,
false},
244{ ARM::VLD1q8HighTPseudo, ARM::VLD1d8T,
true,
false,
false, SingleHighTSpc, 3, 8 ,
false},
245{ ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 8 ,
false},
246{ ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 8 ,
false},
247{ ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 8 ,
false},
249{ ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2,
true,
false,
false, EvenDblSpc, 2, 4 ,
false},
250{ ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2,
true,
false,
false, OddDblSpc, 2, 4 ,
false},
251{ ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 4 ,
false},
252{ ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register,
true,
true,
true, OddDblSpc, 2, 4 ,
false},
253{ ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2,
true,
false,
false, EvenDblSpc, 2, 2 ,
false},
254{ ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2,
true,
false,
false, OddDblSpc, 2, 2 ,
false},
255{ ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 2 ,
false},
256{ ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register,
true,
true,
true, OddDblSpc, 2, 2 ,
false},
257{ ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2,
true,
false,
false, EvenDblSpc, 2, 8 ,
false},
258{ ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2,
true,
false,
false, OddDblSpc, 2, 8 ,
false},
259{ ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 8 ,
false},
260{ ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register,
true,
true,
true, OddDblSpc, 2, 8 ,
false},
262{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16,
true,
false,
false, SingleSpc, 2, 4 ,
true},
263{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD,
true,
true,
true, SingleSpc, 2, 4 ,
true},
264{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32,
true,
false,
false, SingleSpc, 2, 2 ,
true},
265{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD,
true,
true,
true, SingleSpc, 2, 2 ,
true},
266{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8,
true,
false,
false, SingleSpc, 2, 8 ,
true},
267{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD,
true,
true,
true, SingleSpc, 2, 8 ,
true},
268{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16,
true,
false,
false, EvenDblSpc, 2, 4 ,
true},
269{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD,
true,
true,
true, EvenDblSpc, 2, 4 ,
true},
270{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32,
true,
false,
false, EvenDblSpc, 2, 2 ,
true},
271{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD,
true,
true,
true, EvenDblSpc, 2, 2 ,
true},
273{ ARM::VLD2q16Pseudo, ARM::VLD2q16,
true,
false,
false, SingleSpc, 4, 4 ,
false},
274{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
275{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
276{ ARM::VLD2q32Pseudo, ARM::VLD2q32,
true,
false,
false, SingleSpc, 4, 2 ,
false},
277{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
278{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
279{ ARM::VLD2q8Pseudo, ARM::VLD2q8,
true,
false,
false, SingleSpc, 4, 8 ,
false},
280{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
281{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
283{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16,
true,
false,
false, SingleSpc, 3, 4,
true},
284{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD,
true,
true,
true, SingleSpc, 3, 4,
true},
285{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32,
true,
false,
false, SingleSpc, 3, 2,
true},
286{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD,
true,
true,
true, SingleSpc, 3, 2,
true},
287{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8,
true,
false,
false, SingleSpc, 3, 8,
true},
288{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD,
true,
true,
true, SingleSpc, 3, 8,
true},
289{ ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
290{ ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
291{ ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
292{ ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
293{ ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
294{ ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
295{ ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8,
true,
false,
false, EvenDblSpc, 3, 8 ,
true},
296{ ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
297{ ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
299{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
300{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
301{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
302{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
303{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
304{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
305{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
306{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
307{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
308{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
310{ ARM::VLD3d16Pseudo, ARM::VLD3d16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
311{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
312{ ARM::VLD3d32Pseudo, ARM::VLD3d32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
313{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
314{ ARM::VLD3d8Pseudo, ARM::VLD3d8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
315{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
317{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
318{ ARM::VLD3q16oddPseudo, ARM::VLD3q16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
319{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
320{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
321{ ARM::VLD3q32oddPseudo, ARM::VLD3q32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
322{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
323{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, EvenDblSpc, 3, 8 ,
true},
324{ ARM::VLD3q8oddPseudo, ARM::VLD3q8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
325{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
327{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16,
true,
false,
false, SingleSpc, 4, 4,
true},
328{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD,
true,
true,
true, SingleSpc, 4, 4,
true},
329{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32,
true,
false,
false, SingleSpc, 4, 2,
true},
330{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD,
true,
true,
true, SingleSpc, 4, 2,
true},
331{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8,
true,
false,
false, SingleSpc, 4, 8,
true},
332{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD,
true,
true,
true, SingleSpc, 4, 8,
true},
333{ ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
334{ ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
335{ ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
336{ ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
337{ ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
338{ ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
339{ ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8,
true,
false,
false, EvenDblSpc, 4, 8 ,
true},
340{ ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
341{ ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
343{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
344{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
345{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
346{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
347{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
348{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
349{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
350{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
351{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
352{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
354{ ARM::VLD4d16Pseudo, ARM::VLD4d16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
355{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
356{ ARM::VLD4d32Pseudo, ARM::VLD4d32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
357{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
358{ ARM::VLD4d8Pseudo, ARM::VLD4d8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
359{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
361{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
362{ ARM::VLD4q16oddPseudo, ARM::VLD4q16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
363{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
364{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
365{ ARM::VLD4q32oddPseudo, ARM::VLD4q32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
366{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
367{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, EvenDblSpc, 4, 8 ,
true},
368{ ARM::VLD4q8oddPseudo, ARM::VLD4q8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
369{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
371{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16,
false,
false,
false, EvenDblSpc, 1, 4 ,
true},
372{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,
false,
true,
true, EvenDblSpc, 1, 4 ,
true},
373{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32,
false,
false,
false, EvenDblSpc, 1, 2 ,
true},
374{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,
false,
true,
true, EvenDblSpc, 1, 2 ,
true},
375{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8,
false,
false,
false, EvenDblSpc, 1, 8 ,
true},
376{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD,
false,
true,
true, EvenDblSpc, 1, 8 ,
true},
378{ ARM::VST1d16QPseudo, ARM::VST1d16Q,
false,
false,
false, SingleSpc, 4, 4 ,
false},
379{ ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
380{ ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
381{ ARM::VST1d16TPseudo, ARM::VST1d16T,
false,
false,
false, SingleSpc, 3, 4 ,
false},
382{ ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed,
false,
true,
false, SingleSpc, 3, 4 ,
false},
383{ ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register,
false,
true,
true, SingleSpc, 3, 4 ,
false},
385{ ARM::VST1d32QPseudo, ARM::VST1d32Q,
false,
false,
false, SingleSpc, 4, 2 ,
false},
386{ ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
387{ ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
388{ ARM::VST1d32TPseudo, ARM::VST1d32T,
false,
false,
false, SingleSpc, 3, 2 ,
false},
389{ ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed,
false,
true,
false, SingleSpc, 3, 2 ,
false},
390{ ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register,
false,
true,
true, SingleSpc, 3, 2 ,
false},
392{ ARM::VST1d64QPseudo, ARM::VST1d64Q,
false,
false,
false, SingleSpc, 4, 1 ,
false},
393{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed,
false,
true,
false, SingleSpc, 4, 1 ,
false},
394{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register,
false,
true,
true, SingleSpc, 4, 1 ,
false},
395{ ARM::VST1d64TPseudo, ARM::VST1d64T,
false,
false,
false, SingleSpc, 3, 1 ,
false},
396{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed,
false,
true,
false, SingleSpc, 3, 1 ,
false},
397{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register,
false,
true,
true, SingleSpc, 3, 1 ,
false},
399{ ARM::VST1d8QPseudo, ARM::VST1d8Q,
false,
false,
false, SingleSpc, 4, 8 ,
false},
400{ ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
401{ ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
402{ ARM::VST1d8TPseudo, ARM::VST1d8T,
false,
false,
false, SingleSpc, 3, 8 ,
false},
403{ ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed,
false,
true,
false, SingleSpc, 3, 8 ,
false},
404{ ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register,
false,
true,
true, SingleSpc, 3, 8 ,
false},
406{ ARM::VST1q16HighQPseudo, ARM::VST1d16Q,
false,
false,
false, SingleHighQSpc, 4, 4 ,
false},
407{ ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
408{ ARM::VST1q16HighTPseudo, ARM::VST1d16T,
false,
false,
false, SingleHighTSpc, 3, 4 ,
false},
409{ ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 4 ,
false},
410{ ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 4 ,
false},
411{ ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 4 ,
false},
413{ ARM::VST1q32HighQPseudo, ARM::VST1d32Q,
false,
false,
false, SingleHighQSpc, 4, 2 ,
false},
414{ ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
415{ ARM::VST1q32HighTPseudo, ARM::VST1d32T,
false,
false,
false, SingleHighTSpc, 3, 2 ,
false},
416{ ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 2 ,
false},
417{ ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 2 ,
false},
418{ ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 2 ,
false},
420{ ARM::VST1q64HighQPseudo, ARM::VST1d64Q,
false,
false,
false, SingleHighQSpc, 4, 1 ,
false},
421{ ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
422{ ARM::VST1q64HighTPseudo, ARM::VST1d64T,
false,
false,
false, SingleHighTSpc, 3, 1 ,
false},
423{ ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 1 ,
false},
424{ ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 1 ,
false},
425{ ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 1 ,
false},
427{ ARM::VST1q8HighQPseudo, ARM::VST1d8Q,
false,
false,
false, SingleHighQSpc, 4, 8 ,
false},
428{ ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
429{ ARM::VST1q8HighTPseudo, ARM::VST1d8T,
false,
false,
false, SingleHighTSpc, 3, 8 ,
false},
430{ ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 8 ,
false},
431{ ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 8 ,
false},
432{ ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 8 ,
false},
434{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16,
false,
false,
false, SingleSpc, 2, 4 ,
true},
435{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD,
false,
true,
true, SingleSpc, 2, 4 ,
true},
436{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32,
false,
false,
false, SingleSpc, 2, 2 ,
true},
437{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD,
false,
true,
true, SingleSpc, 2, 2 ,
true},
438{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8,
false,
false,
false, SingleSpc, 2, 8 ,
true},
439{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD,
false,
true,
true, SingleSpc, 2, 8 ,
true},
440{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16,
false,
false,
false, EvenDblSpc, 2, 4,
true},
441{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD,
false,
true,
true, EvenDblSpc, 2, 4,
true},
442{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32,
false,
false,
false, EvenDblSpc, 2, 2,
true},
443{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD,
false,
true,
true, EvenDblSpc, 2, 2,
true},
445{ ARM::VST2q16Pseudo, ARM::VST2q16,
false,
false,
false, SingleSpc, 4, 4 ,
false},
446{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
447{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
448{ ARM::VST2q32Pseudo, ARM::VST2q32,
false,
false,
false, SingleSpc, 4, 2 ,
false},
449{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
450{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
451{ ARM::VST2q8Pseudo, ARM::VST2q8,
false,
false,
false, SingleSpc, 4, 8 ,
false},
452{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
453{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
455{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
456{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
457{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
458{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
459{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
460{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
461{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16,
false,
false,
false, EvenDblSpc, 3, 4,
true},
462{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD,
false,
true,
true, EvenDblSpc, 3, 4,
true},
463{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32,
false,
false,
false, EvenDblSpc, 3, 2,
true},
464{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD,
false,
true,
true, EvenDblSpc, 3, 2,
true},
466{ ARM::VST3d16Pseudo, ARM::VST3d16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
467{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
468{ ARM::VST3d32Pseudo, ARM::VST3d32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
469{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
470{ ARM::VST3d8Pseudo, ARM::VST3d8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
471{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
473{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, EvenDblSpc, 3, 4 ,
true},
474{ ARM::VST3q16oddPseudo, ARM::VST3q16,
false,
false,
false, OddDblSpc, 3, 4 ,
true},
475{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, OddDblSpc, 3, 4 ,
true},
476{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, EvenDblSpc, 3, 2 ,
true},
477{ ARM::VST3q32oddPseudo, ARM::VST3q32,
false,
false,
false, OddDblSpc, 3, 2 ,
true},
478{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, OddDblSpc, 3, 2 ,
true},
479{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, EvenDblSpc, 3, 8 ,
true},
480{ ARM::VST3q8oddPseudo, ARM::VST3q8,
false,
false,
false, OddDblSpc, 3, 8 ,
true},
481{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, OddDblSpc, 3, 8 ,
true},
483{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
484{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
485{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
486{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
487{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
488{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
489{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16,
false,
false,
false, EvenDblSpc, 4, 4,
true},
490{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD,
false,
true,
true, EvenDblSpc, 4, 4,
true},
491{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32,
false,
false,
false, EvenDblSpc, 4, 2,
true},
492{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD,
false,
true,
true, EvenDblSpc, 4, 2,
true},
494{ ARM::VST4d16Pseudo, ARM::VST4d16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
495{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
496{ ARM::VST4d32Pseudo, ARM::VST4d32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
497{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
498{ ARM::VST4d8Pseudo, ARM::VST4d8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
499{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
501{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, EvenDblSpc, 4, 4 ,
true},
502{ ARM::VST4q16oddPseudo, ARM::VST4q16,
false,
false,
false, OddDblSpc, 4, 4 ,
true},
503{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, OddDblSpc, 4, 4 ,
true},
504{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, EvenDblSpc, 4, 2 ,
true},
505{ ARM::VST4q32oddPseudo, ARM::VST4q32,
false,
false,
false, OddDblSpc, 4, 2 ,
true},
506{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, OddDblSpc, 4, 2 ,
true},
507{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, EvenDblSpc, 4, 8 ,
true},
508{ ARM::VST4q8oddPseudo, ARM::VST4q8,
false,
false,
false, OddDblSpc, 4, 8 ,
true},
509{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, OddDblSpc, 4, 8 ,
true}
517 static std::atomic<bool> TableChecked(
false);
518 if (!TableChecked.load(std::memory_order_relaxed)) {
520 TableChecked.store(
true, std::memory_order_relaxed);
535 unsigned &D1,
unsigned &D2,
unsigned &D3) {
536 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
537 D0 =
TRI->getSubReg(Reg, ARM::dsub_0);
538 D1 =
TRI->getSubReg(Reg, ARM::dsub_1);
539 D2 =
TRI->getSubReg(Reg, ARM::dsub_2);
540 D3 =
TRI->getSubReg(Reg, ARM::dsub_3);
541 }
else if (RegSpc == SingleHighQSpc) {
542 D0 =
TRI->getSubReg(Reg, ARM::dsub_4);
543 D1 =
TRI->getSubReg(Reg, ARM::dsub_5);
544 D2 =
TRI->getSubReg(Reg, ARM::dsub_6);
545 D3 =
TRI->getSubReg(Reg, ARM::dsub_7);
546 }
else if (RegSpc == SingleHighTSpc) {
547 D0 =
TRI->getSubReg(Reg, ARM::dsub_3);
548 D1 =
TRI->getSubReg(Reg, ARM::dsub_4);
549 D2 =
TRI->getSubReg(Reg, ARM::dsub_5);
550 D3 =
TRI->getSubReg(Reg, ARM::dsub_6);
551 }
else if (RegSpc == EvenDblSpc) {
552 D0 =
TRI->getSubReg(Reg, ARM::dsub_0);
553 D1 =
TRI->getSubReg(Reg, ARM::dsub_2);
554 D2 =
TRI->getSubReg(Reg, ARM::dsub_4);
555 D3 =
TRI->getSubReg(Reg, ARM::dsub_6);
557 assert(RegSpc == OddDblSpc &&
"unknown register spacing");
558 D0 =
TRI->getSubReg(Reg, ARM::dsub_1);
559 D1 =
TRI->getSubReg(Reg, ARM::dsub_3);
560 D2 =
TRI->getSubReg(Reg, ARM::dsub_5);
561 D3 =
TRI->getSubReg(Reg, ARM::dsub_7);
573 assert(TableEntry && TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
574 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
575 unsigned NumRegs = TableEntry->NumRegs;
578 TII->get(TableEntry->RealOpc));
581 bool DstIsDead =
MI.getOperand(OpIdx).isDead();
582 Register DstReg =
MI.getOperand(OpIdx++).getReg();
584 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
585 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
586 TableEntry->RealOpc == ARM::VLD2DUPd32x2 ||
587 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
588 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
589 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed ||
590 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register ||
591 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register ||
592 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register;
595 unsigned SubRegIndex;
596 if (RegSpc == EvenDblSpc) {
597 SubRegIndex = ARM::dsub_0;
599 assert(RegSpc == OddDblSpc &&
"Unexpected spacing!");
600 SubRegIndex = ARM::dsub_1;
603 unsigned DstRegPair =
TRI->getMatchingSuperReg(
SubReg, ARM::dsub_0,
604 &ARM::DPairSpcRegClass);
607 unsigned D0, D1, D2, D3;
610 if (NumRegs > 1 && TableEntry->copyAllListRegs)
612 if (NumRegs > 2 && TableEntry->copyAllListRegs)
614 if (NumRegs > 3 && TableEntry->copyAllListRegs)
618 if (TableEntry->isUpdating)
619 MIB.add(
MI.getOperand(OpIdx++));
622 MIB.add(
MI.getOperand(OpIdx++));
623 MIB.add(
MI.getOperand(OpIdx++));
626 if (TableEntry->hasWritebackOperand) {
635 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
636 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
637 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
638 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
639 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
640 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
641 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
642 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed ||
643 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
644 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
645 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) {
647 "A fixed writing-back pseudo instruction provides an offset "
657 unsigned SrcOpIdx = 0;
659 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc ||
660 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc ||
661 RegSpc == SingleHighTSpc)
666 MIB.add(
MI.getOperand(OpIdx++));
667 MIB.add(
MI.getOperand(OpIdx++));
678 TransferImpOps(
MI, MIB, MIB);
681 MIB.cloneMemRefs(
MI);
682 MI.eraseFromParent();
694 assert(TableEntry && !TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
695 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
696 unsigned NumRegs = TableEntry->NumRegs;
699 TII->get(TableEntry->RealOpc));
701 if (TableEntry->isUpdating)
702 MIB.add(
MI.getOperand(OpIdx++));
705 MIB.add(
MI.getOperand(OpIdx++));
706 MIB.add(
MI.getOperand(OpIdx++));
708 if (TableEntry->hasWritebackOperand) {
717 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
718 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
719 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
720 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
721 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
722 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
723 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
724 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
726 "A fixed writing-back pseudo instruction provides an offset "
733 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
734 bool SrcIsUndef =
MI.getOperand(OpIdx).isUndef();
735 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
736 unsigned D0, D1, D2, D3;
739 if (NumRegs > 1 && TableEntry->copyAllListRegs)
741 if (NumRegs > 2 && TableEntry->copyAllListRegs)
743 if (NumRegs > 3 && TableEntry->copyAllListRegs)
747 MIB.add(
MI.getOperand(OpIdx++));
748 MIB.add(
MI.getOperand(OpIdx++));
750 if (SrcIsKill && !SrcIsUndef)
751 MIB->addRegisterKilled(SrcReg,
TRI,
true);
752 else if (!SrcIsUndef)
754 TransferImpOps(
MI, MIB, MIB);
757 MIB.cloneMemRefs(
MI);
758 MI.eraseFromParent();
770 assert(TableEntry &&
"NEONLdStTable lookup failed");
771 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
772 unsigned NumRegs = TableEntry->NumRegs;
773 unsigned RegElts = TableEntry->RegElts;
776 TII->get(TableEntry->RealOpc));
780 unsigned Lane =
MI.getOperand(
MI.getDesc().getNumOperands() - 3).getImm();
783 assert(RegSpc != OddDblSpc &&
"unexpected register spacing for VLD/VST-lane");
784 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
788 assert(Lane < RegElts &&
"out of range lane for VLD/VST-lane");
790 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
792 bool DstIsDead =
false;
793 if (TableEntry->IsLoad) {
794 DstIsDead =
MI.getOperand(OpIdx).isDead();
795 DstReg =
MI.getOperand(OpIdx++).getReg();
806 if (TableEntry->isUpdating)
807 MIB.add(
MI.getOperand(OpIdx++));
810 MIB.add(
MI.getOperand(OpIdx++));
811 MIB.add(
MI.getOperand(OpIdx++));
813 if (TableEntry->hasWritebackOperand)
814 MIB.add(
MI.getOperand(OpIdx++));
818 if (!TableEntry->IsLoad)
824 MIB.addReg(D0, SrcFlags);
826 MIB.addReg(D1, SrcFlags);
828 MIB.addReg(D2, SrcFlags);
830 MIB.addReg(D3, SrcFlags);
837 MIB.add(
MI.getOperand(OpIdx++));
838 MIB.add(
MI.getOperand(OpIdx++));
843 if (TableEntry->IsLoad)
846 TransferImpOps(
MI, MIB, MIB);
848 MIB.cloneMemRefs(
MI);
849 MI.eraseFromParent();
855 unsigned Opc,
bool IsExt) {
864 MIB.
add(
MI.getOperand(OpIdx++));
870 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
871 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
872 unsigned D0, D1, D2, D3;
881 MIB.
add(
MI.getOperand(OpIdx++));
882 MIB.
add(
MI.getOperand(OpIdx++));
886 TransferImpOps(
MI, MIB, MIB);
887 MI.eraseFromParent();
895 MI.getOpcode() == ARM::MQQPRStore ||
MI.getOpcode() == ARM::MQQQQPRStore
906 MIB.
add(
MI.getOperand(1));
908 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_0), Flags);
909 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_1), Flags);
910 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_2), Flags);
911 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_3), Flags);
912 if (
MI.getOpcode() == ARM::MQQQQPRStore ||
913 MI.getOpcode() == ARM::MQQQQPRLoad) {
914 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_4), Flags);
915 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_5), Flags);
916 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_6), Flags);
917 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_7), Flags);
920 if (NewOpc == ARM::VSTMDIA)
923 TransferImpOps(
MI, MIB, MIB);
925 MI.eraseFromParent();
975 unsigned Opcode =
MI.getOpcode();
979 bool DstIsDead =
MI.getOperand(0).isDead();
980 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
986 if (!STI->hasV6T2Ops() &&
987 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
989 assert(!STI->isTargetWindows() &&
"Windows on ARM requires ARMv7+");
991 assert (MO.
isImm() &&
"MOVi32imm w/ non-immediate source operand!");
993 unsigned SOImmValV1 = 0, SOImmValV2 = 0;
1009 SOImmValV1 = ~(-SOImmValV1);
1012 unsigned MIFlags =
MI.getFlags();
1013 LO16 = LO16.
addImm(SOImmValV1);
1014 HI16 = HI16.
addImm(SOImmValV2);
1023 TransferImpOps(
MI, LO16, HI16);
1024 MI.eraseFromParent();
1028 unsigned LO16Opc = 0;
1029 unsigned HI16Opc = 0;
1030 unsigned MIFlags =
MI.getFlags();
1031 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
1032 LO16Opc = ARM::t2MOVi16;
1033 HI16Opc = ARM::t2MOVTi16;
1035 LO16Opc = ARM::MOVi16;
1036 HI16Opc = ARM::MOVTi16;
1050 unsigned Lo16 =
Imm & 0xffff;
1051 unsigned Hi16 = (
Imm >> 16) & 0xffff;
1052 LO16 = LO16.
addImm(Lo16);
1053 HI16 = HI16.
addImm(Hi16);
1077 if (RequiresBundling)
1082 TransferImpOps(
MI, LO16, HI16);
1083 MI.eraseFromParent();
1093 const std::initializer_list<unsigned> &Regs,
1097 if (!Op.isReg() || !Op.isUse())
1103 std::set_difference(Regs.begin(), Regs.end(), OpRegs.
begin(), OpRegs.
end(),
1104 std::back_inserter(ClearRegs));
1107void ARMExpandPseudo::CMSEClearGPRegs(
1110 unsigned ClobberReg) {
1112 if (STI->hasV8_1MMainlineOps()) {
1116 for (
unsigned R : ClearRegs)
1123 for (
unsigned Reg : ClearRegs) {
1124 if (Reg == ClobberReg)
1132 .
addImm(STI->hasDSP() ? 0xc00 : 0x800)
1151 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1152 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1153 (Reg >= ARM::S0 && Reg <= ARM::S31))
1158 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) {
1159 int R = Reg - ARM::Q0;
1160 ClearRegs.
reset(R * 4, (R + 1) * 4);
1161 }
else if (Reg >= ARM::D0 && Reg <= ARM::D15) {
1162 int R = Reg - ARM::D0;
1163 ClearRegs.
reset(R * 2, (R + 1) * 2);
1164 }
else if (Reg >= ARM::S0 && Reg <= ARM::S31) {
1165 ClearRegs[Reg - ARM::S0] =
false;
1177 if (STI->hasV8_1MMainlineOps())
1178 return CMSEClearFPRegsV81(
MBB,
MBBI, ClearRegs);
1180 return CMSEClearFPRegsV8(
MBB,
MBBI, ClearRegs);
1189 if (!STI->hasFPRegs())
1199 if (STI->hasMinSize()) {
1200 ClearBB = DoneBB = &
MBB;
1221 if (Reg == ARM::NoRegister || Reg == ARM::LR)
1223 assert(
Reg.isPhysical() &&
"Unallocated register");
1247 for (
unsigned D = 0;
D < 8;
D++) {
1249 if (ClearRegs[
D * 2 + 0] && ClearRegs[
D * 2 + 1]) {
1250 unsigned Reg = ARM::D0 +
D;
1257 if (ClearRegs[
D * 2 + 0]) {
1258 unsigned Reg = ARM::S0 +
D * 2;
1264 if (ClearRegs[
D * 2 + 1]) {
1265 unsigned Reg = ARM::S0 +
D * 2 + 1;
1302 int Start = -1, End = -1;
1303 for (
int S = 0,
E = ClearRegs.
size(); S !=
E; ++S) {
1304 if (ClearRegs[S] && S == End + 1) {
1313 while (++Start <= End)
1324 while (++Start <= End)
1332void ARMExpandPseudo::CMSESaveClearFPRegs(
1335 if (STI->hasV8_1MMainlineOps())
1336 CMSESaveClearFPRegsV81(
MBB,
MBBI,
DL, LiveRegs);
1337 else if (STI->hasV8MMainlineOps())
1338 CMSESaveClearFPRegsV8(
MBB,
MBBI,
DL, LiveRegs, ScratchRegs);
1342void ARMExpandPseudo::CMSESaveClearFPRegsV8(
1348 unsigned SpareReg = ScratchRegs.
front();
1357 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1358 std::vector<unsigned> NonclearedFPRegs;
1360 if (
Op.isReg() &&
Op.isUse()) {
1363 ARM::DPR_VFP2RegClass.
contains(Reg));
1365 if (ARM::DPR_VFP2RegClass.
contains(Reg)) {
1366 if (ScratchRegs.
size() >= 2) {
1369 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
1378 NonclearedFPRegs.push_back(Reg);
1380 }
else if (ARM::SPRRegClass.
contains(Reg)) {
1381 if (ScratchRegs.
size() >= 1) {
1383 ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
1390 NonclearedFPRegs.push_back(Reg);
1396 bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1399 assert(STI->hasFPRegs() &&
"Subtarget needs fpregs");
1406 for (
auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
1407 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1412 for (
const auto &Regs : ClearedFPRegs) {
1413 unsigned Reg, SaveReg1, SaveReg2;
1414 std::tie(Reg, SaveReg1, SaveReg2) = Regs;
1415 if (ARM::DPR_VFP2RegClass.
contains(Reg))
1420 else if (ARM::SPRRegClass.
contains(Reg))
1426 for (
unsigned Reg : NonclearedFPRegs) {
1427 if (ARM::DPR_VFP2RegClass.
contains(Reg)) {
1428 if (STI->isLittle()) {
1431 .
addImm((Reg - ARM::D0) * 2)
1436 unsigned SReg0 =
TRI->getSubReg(Reg, ARM::ssub_0);
1439 .
addImm((Reg - ARM::D0) * 2)
1443 .
addImm((Reg - ARM::D0) * 2 + 1)
1446 }
else if (ARM::SPRRegClass.
contains(Reg)) {
1489 if (!DefFP && ClearRegs.
count() == ClearRegs.
size()) {
1500 for (
auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
1501 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
1510 for (
int Reg = ARM::S16;
Reg <= ARM::S31; ++
Reg)
1514 (void)CMSEClearFPRegsV81(
MBB,
MBBI, ClearRegs);
1525void ARMExpandPseudo::CMSERestoreFPRegs(
1528 if (STI->hasV8_1MMainlineOps())
1529 CMSERestoreFPRegsV81(
MBB,
MBBI,
DL, AvailableRegs);
1530 else if (STI->hasV8MMainlineOps())
1531 CMSERestoreFPRegsV8(
MBB,
MBBI,
DL, AvailableRegs);
1534void ARMExpandPseudo::CMSERestoreFPRegsV8(
1539 unsigned ScratchReg = ARM::NoRegister;
1540 if (STI->fixCMSE_CVE_2021_35465())
1544 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1545 std::vector<unsigned> NonclearedFPRegs;
1547 if (
Op.isReg() &&
Op.isDef()) {
1550 ARM::DPR_VFP2RegClass.
contains(Reg));
1552 if (ARM::DPR_VFP2RegClass.
contains(Reg)) {
1553 if (AvailableRegs.
size() >= 2) {
1556 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
1565 NonclearedFPRegs.push_back(Reg);
1567 }
else if (ARM::SPRRegClass.
contains(Reg)) {
1568 if (AvailableRegs.
size() >= 1) {
1570 ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
1577 NonclearedFPRegs.push_back(Reg);
1583 bool returnsFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1586 assert(STI->hasFPRegs() &&
"Subtarget needs fpregs");
1589 for (
unsigned Reg : NonclearedFPRegs) {
1590 if (ARM::DPR_VFP2RegClass.
contains(Reg))
1594 .
addImm((Reg - ARM::D0) * 2)
1596 else if (ARM::SPRRegClass.
contains(Reg))
1610 if (STI->fixCMSE_CVE_2021_35465()) {
1630 if (STI->hasFPRegs())
1643 for (
const auto &Regs : ClearedFPRegs) {
1644 unsigned Reg, SaveReg1, SaveReg2;
1645 std::tie(Reg, SaveReg1, SaveReg2) = Regs;
1646 if (ARM::DPR_VFP2RegClass.
contains(Reg))
1651 else if (ARM::SPRRegClass.
contains(Reg))
1669 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1670 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1671 (Reg >= ARM::S0 && Reg <= ARM::S31))
1677void ARMExpandPseudo::CMSERestoreFPRegsV81(
1681 if (STI->fixCMSE_CVE_2021_35465()) {
1710 for (
int Reg = ARM::S16;
Reg <= ARM::S31; ++
Reg)
1720 unsigned LdrexOp,
unsigned StrexOp,
1723 bool IsThumb = STI->isThumb();
1724 bool IsThumb1Only = STI->isThumb1Only();
1728 Register TempReg =
MI.getOperand(1).getReg();
1731 assert(!
MI.getOperand(2).isUndef() &&
"cannot handle undef");
1732 Register AddrReg =
MI.getOperand(2).getReg();
1733 Register DesiredReg =
MI.getOperand(3).getReg();
1737 assert(STI->hasV8MBaselineOps() &&
1738 "CMP_SWAP not expected to be custom expanded for Thumb1");
1739 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
1740 "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
1742 "DesiredReg used for UXT op must be tGPR");
1751 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
1752 MF->
insert(++StoreBB->getIterator(), DoneBB);
1771 if (LdrexOp == ARM::t2LDREX)
1775 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1780 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1785 LoadCmpBB->addSuccessor(DoneBB);
1786 LoadCmpBB->addSuccessor(StoreBB);
1795 if (StrexOp == ARM::t2STREX)
1800 IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri;
1809 StoreBB->addSuccessor(LoadCmpBB);
1810 StoreBB->addSuccessor(DoneBB);
1818 MI.eraseFromParent();
1826 StoreBB->clearLiveIns();
1828 LoadCmpBB->clearLiveIns();
1838 unsigned Flags,
bool IsThumb,
1841 Register RegLo =
TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1842 Register RegHi =
TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1853 bool IsThumb = STI->isThumb();
1854 assert(!STI->isThumb1Only() &&
"CMP_SWAP_64 unsupported under Thumb1!");
1858 Register TempReg =
MI.getOperand(1).getReg();
1861 assert(!
MI.getOperand(2).isUndef() &&
"cannot handle undef");
1862 Register AddrReg =
MI.getOperand(2).getReg();
1863 Register DesiredReg =
MI.getOperand(3).getReg();
1865 New.setIsKill(
false);
1869 Register DesiredLo =
TRI->getSubReg(DesiredReg, ARM::gsub_0);
1870 Register DesiredHi =
TRI->getSubReg(DesiredReg, ARM::gsub_1);
1878 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
1879 MF->
insert(++StoreBB->getIterator(), DoneBB);
1886 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1892 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1903 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1908 LoadCmpBB->addSuccessor(DoneBB);
1909 LoadCmpBB->addSuccessor(StoreBB);
1915 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
1921 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1930 StoreBB->addSuccessor(LoadCmpBB);
1931 StoreBB->addSuccessor(DoneBB);
1939 MI.eraseFromParent();
1947 StoreBB->clearLiveIns();
1949 LoadCmpBB->clearLiveIns();
1963 for (
int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
1975 for (
int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) {
1976 if (JumpReg == LoReg)
1985 for (
int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
1994 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) {
1995 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4;
2008 for (
int Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
2023 for (
int R = 0; R < 4; ++R) {
2031 for (
int R = 0; R < 4; ++R)
2038 for (
int Reg = ARM::R4; Reg < ARM::R12; ++Reg)
2047 unsigned Opcode =
MI.getOpcode();
2055 if (DstReg ==
MI.getOperand(3).getReg()) {
2057 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
2059 .
add(
MI.getOperand(0))
2060 .
add(
MI.getOperand(3))
2061 .
add(
MI.getOperand(2))
2062 .
add(
MI.getOperand(1))
2064 .
add(
MI.getOperand(5));
2065 }
else if (DstReg ==
MI.getOperand(2).getReg()) {
2067 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
2069 .
add(
MI.getOperand(0))
2070 .
add(
MI.getOperand(2))
2071 .
add(
MI.getOperand(3))
2072 .
add(
MI.getOperand(1))
2074 .
add(
MI.getOperand(5));
2077 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
2078 if (DstReg ==
MI.getOperand(1).getReg()) {
2080 .
add(
MI.getOperand(0))
2081 .
add(
MI.getOperand(1))
2082 .
add(
MI.getOperand(2))
2083 .
add(
MI.getOperand(3))
2085 .
add(
MI.getOperand(5));
2088 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
2093 .
add(
MI.getOperand(1))
2094 .
add(
MI.getOperand(1))
2096 .
add(
MI.getOperand(5));
2098 .
add(
MI.getOperand(0))
2102 .
add(
MI.getOperand(2))
2103 .
add(
MI.getOperand(3))
2105 .
add(
MI.getOperand(5));
2108 MI.eraseFromParent();
2112 case ARM::TCRETURNdi:
2113 case ARM::TCRETURNri: {
2115 if (
MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2117 if (
MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2120 "Can only insert epilog into returning blocks");
2121 unsigned RetOpcode =
MBBI->getOpcode();
2128 if (
MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2130 if (
MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2135 if (RetOpcode == ARM::TCRETURNdi) {
2141 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd
2157 }
else if (RetOpcode == ARM::TCRETURNri) {
2159 STI->isThumb() ? ARM::tTAILJMPr
2160 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
2166 auto NewMI = std::prev(
MBBI);
2167 for (
unsigned i = 2, e =
MBBI->getNumOperands(); i != e; ++i)
2168 NewMI->addOperand(
MBBI->getOperand(i));
2172 if (
MI.isCandidateForCallSiteEntry())
2173 MI.getMF()->moveCallSiteInfo(&
MI, &*NewMI);
2179 case ARM::tBXNS_RET: {
2182 if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress())
2187 if (STI->hasV8_1MMainlineOps()) {
2190 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP)
2195 if (AFI->shouldSignReturnAddress())
2201 return !Op.isReg() || Op.getReg() != ARM::R12;
2205 *
MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2206 CMSEClearGPRegs(AfterBB, AfterBB.
end(),
MBBI->getDebugLoc(), ClearRegs,
2211 TII->get(ARM::tBXNS))
2216 MI.eraseFromParent();
2219 case ARM::tBLXNS_CALL: {
2234 AFI->isThumb1OnlyFunction());
2238 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
2239 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9,
2240 ARM::R10, ARM::R11, ARM::R12},
2242 auto OriginalClearRegs = ClearRegs;
2246 unsigned ScratchReg = ClearRegs.
front();
2249 if (AFI->isThumb2Function()) {
2270 CMSESaveClearFPRegs(
MBB,
MBBI,
DL, LiveRegs,
2272 CMSEClearGPRegs(
MBB,
MBBI,
DL, ClearRegs, JumpReg);
2281 if (
MI.isCandidateForCallSiteEntry())
2284 CMSERestoreFPRegs(
MBB,
MBBI,
DL, OriginalClearRegs);
2288 MI.eraseFromParent();
2293 case ARM::VMOVDcc: {
2294 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
2296 MI.getOperand(1).getReg())
2297 .
add(
MI.getOperand(2))
2299 .
add(
MI.getOperand(4))
2302 MI.eraseFromParent();
2307 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
2309 MI.getOperand(1).getReg())
2310 .
add(
MI.getOperand(2))
2312 .
add(
MI.getOperand(4))
2316 MI.eraseFromParent();
2319 case ARM::MOVCCsi: {
2321 (
MI.getOperand(1).getReg()))
2322 .
add(
MI.getOperand(2))
2325 .
add(
MI.getOperand(5))
2329 MI.eraseFromParent();
2332 case ARM::MOVCCsr: {
2334 (
MI.getOperand(1).getReg()))
2335 .
add(
MI.getOperand(2))
2336 .
add(
MI.getOperand(3))
2339 .
add(
MI.getOperand(6))
2343 MI.eraseFromParent();
2346 case ARM::t2MOVCCi16:
2347 case ARM::MOVCCi16: {
2348 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
2350 MI.getOperand(1).getReg())
2353 .
add(
MI.getOperand(4))
2355 MI.eraseFromParent();
2360 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
2362 MI.getOperand(1).getReg())
2365 .
add(
MI.getOperand(4))
2369 MI.eraseFromParent();
2374 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
2376 MI.getOperand(1).getReg())
2379 .
add(
MI.getOperand(4))
2383 MI.eraseFromParent();
2386 case ARM::t2MOVCClsl:
2387 case ARM::t2MOVCClsr:
2388 case ARM::t2MOVCCasr:
2389 case ARM::t2MOVCCror: {
2392 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri;
break;
2393 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri;
break;
2394 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri;
break;
2395 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri;
break;
2399 MI.getOperand(1).getReg())
2400 .
add(
MI.getOperand(2))
2403 .
add(
MI.getOperand(5))
2406 MI.eraseFromParent();
2409 case ARM::Int_eh_sjlj_dispatchsetup: {
2418 int32_t NumBytes = AFI->getFramePtrSpillOffset();
2421 "base pointer without frame pointer?");
2423 if (AFI->isThumb2Function()) {
2426 }
else if (AFI->isThumbFunction()) {
2435 if (RI.hasStackRealignment(MF)) {
2438 assert (!AFI->isThumb1OnlyFunction());
2441 "The BIC instruction cannot encode "
2442 "immediates larger than 256 with all lower "
2444 unsigned bicOpc = AFI->isThumbFunction() ?
2445 ARM::t2BICri : ARM::BICri;
2453 MI.eraseFromParent();
2457 case ARM::MOVsrl_flag:
2458 case ARM::MOVsra_flag: {
2461 MI.getOperand(0).getReg())
2462 .
add(
MI.getOperand(1))
2467 MI.eraseFromParent();
2474 MI.getOperand(0).getReg())
2475 .
add(
MI.getOperand(1))
2479 TransferImpOps(
MI, MIB, MIB);
2480 MI.eraseFromParent();
2485 const bool Thumb = Opcode == ARM::tTPsoft;
2489 if (STI->genLongCalls()) {
2491 unsigned PCLabelID = AFI->createPICLabelUId();
2494 "__aeabi_read_tp", PCLabelID, 0);
2498 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
2512 TII->get(Thumb ? ARM::tBL : ARM::BL));
2519 TransferImpOps(
MI, MIB, MIB);
2521 if (
MI.isCandidateForCallSiteEntry())
2523 MI.eraseFromParent();
2526 case ARM::tLDRpci_pic:
2527 case ARM::t2LDRpci_pic: {
2528 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
2529 ? ARM::tLDRpci : ARM::t2LDRpci;
2531 bool DstIsDead =
MI.getOperand(0).isDead();
2534 .
add(
MI.getOperand(1))
2541 .
add(
MI.getOperand(2));
2542 TransferImpOps(
MI, MIB1, MIB2);
2543 MI.eraseFromParent();
2547 case ARM::LDRLIT_ga_abs:
2548 case ARM::LDRLIT_ga_pcrel:
2549 case ARM::LDRLIT_ga_pcrel_ldr:
2550 case ARM::tLDRLIT_ga_abs:
2551 case ARM::t2LDRLIT_ga_pcrel:
2552 case ARM::tLDRLIT_ga_pcrel: {
2554 bool DstIsDead =
MI.getOperand(0).isDead();
2558 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
2559 Opcode != ARM::tLDRLIT_ga_abs &&
2560 Opcode != ARM::t2LDRLIT_ga_pcrel;
2562 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
2563 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
2564 if (Opcode == ARM::t2LDRLIT_ga_pcrel)
2565 LDRLITOpc = ARM::t2LDRpci;
2566 unsigned PICAddOpc =
2568 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2573 unsigned ARMPCLabelIndex = 0;
2577 unsigned PCAdj = IsARM ? 8 : 4;
2581 ARMPCLabelIndex = AFI->createPICLabelUId();
2600 .
addImm(ARMPCLabelIndex);
2606 MI.eraseFromParent();
2609 case ARM::MOV_ga_pcrel:
2610 case ARM::MOV_ga_pcrel_ldr:
2611 case ARM::t2MOV_ga_pcrel: {
2613 unsigned LabelId = AFI->createPICLabelUId();
2615 bool DstIsDead =
MI.getOperand(0).isDead();
2619 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
2620 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
2621 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
2624 unsigned PICAddOpc = isARM
2625 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2628 TII->get(LO16Opc), DstReg)
2638 TII->get(PICAddOpc))
2643 if (Opcode == ARM::MOV_ga_pcrel_ldr)
2646 TransferImpOps(
MI, MIB1, MIB3);
2647 MI.eraseFromParent();
2651 case ARM::MOVi32imm:
2652 case ARM::MOVCCi32imm:
2653 case ARM::t2MOVi32imm:
2654 case ARM::t2MOVCCi32imm:
2658 case ARM::SUBS_PC_LR: {
2662 .
add(
MI.getOperand(0))
2663 .
add(
MI.getOperand(1))
2664 .
add(
MI.getOperand(2))
2666 TransferImpOps(
MI, MIB, MIB);
2667 MI.eraseFromParent();
2670 case ARM::VLDMQIA: {
2671 unsigned NewOpc = ARM::VLDMDIA;
2677 bool DstIsDead =
MI.getOperand(OpIdx).isDead();
2678 Register DstReg =
MI.getOperand(OpIdx++).getReg();
2681 MIB.
add(
MI.getOperand(OpIdx++));
2684 MIB.
add(
MI.getOperand(OpIdx++));
2685 MIB.
add(
MI.getOperand(OpIdx++));
2688 Register D0 =
TRI->getSubReg(DstReg, ARM::dsub_0);
2689 Register D1 =
TRI->getSubReg(DstReg, ARM::dsub_1);
2695 TransferImpOps(
MI, MIB, MIB);
2697 MI.eraseFromParent();
2701 case ARM::VSTMQIA: {
2702 unsigned NewOpc = ARM::VSTMDIA;
2708 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
2709 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
2716 MIB.
add(
MI.getOperand(OpIdx++));
2717 MIB.
add(
MI.getOperand(OpIdx++));
2720 Register D0 =
TRI->getSubReg(SrcReg, ARM::dsub_0);
2721 Register D1 =
TRI->getSubReg(SrcReg, ARM::dsub_1);
2728 TransferImpOps(
MI, MIB, MIB);
2730 MI.eraseFromParent();
2734 case ARM::VLD2q8Pseudo:
2735 case ARM::VLD2q16Pseudo:
2736 case ARM::VLD2q32Pseudo:
2737 case ARM::VLD2q8PseudoWB_fixed:
2738 case ARM::VLD2q16PseudoWB_fixed:
2739 case ARM::VLD2q32PseudoWB_fixed:
2740 case ARM::VLD2q8PseudoWB_register:
2741 case ARM::VLD2q16PseudoWB_register:
2742 case ARM::VLD2q32PseudoWB_register:
2743 case ARM::VLD3d8Pseudo:
2744 case ARM::VLD3d16Pseudo:
2745 case ARM::VLD3d32Pseudo:
2746 case ARM::VLD1d8TPseudo:
2747 case ARM::VLD1d8TPseudoWB_fixed:
2748 case ARM::VLD1d8TPseudoWB_register:
2749 case ARM::VLD1d16TPseudo:
2750 case ARM::VLD1d16TPseudoWB_fixed:
2751 case ARM::VLD1d16TPseudoWB_register:
2752 case ARM::VLD1d32TPseudo:
2753 case ARM::VLD1d32TPseudoWB_fixed:
2754 case ARM::VLD1d32TPseudoWB_register:
2755 case ARM::VLD1d64TPseudo:
2756 case ARM::VLD1d64TPseudoWB_fixed:
2757 case ARM::VLD1d64TPseudoWB_register:
2758 case ARM::VLD3d8Pseudo_UPD:
2759 case ARM::VLD3d16Pseudo_UPD:
2760 case ARM::VLD3d32Pseudo_UPD:
2761 case ARM::VLD3q8Pseudo_UPD:
2762 case ARM::VLD3q16Pseudo_UPD:
2763 case ARM::VLD3q32Pseudo_UPD:
2764 case ARM::VLD3q8oddPseudo:
2765 case ARM::VLD3q16oddPseudo:
2766 case ARM::VLD3q32oddPseudo:
2767 case ARM::VLD3q8oddPseudo_UPD:
2768 case ARM::VLD3q16oddPseudo_UPD:
2769 case ARM::VLD3q32oddPseudo_UPD:
2770 case ARM::VLD4d8Pseudo:
2771 case ARM::VLD4d16Pseudo:
2772 case ARM::VLD4d32Pseudo:
2773 case ARM::VLD1d8QPseudo:
2774 case ARM::VLD1d8QPseudoWB_fixed:
2775 case ARM::VLD1d8QPseudoWB_register:
2776 case ARM::VLD1d16QPseudo:
2777 case ARM::VLD1d16QPseudoWB_fixed:
2778 case ARM::VLD1d16QPseudoWB_register:
2779 case ARM::VLD1d32QPseudo:
2780 case ARM::VLD1d32QPseudoWB_fixed:
2781 case ARM::VLD1d32QPseudoWB_register:
2782 case ARM::VLD1d64QPseudo:
2783 case ARM::VLD1d64QPseudoWB_fixed:
2784 case ARM::VLD1d64QPseudoWB_register:
2785 case ARM::VLD1q8HighQPseudo:
2786 case ARM::VLD1q8HighQPseudo_UPD:
2787 case ARM::VLD1q8LowQPseudo_UPD:
2788 case ARM::VLD1q8HighTPseudo:
2789 case ARM::VLD1q8HighTPseudo_UPD:
2790 case ARM::VLD1q8LowTPseudo_UPD:
2791 case ARM::VLD1q16HighQPseudo:
2792 case ARM::VLD1q16HighQPseudo_UPD:
2793 case ARM::VLD1q16LowQPseudo_UPD:
2794 case ARM::VLD1q16HighTPseudo:
2795 case ARM::VLD1q16HighTPseudo_UPD:
2796 case ARM::VLD1q16LowTPseudo_UPD:
2797 case ARM::VLD1q32HighQPseudo:
2798 case ARM::VLD1q32HighQPseudo_UPD:
2799 case ARM::VLD1q32LowQPseudo_UPD:
2800 case ARM::VLD1q32HighTPseudo:
2801 case ARM::VLD1q32HighTPseudo_UPD:
2802 case ARM::VLD1q32LowTPseudo_UPD:
2803 case ARM::VLD1q64HighQPseudo:
2804 case ARM::VLD1q64HighQPseudo_UPD:
2805 case ARM::VLD1q64LowQPseudo_UPD:
2806 case ARM::VLD1q64HighTPseudo:
2807 case ARM::VLD1q64HighTPseudo_UPD:
2808 case ARM::VLD1q64LowTPseudo_UPD:
2809 case ARM::VLD4d8Pseudo_UPD:
2810 case ARM::VLD4d16Pseudo_UPD:
2811 case ARM::VLD4d32Pseudo_UPD:
2812 case ARM::VLD4q8Pseudo_UPD:
2813 case ARM::VLD4q16Pseudo_UPD:
2814 case ARM::VLD4q32Pseudo_UPD:
2815 case ARM::VLD4q8oddPseudo:
2816 case ARM::VLD4q16oddPseudo:
2817 case ARM::VLD4q32oddPseudo:
2818 case ARM::VLD4q8oddPseudo_UPD:
2819 case ARM::VLD4q16oddPseudo_UPD:
2820 case ARM::VLD4q32oddPseudo_UPD:
2821 case ARM::VLD3DUPd8Pseudo:
2822 case ARM::VLD3DUPd16Pseudo:
2823 case ARM::VLD3DUPd32Pseudo:
2824 case ARM::VLD3DUPd8Pseudo_UPD:
2825 case ARM::VLD3DUPd16Pseudo_UPD:
2826 case ARM::VLD3DUPd32Pseudo_UPD:
2827 case ARM::VLD4DUPd8Pseudo:
2828 case ARM::VLD4DUPd16Pseudo:
2829 case ARM::VLD4DUPd32Pseudo:
2830 case ARM::VLD4DUPd8Pseudo_UPD:
2831 case ARM::VLD4DUPd16Pseudo_UPD:
2832 case ARM::VLD4DUPd32Pseudo_UPD:
2833 case ARM::VLD2DUPq8EvenPseudo:
2834 case ARM::VLD2DUPq8OddPseudo:
2835 case ARM::VLD2DUPq16EvenPseudo:
2836 case ARM::VLD2DUPq16OddPseudo:
2837 case ARM::VLD2DUPq32EvenPseudo:
2838 case ARM::VLD2DUPq32OddPseudo:
2839 case ARM::VLD2DUPq8OddPseudoWB_fixed:
2840 case ARM::VLD2DUPq8OddPseudoWB_register:
2841 case ARM::VLD2DUPq16OddPseudoWB_fixed:
2842 case ARM::VLD2DUPq16OddPseudoWB_register:
2843 case ARM::VLD2DUPq32OddPseudoWB_fixed:
2844 case ARM::VLD2DUPq32OddPseudoWB_register:
2845 case ARM::VLD3DUPq8EvenPseudo:
2846 case ARM::VLD3DUPq8OddPseudo:
2847 case ARM::VLD3DUPq16EvenPseudo:
2848 case ARM::VLD3DUPq16OddPseudo:
2849 case ARM::VLD3DUPq32EvenPseudo:
2850 case ARM::VLD3DUPq32OddPseudo:
2851 case ARM::VLD3DUPq8OddPseudo_UPD:
2852 case ARM::VLD3DUPq16OddPseudo_UPD:
2853 case ARM::VLD3DUPq32OddPseudo_UPD:
2854 case ARM::VLD4DUPq8EvenPseudo:
2855 case ARM::VLD4DUPq8OddPseudo:
2856 case ARM::VLD4DUPq16EvenPseudo:
2857 case ARM::VLD4DUPq16OddPseudo:
2858 case ARM::VLD4DUPq32EvenPseudo:
2859 case ARM::VLD4DUPq32OddPseudo:
2860 case ARM::VLD4DUPq8OddPseudo_UPD:
2861 case ARM::VLD4DUPq16OddPseudo_UPD:
2862 case ARM::VLD4DUPq32OddPseudo_UPD:
2866 case ARM::VST2q8Pseudo:
2867 case ARM::VST2q16Pseudo:
2868 case ARM::VST2q32Pseudo:
2869 case ARM::VST2q8PseudoWB_fixed:
2870 case ARM::VST2q16PseudoWB_fixed:
2871 case ARM::VST2q32PseudoWB_fixed:
2872 case ARM::VST2q8PseudoWB_register:
2873 case ARM::VST2q16PseudoWB_register:
2874 case ARM::VST2q32PseudoWB_register:
2875 case ARM::VST3d8Pseudo:
2876 case ARM::VST3d16Pseudo:
2877 case ARM::VST3d32Pseudo:
2878 case ARM::VST1d8TPseudo:
2879 case ARM::VST1d8TPseudoWB_fixed:
2880 case ARM::VST1d8TPseudoWB_register:
2881 case ARM::VST1d16TPseudo:
2882 case ARM::VST1d16TPseudoWB_fixed:
2883 case ARM::VST1d16TPseudoWB_register:
2884 case ARM::VST1d32TPseudo:
2885 case ARM::VST1d32TPseudoWB_fixed:
2886 case ARM::VST1d32TPseudoWB_register:
2887 case ARM::VST1d64TPseudo:
2888 case ARM::VST1d64TPseudoWB_fixed:
2889 case ARM::VST1d64TPseudoWB_register:
2890 case ARM::VST3d8Pseudo_UPD:
2891 case ARM::VST3d16Pseudo_UPD:
2892 case ARM::VST3d32Pseudo_UPD:
2893 case ARM::VST3q8Pseudo_UPD:
2894 case ARM::VST3q16Pseudo_UPD:
2895 case ARM::VST3q32Pseudo_UPD:
2896 case ARM::VST3q8oddPseudo:
2897 case ARM::VST3q16oddPseudo:
2898 case ARM::VST3q32oddPseudo:
2899 case ARM::VST3q8oddPseudo_UPD:
2900 case ARM::VST3q16oddPseudo_UPD:
2901 case ARM::VST3q32oddPseudo_UPD:
2902 case ARM::VST4d8Pseudo:
2903 case ARM::VST4d16Pseudo:
2904 case ARM::VST4d32Pseudo:
2905 case ARM::VST1d8QPseudo:
2906 case ARM::VST1d8QPseudoWB_fixed:
2907 case ARM::VST1d8QPseudoWB_register:
2908 case ARM::VST1d16QPseudo:
2909 case ARM::VST1d16QPseudoWB_fixed:
2910 case ARM::VST1d16QPseudoWB_register:
2911 case ARM::VST1d32QPseudo:
2912 case ARM::VST1d32QPseudoWB_fixed:
2913 case ARM::VST1d32QPseudoWB_register:
2914 case ARM::VST1d64QPseudo:
2915 case ARM::VST1d64QPseudoWB_fixed:
2916 case ARM::VST1d64QPseudoWB_register:
2917 case ARM::VST4d8Pseudo_UPD:
2918 case ARM::VST4d16Pseudo_UPD:
2919 case ARM::VST4d32Pseudo_UPD:
2920 case ARM::VST1q8HighQPseudo:
2921 case ARM::VST1q8LowQPseudo_UPD:
2922 case ARM::VST1q8HighTPseudo:
2923 case ARM::VST1q8LowTPseudo_UPD:
2924 case ARM::VST1q16HighQPseudo:
2925 case ARM::VST1q16LowQPseudo_UPD:
2926 case ARM::VST1q16HighTPseudo:
2927 case ARM::VST1q16LowTPseudo_UPD:
2928 case ARM::VST1q32HighQPseudo:
2929 case ARM::VST1q32LowQPseudo_UPD:
2930 case ARM::VST1q32HighTPseudo:
2931 case ARM::VST1q32LowTPseudo_UPD:
2932 case ARM::VST1q64HighQPseudo:
2933 case ARM::VST1q64LowQPseudo_UPD:
2934 case ARM::VST1q64HighTPseudo:
2935 case ARM::VST1q64LowTPseudo_UPD:
2936 case ARM::VST1q8HighTPseudo_UPD:
2937 case ARM::VST1q16HighTPseudo_UPD:
2938 case ARM::VST1q32HighTPseudo_UPD:
2939 case ARM::VST1q64HighTPseudo_UPD:
2940 case ARM::VST1q8HighQPseudo_UPD:
2941 case ARM::VST1q16HighQPseudo_UPD:
2942 case ARM::VST1q32HighQPseudo_UPD:
2943 case ARM::VST1q64HighQPseudo_UPD:
2944 case ARM::VST4q8Pseudo_UPD:
2945 case ARM::VST4q16Pseudo_UPD:
2946 case ARM::VST4q32Pseudo_UPD:
2947 case ARM::VST4q8oddPseudo:
2948 case ARM::VST4q16oddPseudo:
2949 case ARM::VST4q32oddPseudo:
2950 case ARM::VST4q8oddPseudo_UPD:
2951 case ARM::VST4q16oddPseudo_UPD:
2952 case ARM::VST4q32oddPseudo_UPD:
2956 case ARM::VLD1LNq8Pseudo:
2957 case ARM::VLD1LNq16Pseudo:
2958 case ARM::VLD1LNq32Pseudo:
2959 case ARM::VLD1LNq8Pseudo_UPD:
2960 case ARM::VLD1LNq16Pseudo_UPD:
2961 case ARM::VLD1LNq32Pseudo_UPD:
2962 case ARM::VLD2LNd8Pseudo:
2963 case ARM::VLD2LNd16Pseudo:
2964 case ARM::VLD2LNd32Pseudo:
2965 case ARM::VLD2LNq16Pseudo:
2966 case ARM::VLD2LNq32Pseudo:
2967 case ARM::VLD2LNd8Pseudo_UPD:
2968 case ARM::VLD2LNd16Pseudo_UPD:
2969 case ARM::VLD2LNd32Pseudo_UPD:
2970 case ARM::VLD2LNq16Pseudo_UPD:
2971 case ARM::VLD2LNq32Pseudo_UPD:
2972 case ARM::VLD3LNd8Pseudo:
2973 case ARM::VLD3LNd16Pseudo:
2974 case ARM::VLD3LNd32Pseudo:
2975 case ARM::VLD3LNq16Pseudo:
2976 case ARM::VLD3LNq32Pseudo:
2977 case ARM::VLD3LNd8Pseudo_UPD:
2978 case ARM::VLD3LNd16Pseudo_UPD:
2979 case ARM::VLD3LNd32Pseudo_UPD:
2980 case ARM::VLD3LNq16Pseudo_UPD:
2981 case ARM::VLD3LNq32Pseudo_UPD:
2982 case ARM::VLD4LNd8Pseudo:
2983 case ARM::VLD4LNd16Pseudo:
2984 case ARM::VLD4LNd32Pseudo:
2985 case ARM::VLD4LNq16Pseudo:
2986 case ARM::VLD4LNq32Pseudo:
2987 case ARM::VLD4LNd8Pseudo_UPD:
2988 case ARM::VLD4LNd16Pseudo_UPD:
2989 case ARM::VLD4LNd32Pseudo_UPD:
2990 case ARM::VLD4LNq16Pseudo_UPD:
2991 case ARM::VLD4LNq32Pseudo_UPD:
2992 case ARM::VST1LNq8Pseudo:
2993 case ARM::VST1LNq16Pseudo:
2994 case ARM::VST1LNq32Pseudo:
2995 case ARM::VST1LNq8Pseudo_UPD:
2996 case ARM::VST1LNq16Pseudo_UPD:
2997 case ARM::VST1LNq32Pseudo_UPD:
2998 case ARM::VST2LNd8Pseudo:
2999 case ARM::VST2LNd16Pseudo:
3000 case ARM::VST2LNd32Pseudo:
3001 case ARM::VST2LNq16Pseudo:
3002 case ARM::VST2LNq32Pseudo:
3003 case ARM::VST2LNd8Pseudo_UPD:
3004 case ARM::VST2LNd16Pseudo_UPD:
3005 case ARM::VST2LNd32Pseudo_UPD:
3006 case ARM::VST2LNq16Pseudo_UPD:
3007 case ARM::VST2LNq32Pseudo_UPD:
3008 case ARM::VST3LNd8Pseudo:
3009 case ARM::VST3LNd16Pseudo:
3010 case ARM::VST3LNd32Pseudo:
3011 case ARM::VST3LNq16Pseudo:
3012 case ARM::VST3LNq32Pseudo:
3013 case ARM::VST3LNd8Pseudo_UPD:
3014 case ARM::VST3LNd16Pseudo_UPD:
3015 case ARM::VST3LNd32Pseudo_UPD:
3016 case ARM::VST3LNq16Pseudo_UPD:
3017 case ARM::VST3LNq32Pseudo_UPD:
3018 case ARM::VST4LNd8Pseudo:
3019 case ARM::VST4LNd16Pseudo:
3020 case ARM::VST4LNd32Pseudo:
3021 case ARM::VST4LNq16Pseudo:
3022 case ARM::VST4LNq32Pseudo:
3023 case ARM::VST4LNd8Pseudo_UPD:
3024 case ARM::VST4LNd16Pseudo_UPD:
3025 case ARM::VST4LNd32Pseudo_UPD:
3026 case ARM::VST4LNq16Pseudo_UPD:
3027 case ARM::VST4LNq32Pseudo_UPD:
3031 case ARM::VTBL3Pseudo: ExpandVTBL(
MBBI, ARM::VTBL3,
false);
return true;
3032 case ARM::VTBL4Pseudo: ExpandVTBL(
MBBI, ARM::VTBL4,
false);
return true;
3033 case ARM::VTBX3Pseudo: ExpandVTBL(
MBBI, ARM::VTBX3,
true);
return true;
3034 case ARM::VTBX4Pseudo: ExpandVTBL(
MBBI, ARM::VTBX4,
true);
return true;
3036 case ARM::MQQPRLoad:
3037 case ARM::MQQPRStore:
3038 case ARM::MQQQQPRLoad:
3039 case ARM::MQQQQPRStore:
3040 ExpandMQQPRLoadStore(
MBBI);
3043 case ARM::tCMP_SWAP_8:
3045 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
3047 case ARM::tCMP_SWAP_16:
3049 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
3051 case ARM::tCMP_SWAP_32:
3053 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI);
3055 case ARM::CMP_SWAP_8:
3057 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB,
3059 case ARM::CMP_SWAP_16:
3061 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH,
3063 case ARM::CMP_SWAP_32:
3065 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
3067 case ARM::CMP_SWAP_64:
3068 return ExpandCMP_SWAP_64(
MBB,
MBBI, NextMBBI);
3070 case ARM::tBL_PUSHLR:
3071 case ARM::BL_PUSHLR: {
3072 const bool Thumb = Opcode == ARM::tBL_PUSHLR;
3074 assert(Reg == ARM::LR &&
"expect LR register!");
3098 MI.eraseFromParent();
3101 case ARM::t2CALL_BTI: {
3106 for (
unsigned i = 0; i <
MI.getNumOperands(); ++i)
3107 MIB.
add(
MI.getOperand(i));
3108 if (
MI.isCandidateForCallSiteEntry())
3111 Bundler.append(MIB);
3112 Bundler.append(
BuildMI(MF,
MI.getDebugLoc(),
TII->get(ARM::t2BTI)));
3114 MI.eraseFromParent();
3118 case ARM::STOREDUAL: {
3119 Register PairReg =
MI.getOperand(0).getReg();
3123 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD))
3124 .
addReg(
TRI->getSubReg(PairReg, ARM::gsub_0),
3126 .
addReg(
TRI->getSubReg(PairReg, ARM::gsub_1),
3132 MI.eraseFromParent();
3153 TII = STI->getInstrInfo();
3154 TRI = STI->getRegisterInfo();
3157 LLVM_DEBUG(
dbgs() <<
"********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
3158 <<
"********** Function: " << MF.
getName() <<
'\n');
3164 MF.verify(
this,
"After expanding ARM pseudo instructions.");
3166 LLVM_DEBUG(
dbgs() <<
"***************************************************\n");
3173 return new ARMExpandPseudo();
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool determineFPRegsToClear(const MachineInstr &MI, BitVector &ClearRegs)
static void CMSEPopCalleeSaves(const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int JumpReg, bool Thumb1Only)
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3)
GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified regis...
static MachineOperand makeImplicit(const MachineOperand &MO)
static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI)
ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register),...
static cl::opt< bool > VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int JumpReg, const LivePhysRegs &LiveRegs, bool Thumb1Only)
static bool definesOrUsesFPReg(const MachineInstr &MI)
static void determineGPRegsToClear(const MachineInstr &MI, const std::initializer_list< unsigned > &Regs, SmallVectorImpl< unsigned > &ClearRegs)
static bool IsAnAddressOperand(const MachineOperand &MO)
#define ARM_EXPAND_PSEUDO_NAME
static const int CMSE_FP_SAVE_SIZE
static const NEONLdStTableEntry * LookupNEONLdSt(unsigned Opcode)
LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instructi...
static const NEONLdStTableEntry NEONLdStTable[]
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static const unsigned FramePtr
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
bool hasBasePointer(const MachineFunction &MF) const
Register getFrameRegister(const MachineFunction &MF) const override
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
static ARMConstantPoolSymbol * Create(LLVMContext &C, StringRef s, unsigned ID, unsigned char PCAdj)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
size_type count() const
count - Returns the number of bits which are set.
size_type size() const
size - Returns the number of bits in this bitvector.
FunctionPass class - This class is used to implement most global optimizations.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
bool usesWindowsCFI() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Helper class for constructing bundles of MachineInstrs.
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
reverse_iterator rbegin()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Abstract base class for all machine specific constantpool value subclasses.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
void setImplicit(bool Val=true)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_Predicate
Generic predicate for ISel.
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
@ MO_CImmediate
Immediate >64bit operand.
@ MO_BlockAddress
Address of a basic block.
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_IntrinsicID
Intrinsic ID for ISel.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_Metadata
Metadata reference (for debug info)
@ MO_FPImmediate
Floating-point immediate operand.
@ MO_RegisterLiveOut
Mask of live-out registers.
int64_t getOffset() const
Return the offset from the symbol in this operand.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
TargetInstrInfo - Interface to description of machine instruction set.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
@ MO_GOT
MO_GOT - On a symbol operand, this represents a GOT relative relocation.
unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
bool isSOImmTwoPartVal(unsigned V)
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVa...
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
bool operator<(int64_t V1, const APSInt &V2)
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned getDeadRegState(bool B)
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
unsigned getUndefRegState(bool B)
unsigned getDefRegState(bool B)
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
unsigned getKillRegState(bool B)
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
unsigned getRenamableRegState(bool B)
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
unsigned gettBLXrOpcode(const MachineFunction &MF)
unsigned getBLXOpcode(const MachineFunction &MF)
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.