LLVM  16.0.0git
SystemZFrameLowering.cpp
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1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZFrameLowering.h"
10 #include "SystemZCallingConv.h"
11 #include "SystemZInstrBuilder.h"
12 #include "SystemZInstrInfo.h"
14 #include "SystemZRegisterInfo.h"
15 #include "SystemZSubtarget.h"
20 #include "llvm/IR/Function.h"
22 
23 using namespace llvm;
24 
25 namespace {
26 // The ABI-defined register save slots, relative to the CFA (i.e.
27 // incoming stack pointer + SystemZMC::ELFCallFrameSize).
28 static const TargetFrameLowering::SpillSlot ELFSpillOffsetTable[] = {
29  { SystemZ::R2D, 0x10 },
30  { SystemZ::R3D, 0x18 },
31  { SystemZ::R4D, 0x20 },
32  { SystemZ::R5D, 0x28 },
33  { SystemZ::R6D, 0x30 },
34  { SystemZ::R7D, 0x38 },
35  { SystemZ::R8D, 0x40 },
36  { SystemZ::R9D, 0x48 },
37  { SystemZ::R10D, 0x50 },
38  { SystemZ::R11D, 0x58 },
39  { SystemZ::R12D, 0x60 },
40  { SystemZ::R13D, 0x68 },
41  { SystemZ::R14D, 0x70 },
42  { SystemZ::R15D, 0x78 },
43  { SystemZ::F0D, 0x80 },
44  { SystemZ::F2D, 0x88 },
45  { SystemZ::F4D, 0x90 },
46  { SystemZ::F6D, 0x98 }
47 };
48 
49 static const TargetFrameLowering::SpillSlot XPLINKSpillOffsetTable[] = {
50  {SystemZ::R4D, 0x00}, {SystemZ::R5D, 0x08}, {SystemZ::R6D, 0x10},
51  {SystemZ::R7D, 0x18}, {SystemZ::R8D, 0x20}, {SystemZ::R9D, 0x28},
52  {SystemZ::R10D, 0x30}, {SystemZ::R11D, 0x38}, {SystemZ::R12D, 0x40},
53  {SystemZ::R13D, 0x48}, {SystemZ::R14D, 0x50}, {SystemZ::R15D, 0x58}};
54 } // end anonymous namespace
55 
57  int LAO, Align TransAl,
58  bool StackReal)
59  : TargetFrameLowering(D, StackAl, LAO, TransAl, StackReal) {}
60 
61 std::unique_ptr<SystemZFrameLowering>
63  if (STI.isTargetXPLINK64())
64  return std::make_unique<SystemZXPLINKFrameLowering>();
65  return std::make_unique<SystemZELFFrameLowering>();
66 }
67 
71  switch (MI->getOpcode()) {
72  case SystemZ::ADJCALLSTACKDOWN:
73  case SystemZ::ADJCALLSTACKUP:
75  "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
76  return MBB.erase(MI);
77  break;
78 
79  default:
80  llvm_unreachable("Unexpected call frame instruction");
81  }
82 }
83 
84 namespace {
85 struct SZFrameSortingObj {
86  bool IsValid = false; // True if we care about this Object.
87  uint32_t ObjectIndex = 0; // Index of Object into MFI list.
88  uint64_t ObjectSize = 0; // Size of Object in bytes.
89  uint32_t D12Count = 0; // 12-bit displacement only.
90  uint32_t DPairCount = 0; // 12 or 20 bit displacement.
91 };
92 typedef std::vector<SZFrameSortingObj> SZFrameObjVec;
93 } // namespace
94 
95 // TODO: Move to base class.
97  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
98  const MachineFrameInfo &MFI = MF.getFrameInfo();
99  auto *TII = MF.getSubtarget<SystemZSubtarget>().getInstrInfo();
100 
101  // Make a vector of sorting objects to track all MFI objects and mark those
102  // to be sorted as valid.
103  if (ObjectsToAllocate.size() <= 1)
104  return;
105  SZFrameObjVec SortingObjects(MFI.getObjectIndexEnd());
106  for (auto &Obj : ObjectsToAllocate) {
107  SortingObjects[Obj].IsValid = true;
108  SortingObjects[Obj].ObjectIndex = Obj;
109  SortingObjects[Obj].ObjectSize = MFI.getObjectSize(Obj);
110  }
111 
112  // Examine uses for each object and record short (12-bit) and "pair"
113  // displacement types.
114  for (auto &MBB : MF)
115  for (auto &MI : MBB) {
116  if (MI.isDebugInstr())
117  continue;
118  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
119  const MachineOperand &MO = MI.getOperand(I);
120  if (!MO.isFI())
121  continue;
122  int Index = MO.getIndex();
123  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
124  SortingObjects[Index].IsValid) {
125  if (TII->hasDisplacementPairInsn(MI.getOpcode()))
126  SortingObjects[Index].DPairCount++;
127  else if (!(MI.getDesc().TSFlags & SystemZII::Has20BitOffset))
128  SortingObjects[Index].D12Count++;
129  }
130  }
131  }
132 
133  // Sort all objects for short/paired displacements, which should be
134  // sufficient as it seems like all frame objects typically are within the
135  // long displacement range. Sorting works by computing the "density" as
136  // Count / ObjectSize. The comparisons of two such fractions are refactored
137  // by multiplying both sides with A.ObjectSize * B.ObjectSize, in order to
138  // eliminate the (fp) divisions. A higher density object needs to go after
139  // in the list in order for it to end up lower on the stack.
140  auto CmpD12 = [](const SZFrameSortingObj &A, const SZFrameSortingObj &B) {
141  // Put all invalid and variable sized objects at the end.
142  if (!A.IsValid || !B.IsValid)
143  return A.IsValid;
144  if (!A.ObjectSize || !B.ObjectSize)
145  return A.ObjectSize > 0;
146  uint64_t ADensityCmp = A.D12Count * B.ObjectSize;
147  uint64_t BDensityCmp = B.D12Count * A.ObjectSize;
148  if (ADensityCmp != BDensityCmp)
149  return ADensityCmp < BDensityCmp;
150  return A.DPairCount * B.ObjectSize < B.DPairCount * A.ObjectSize;
151  };
152  std::stable_sort(SortingObjects.begin(), SortingObjects.end(), CmpD12);
153 
154  // Now modify the original list to represent the final order that
155  // we want.
156  unsigned Idx = 0;
157  for (auto &Obj : SortingObjects) {
158  // All invalid items are sorted at the end, so it's safe to stop.
159  if (!Obj.IsValid)
160  break;
161  ObjectsToAllocate[Idx++] = Obj.ObjectIndex;
162  }
163 }
164 
166  const MachineFunction &MF) const {
167  // The ELF ABI requires us to allocate 160 bytes of stack space for the
168  // callee, with any outgoing stack arguments being placed above that. It
169  // seems better to make that area a permanent feature of the frame even if
170  // we're using a frame pointer. Similarly, 64-bit XPLINK requires 96 bytes
171  // of stack space for the register save area.
172  return true;
173 }
174 
177  std::vector<CalleeSavedInfo> &CSI) const {
179  MachineFrameInfo &MFFrame = MF.getFrameInfo();
180  bool IsVarArg = MF.getFunction().isVarArg();
181  if (CSI.empty())
182  return true; // Early exit if no callee saved registers are modified!
183 
184  unsigned LowGPR = 0;
185  unsigned HighGPR = SystemZ::R15D;
186  int StartSPOffset = SystemZMC::ELFCallFrameSize;
187  for (auto &CS : CSI) {
188  Register Reg = CS.getReg();
189  int Offset = getRegSpillOffset(MF, Reg);
190  if (Offset) {
191  if (SystemZ::GR64BitRegClass.contains(Reg) && StartSPOffset > Offset) {
192  LowGPR = Reg;
193  StartSPOffset = Offset;
194  }
195  Offset -= SystemZMC::ELFCallFrameSize;
196  int FrameIdx = MFFrame.CreateFixedSpillStackObject(8, Offset);
197  CS.setFrameIdx(FrameIdx);
198  } else
199  CS.setFrameIdx(INT32_MAX);
200  }
201 
202  // Save the range of call-saved registers, for use by the
203  // prologue/epilogue inserters.
204  ZFI->setRestoreGPRRegs(LowGPR, HighGPR, StartSPOffset);
205  if (IsVarArg) {
206  // Also save the GPR varargs, if any. R6D is call-saved, so would
207  // already be included, but we also need to handle the call-clobbered
208  // argument registers.
209  Register FirstGPR = ZFI->getVarArgsFirstGPR();
210  if (FirstGPR < SystemZ::ELFNumArgGPRs) {
211  unsigned Reg = SystemZ::ELFArgGPRs[FirstGPR];
212  int Offset = getRegSpillOffset(MF, Reg);
213  if (StartSPOffset > Offset) {
214  LowGPR = Reg; StartSPOffset = Offset;
215  }
216  }
217  }
218  ZFI->setSpillGPRRegs(LowGPR, HighGPR, StartSPOffset);
219 
220  // Create fixed stack objects for the remaining registers.
221  int CurrOffset = -SystemZMC::ELFCallFrameSize;
222  if (usePackedStack(MF))
223  CurrOffset += StartSPOffset;
224 
225  for (auto &CS : CSI) {
226  if (CS.getFrameIdx() != INT32_MAX)
227  continue;
228  Register Reg = CS.getReg();
230  unsigned Size = TRI->getSpillSize(*RC);
231  CurrOffset -= Size;
232  assert(CurrOffset % 8 == 0 &&
233  "8-byte alignment required for for all register save slots");
234  int FrameIdx = MFFrame.CreateFixedSpillStackObject(Size, CurrOffset);
235  CS.setFrameIdx(FrameIdx);
236  }
237 
238  return true;
239 }
240 
242  BitVector &SavedRegs,
243  RegScavenger *RS) const {
245 
246  MachineFrameInfo &MFFrame = MF.getFrameInfo();
248  bool HasFP = hasFP(MF);
250  bool IsVarArg = MF.getFunction().isVarArg();
251 
252  // va_start stores incoming FPR varargs in the normal way, but delegates
253  // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
254  // Record these pending uses, which typically include the call-saved
255  // argument register R6D.
256  if (IsVarArg)
257  for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::ELFNumArgGPRs; ++I)
258  SavedRegs.set(SystemZ::ELFArgGPRs[I]);
259 
260  // If there are any landing pads, entering them will modify r6/r7.
261  if (!MF.getLandingPads().empty()) {
262  SavedRegs.set(SystemZ::R6D);
263  SavedRegs.set(SystemZ::R7D);
264  }
265 
266  // If the function requires a frame pointer, record that the hard
267  // frame pointer will be clobbered.
268  if (HasFP)
269  SavedRegs.set(SystemZ::R11D);
270 
271  // If the function calls other functions, record that the return
272  // address register will be clobbered.
273  if (MFFrame.hasCalls())
274  SavedRegs.set(SystemZ::R14D);
275 
276  // If we are saving GPRs other than the stack pointer, we might as well
277  // save and restore the stack pointer at the same time, via STMG and LMG.
278  // This allows the deallocation to be done by the LMG, rather than needing
279  // a separate %r15 addition.
280  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
281  for (unsigned I = 0; CSRegs[I]; ++I) {
282  unsigned Reg = CSRegs[I];
283  if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
284  SavedRegs.set(SystemZ::R15D);
285  break;
286  }
287  }
288 }
289 
291  : SystemZFrameLowering(TargetFrameLowering::StackGrowsDown, Align(8), 0,
292  Align(8), /* StackRealignable */ false),
293  RegSpillOffsets(0) {
294 
295  // Due to the SystemZ ABI, the DWARF CFA (Canonical Frame Address) is not
296  // equal to the incoming stack pointer, but to incoming stack pointer plus
297  // 160. Instead of using a Local Area Offset, the Register save area will
298  // be occupied by fixed frame objects, and all offsets are actually
299  // relative to CFA.
300 
301  // Create a mapping from register number to save slot offset.
302  // These offsets are relative to the start of the register save area.
303  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
304  for (const auto &Entry : ELFSpillOffsetTable)
305  RegSpillOffsets[Entry.Reg] = Entry.Offset;
306 }
307 
308 // Add GPR64 to the save instruction being built by MIB, which is in basic
309 // block MBB. IsImplicit says whether this is an explicit operand to the
310 // instruction, or an implicit one that comes between the explicit start
311 // and end registers.
313  unsigned GPR64, bool IsImplicit) {
314  const TargetRegisterInfo *RI =
316  Register GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
317  bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
318  if (!IsLive || !IsImplicit) {
319  MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
320  if (!IsLive)
321  MBB.addLiveIn(GPR64);
322  }
323 }
324 
328  if (CSI.empty())
329  return false;
330 
331  MachineFunction &MF = *MBB.getParent();
334  bool IsVarArg = MF.getFunction().isVarArg();
335  DebugLoc DL;
336 
337  // Save GPRs
338  SystemZ::GPRRegs SpillGPRs = ZFI->getSpillGPRRegs();
339  if (SpillGPRs.LowGPR) {
340  assert(SpillGPRs.LowGPR != SpillGPRs.HighGPR &&
341  "Should be saving %r15 and something else");
342 
343  // Build an STMG instruction.
344  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
345 
346  // Add the explicit register operands.
347  addSavedGPR(MBB, MIB, SpillGPRs.LowGPR, false);
348  addSavedGPR(MBB, MIB, SpillGPRs.HighGPR, false);
349 
350  // Add the address.
351  MIB.addReg(SystemZ::R15D).addImm(SpillGPRs.GPROffset);
352 
353  // Make sure all call-saved GPRs are included as operands and are
354  // marked as live on entry.
355  for (const CalleeSavedInfo &I : CSI) {
356  Register Reg = I.getReg();
357  if (SystemZ::GR64BitRegClass.contains(Reg))
358  addSavedGPR(MBB, MIB, Reg, true);
359  }
360 
361  // ...likewise GPR varargs.
362  if (IsVarArg)
363  for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::ELFNumArgGPRs; ++I)
364  addSavedGPR(MBB, MIB, SystemZ::ELFArgGPRs[I], true);
365  }
366 
367  // Save FPRs/VRs in the normal TargetInstrInfo way.
368  for (const CalleeSavedInfo &I : CSI) {
369  Register Reg = I.getReg();
370  if (SystemZ::FP64BitRegClass.contains(Reg)) {
371  MBB.addLiveIn(Reg);
372  TII->storeRegToStackSlot(MBB, MBBI, Reg, true, I.getFrameIdx(),
373  &SystemZ::FP64BitRegClass, TRI);
374  }
375  if (SystemZ::VR128BitRegClass.contains(Reg)) {
376  MBB.addLiveIn(Reg);
377  TII->storeRegToStackSlot(MBB, MBBI, Reg, true, I.getFrameIdx(),
378  &SystemZ::VR128BitRegClass, TRI);
379  }
380  }
381 
382  return true;
383 }
384 
388  if (CSI.empty())
389  return false;
390 
391  MachineFunction &MF = *MBB.getParent();
394  bool HasFP = hasFP(MF);
395  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
396 
397  // Restore FPRs/VRs in the normal TargetInstrInfo way.
398  for (const CalleeSavedInfo &I : CSI) {
399  Register Reg = I.getReg();
400  if (SystemZ::FP64BitRegClass.contains(Reg))
401  TII->loadRegFromStackSlot(MBB, MBBI, Reg, I.getFrameIdx(),
402  &SystemZ::FP64BitRegClass, TRI);
403  if (SystemZ::VR128BitRegClass.contains(Reg))
404  TII->loadRegFromStackSlot(MBB, MBBI, Reg, I.getFrameIdx(),
405  &SystemZ::VR128BitRegClass, TRI);
406  }
407 
408  // Restore call-saved GPRs (but not call-clobbered varargs, which at
409  // this point might hold return values).
410  SystemZ::GPRRegs RestoreGPRs = ZFI->getRestoreGPRRegs();
411  if (RestoreGPRs.LowGPR) {
412  // If we saved any of %r2-%r5 as varargs, we should also be saving
413  // and restoring %r6. If we're saving %r6 or above, we should be
414  // restoring it too.
415  assert(RestoreGPRs.LowGPR != RestoreGPRs.HighGPR &&
416  "Should be loading %r15 and something else");
417 
418  // Build an LMG instruction.
419  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
420 
421  // Add the explicit register operands.
422  MIB.addReg(RestoreGPRs.LowGPR, RegState::Define);
423  MIB.addReg(RestoreGPRs.HighGPR, RegState::Define);
424 
425  // Add the address.
426  MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
427  MIB.addImm(RestoreGPRs.GPROffset);
428 
429  // Do a second scan adding regs as being defined by instruction
430  for (const CalleeSavedInfo &I : CSI) {
431  Register Reg = I.getReg();
432  if (Reg != RestoreGPRs.LowGPR && Reg != RestoreGPRs.HighGPR &&
433  SystemZ::GR64BitRegClass.contains(Reg))
435  }
436  }
437 
438  return true;
439 }
440 
442  MachineFunction &MF, RegScavenger *RS) const {
443  MachineFrameInfo &MFFrame = MF.getFrameInfo();
446  bool BackChain = MF.getFunction().hasFnAttribute("backchain");
447 
448  if (!usePackedStack(MF) || BackChain)
449  // Create the incoming register save area.
451 
452  // Get the size of our stack frame to be allocated ...
453  uint64_t StackSize = (MFFrame.estimateStackSize(MF) +
455  // ... and the maximum offset we may need to reach into the
456  // caller's frame to access the save area or stack arguments.
457  int64_t MaxArgOffset = 0;
458  for (int I = MFFrame.getObjectIndexBegin(); I != 0; ++I)
459  if (MFFrame.getObjectOffset(I) >= 0) {
460  int64_t ArgOffset = MFFrame.getObjectOffset(I) +
461  MFFrame.getObjectSize(I);
462  MaxArgOffset = std::max(MaxArgOffset, ArgOffset);
463  }
464 
465  uint64_t MaxReach = StackSize + MaxArgOffset;
466  if (!isUInt<12>(MaxReach)) {
467  // We may need register scavenging slots if some parts of the frame
468  // are outside the reach of an unsigned 12-bit displacement.
469  // Create 2 for the case where both addresses in an MVC are
470  // out of range.
471  RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false));
472  RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false));
473  }
474 
475  // If R6 is used as an argument register it is still callee saved. If it in
476  // this case is not clobbered (and restored) it should never be marked as
477  // killed.
478  if (MF.front().isLiveIn(SystemZ::R6D) &&
479  ZFI->getRestoreGPRRegs().LowGPR != SystemZ::R6D)
480  for (auto &MO : MRI->use_nodbg_operands(SystemZ::R6D))
481  MO.setIsKill(false);
482 }
483 
484 // Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
487  Register Reg, int64_t NumBytes,
488  const TargetInstrInfo *TII) {
489  while (NumBytes) {
490  unsigned Opcode;
491  int64_t ThisVal = NumBytes;
492  if (isInt<16>(NumBytes))
493  Opcode = SystemZ::AGHI;
494  else {
495  Opcode = SystemZ::AGFI;
496  // Make sure we maintain 8-byte stack alignment.
497  int64_t MinVal = -uint64_t(1) << 31;
498  int64_t MaxVal = (int64_t(1) << 31) - 8;
499  if (ThisVal < MinVal)
500  ThisVal = MinVal;
501  else if (ThisVal > MaxVal)
502  ThisVal = MaxVal;
503  }
504  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
505  .addReg(Reg).addImm(ThisVal);
506  // The CC implicit def is dead.
507  MI->getOperand(3).setIsDead();
508  NumBytes -= ThisVal;
509  }
510 }
511 
512 // Add CFI for the new CFA offset.
515  const DebugLoc &DL, int Offset,
516  const SystemZInstrInfo *ZII) {
517  unsigned CFIIndex = MBB.getParent()->addFrameInst(
518  MCCFIInstruction::cfiDefCfaOffset(nullptr, -Offset));
519  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
520  .addCFIIndex(CFIIndex);
521 }
522 
523 // Add CFI for the new frame location.
526  const DebugLoc &DL, unsigned Reg,
527  const SystemZInstrInfo *ZII) {
528  MachineFunction &MF = *MBB.getParent();
529  MachineModuleInfo &MMI = MF.getMMI();
530  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
531  unsigned RegNum = MRI->getDwarfRegNum(Reg, true);
532  unsigned CFIIndex = MF.addFrameInst(
533  MCCFIInstruction::createDefCfaRegister(nullptr, RegNum));
534  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
535  .addCFIIndex(CFIIndex);
536 }
537 
539  MachineBasicBlock &MBB) const {
540  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
542  const SystemZTargetLowering &TLI = *STI.getTargetLowering();
543  MachineFrameInfo &MFFrame = MF.getFrameInfo();
544  auto *ZII = static_cast<const SystemZInstrInfo *>(STI.getInstrInfo());
547  MachineModuleInfo &MMI = MF.getMMI();
548  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
549  const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
550  bool HasFP = hasFP(MF);
551 
552  // In GHC calling convention C stack space, including the ABI-defined
553  // 160-byte base area, is (de)allocated by GHC itself. This stack space may
554  // be used by LLVM as spill slots for the tail recursive GHC functions. Thus
555  // do not allocate stack space here, too.
557  if (MFFrame.getStackSize() > 2048 * sizeof(long)) {
559  "Pre allocated stack space for GHC function is too small");
560  }
561  if (HasFP) {
563  "In GHC calling convention a frame pointer is not supported");
564  }
566  return;
567  }
568 
569  // Debug location must be unknown since the first debug location is used
570  // to determine the end of the prologue.
571  DebugLoc DL;
572 
573  // The current offset of the stack pointer from the CFA.
574  int64_t SPOffsetFromCFA = -SystemZMC::ELFCFAOffsetFromInitialSP;
575 
576  if (ZFI->getSpillGPRRegs().LowGPR) {
577  // Skip over the GPR saves.
578  if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
579  ++MBBI;
580  else
581  llvm_unreachable("Couldn't skip over GPR saves");
582 
583  // Add CFI for the GPR saves.
584  for (auto &Save : CSI) {
585  Register Reg = Save.getReg();
586  if (SystemZ::GR64BitRegClass.contains(Reg)) {
587  int FI = Save.getFrameIdx();
588  int64_t Offset = MFFrame.getObjectOffset(FI);
589  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
590  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
591  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
592  .addCFIIndex(CFIIndex);
593  }
594  }
595  }
596 
597  uint64_t StackSize = MFFrame.getStackSize();
598  // We need to allocate the ABI-defined 160-byte base area whenever
599  // we allocate stack space for our own use and whenever we call another
600  // function.
601  bool HasStackObject = false;
602  for (unsigned i = 0, e = MFFrame.getObjectIndexEnd(); i != e; ++i)
603  if (!MFFrame.isDeadObjectIndex(i)) {
604  HasStackObject = true;
605  break;
606  }
607  if (HasStackObject || MFFrame.hasCalls())
608  StackSize += SystemZMC::ELFCallFrameSize;
609  // Don't allocate the incoming reg save area.
610  StackSize = StackSize > SystemZMC::ELFCallFrameSize
611  ? StackSize - SystemZMC::ELFCallFrameSize
612  : 0;
613  MFFrame.setStackSize(StackSize);
614 
615  if (StackSize) {
616  // Allocate StackSize bytes.
617  int64_t Delta = -int64_t(StackSize);
618  const unsigned ProbeSize = TLI.getStackProbeSize(MF);
619  bool FreeProbe = (ZFI->getSpillGPRRegs().GPROffset &&
620  (ZFI->getSpillGPRRegs().GPROffset + StackSize) < ProbeSize);
621  if (!FreeProbe &&
623  // Stack probing may involve looping, but splitting the prologue block
624  // is not possible at this point since it would invalidate the
625  // SaveBlocks / RestoreBlocks sets of PEI in the single block function
626  // case. Build a pseudo to be handled later by inlineStackProbe().
627  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::PROBED_STACKALLOC))
628  .addImm(StackSize);
629  }
630  else {
631  bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
632  // If we need backchain, save current stack pointer. R1 is free at
633  // this point.
634  if (StoreBackchain)
635  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
636  .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
637  emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
638  buildCFAOffs(MBB, MBBI, DL, SPOffsetFromCFA + Delta, ZII);
639  if (StoreBackchain)
640  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
641  .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
643  }
644  SPOffsetFromCFA += Delta;
645  }
646 
647  if (HasFP) {
648  // Copy the base of the frame to R11.
649  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
650  .addReg(SystemZ::R15D);
651 
652  // Add CFI for the new frame location.
653  buildDefCFAReg(MBB, MBBI, DL, SystemZ::R11D, ZII);
654 
655  // Mark the FramePtr as live at the beginning of every block except
656  // the entry block. (We'll have marked R11 as live on entry when
657  // saving the GPRs.)
658  for (MachineBasicBlock &MBBJ : llvm::drop_begin(MF))
659  MBBJ.addLiveIn(SystemZ::R11D);
660  }
661 
662  // Skip over the FPR/VR saves.
663  SmallVector<unsigned, 8> CFIIndexes;
664  for (auto &Save : CSI) {
665  Register Reg = Save.getReg();
666  if (SystemZ::FP64BitRegClass.contains(Reg)) {
667  if (MBBI != MBB.end() &&
668  (MBBI->getOpcode() == SystemZ::STD ||
669  MBBI->getOpcode() == SystemZ::STDY))
670  ++MBBI;
671  else
672  llvm_unreachable("Couldn't skip over FPR save");
673  } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
674  if (MBBI != MBB.end() &&
675  MBBI->getOpcode() == SystemZ::VST)
676  ++MBBI;
677  else
678  llvm_unreachable("Couldn't skip over VR save");
679  } else
680  continue;
681 
682  // Add CFI for the this save.
683  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
684  Register IgnoredFrameReg;
685  int64_t Offset =
686  getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg)
687  .getFixed();
688 
689  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
690  nullptr, DwarfReg, SPOffsetFromCFA + Offset));
691  CFIIndexes.push_back(CFIIndex);
692  }
693  // Complete the CFI for the FPR/VR saves, modelling them as taking effect
694  // after the last save.
695  for (auto CFIIndex : CFIIndexes) {
696  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
697  .addCFIIndex(CFIIndex);
698  }
699 }
700 
702  MachineBasicBlock &MBB) const {
704  auto *ZII =
705  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
707  MachineFrameInfo &MFFrame = MF.getFrameInfo();
708 
709  // See SystemZELFFrameLowering::emitPrologue
711  return;
712 
713  // Skip the return instruction.
714  assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
715 
716  uint64_t StackSize = MFFrame.getStackSize();
717  if (ZFI->getRestoreGPRRegs().LowGPR) {
718  --MBBI;
719  unsigned Opcode = MBBI->getOpcode();
720  if (Opcode != SystemZ::LMG)
721  llvm_unreachable("Expected to see callee-save register restore code");
722 
723  unsigned AddrOpNo = 2;
724  DebugLoc DL = MBBI->getDebugLoc();
725  uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
726  unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
727 
728  // If the offset is too large, use the largest stack-aligned offset
729  // and add the rest to the base register (the stack or frame pointer).
730  if (!NewOpcode) {
731  uint64_t NumBytes = Offset - 0x7fff8;
732  emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
733  NumBytes, ZII);
734  Offset -= NumBytes;
735  NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
736  assert(NewOpcode && "No restore instruction available");
737  }
738 
739  MBBI->setDesc(ZII->get(NewOpcode));
740  MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
741  } else if (StackSize) {
742  DebugLoc DL = MBBI->getDebugLoc();
743  emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
744  }
745 }
746 
748  MachineFunction &MF, MachineBasicBlock &PrologMBB) const {
749  auto *ZII =
750  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
752  const SystemZTargetLowering &TLI = *STI.getTargetLowering();
753 
754  MachineInstr *StackAllocMI = nullptr;
755  for (MachineInstr &MI : PrologMBB)
756  if (MI.getOpcode() == SystemZ::PROBED_STACKALLOC) {
757  StackAllocMI = &MI;
758  break;
759  }
760  if (StackAllocMI == nullptr)
761  return;
762  uint64_t StackSize = StackAllocMI->getOperand(0).getImm();
763  const unsigned ProbeSize = TLI.getStackProbeSize(MF);
764  uint64_t NumFullBlocks = StackSize / ProbeSize;
765  uint64_t Residual = StackSize % ProbeSize;
766  int64_t SPOffsetFromCFA = -SystemZMC::ELFCFAOffsetFromInitialSP;
767  MachineBasicBlock *MBB = &PrologMBB;
768  MachineBasicBlock::iterator MBBI = StackAllocMI;
769  const DebugLoc DL = StackAllocMI->getDebugLoc();
770 
771  // Allocate a block of Size bytes on the stack and probe it.
772  auto allocateAndProbe = [&](MachineBasicBlock &InsMBB,
773  MachineBasicBlock::iterator InsPt, unsigned Size,
774  bool EmitCFI) -> void {
775  emitIncrement(InsMBB, InsPt, DL, SystemZ::R15D, -int64_t(Size), ZII);
776  if (EmitCFI) {
777  SPOffsetFromCFA -= Size;
778  buildCFAOffs(InsMBB, InsPt, DL, SPOffsetFromCFA, ZII);
779  }
780  // Probe by means of a volatile compare.
783  BuildMI(InsMBB, InsPt, DL, ZII->get(SystemZ::CG))
784  .addReg(SystemZ::R0D, RegState::Undef)
785  .addReg(SystemZ::R15D).addImm(Size - 8).addReg(0)
786  .addMemOperand(MMO);
787  };
788 
789  bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
790  if (StoreBackchain)
791  BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR))
792  .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
793 
794  MachineBasicBlock *DoneMBB = nullptr;
795  MachineBasicBlock *LoopMBB = nullptr;
796  if (NumFullBlocks < 3) {
797  // Emit unrolled probe statements.
798  for (unsigned int i = 0; i < NumFullBlocks; i++)
799  allocateAndProbe(*MBB, MBBI, ProbeSize, true/*EmitCFI*/);
800  } else {
801  // Emit a loop probing the pages.
802  uint64_t LoopAlloc = ProbeSize * NumFullBlocks;
803  SPOffsetFromCFA -= LoopAlloc;
804 
805  // Use R0D to hold the exit value.
806  BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R0D)
807  .addReg(SystemZ::R15D);
808  buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R0D, ZII);
809  emitIncrement(*MBB, MBBI, DL, SystemZ::R0D, -int64_t(LoopAlloc), ZII);
810  buildCFAOffs(*MBB, MBBI, DL, -int64_t(SystemZMC::ELFCallFrameSize + LoopAlloc),
811  ZII);
812 
813  DoneMBB = SystemZ::splitBlockBefore(MBBI, MBB);
814  LoopMBB = SystemZ::emitBlockAfter(MBB);
815  MBB->addSuccessor(LoopMBB);
816  LoopMBB->addSuccessor(LoopMBB);
817  LoopMBB->addSuccessor(DoneMBB);
818 
819  MBB = LoopMBB;
820  allocateAndProbe(*MBB, MBB->end(), ProbeSize, false/*EmitCFI*/);
821  BuildMI(*MBB, MBB->end(), DL, ZII->get(SystemZ::CLGR))
822  .addReg(SystemZ::R15D).addReg(SystemZ::R0D);
823  BuildMI(*MBB, MBB->end(), DL, ZII->get(SystemZ::BRC))
825 
826  MBB = DoneMBB;
827  MBBI = DoneMBB->begin();
828  buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R15D, ZII);
829  }
830 
831  if (Residual)
832  allocateAndProbe(*MBB, MBBI, Residual, true/*EmitCFI*/);
833 
834  if (StoreBackchain)
835  BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::STG))
836  .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
838 
839  StackAllocMI->eraseFromParent();
840  if (DoneMBB != nullptr) {
841  // Compute the live-in lists for the new blocks.
842  recomputeLiveIns(*DoneMBB);
843  recomputeLiveIns(*LoopMBB);
844  }
845 }
846 
848  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
850 }
851 
853  const MachineFunction &MF, int FI, Register &FrameReg) const {
854  // Our incoming SP is actually SystemZMC::ELFCallFrameSize below the CFA, so
855  // add that difference here.
856  StackOffset Offset =
859 }
860 
862  Register Reg) const {
863  bool IsVarArg = MF.getFunction().isVarArg();
864  bool BackChain = MF.getFunction().hasFnAttribute("backchain");
865  bool SoftFloat = MF.getSubtarget<SystemZSubtarget>().hasSoftFloat();
866  unsigned Offset = RegSpillOffsets[Reg];
867  if (usePackedStack(MF) && !(IsVarArg && !SoftFloat)) {
868  if (SystemZ::GR64BitRegClass.contains(Reg))
869  // Put all GPRs at the top of the Register save area with packed
870  // stack. Make room for the backchain if needed.
871  Offset += BackChain ? 24 : 32;
872  else
873  Offset = 0;
874  }
875  return Offset;
876 }
877 
879  MachineFunction &MF) const {
881  int FI = ZFI->getFramePointerSaveIndex();
882  if (!FI) {
883  MachineFrameInfo &MFFrame = MF.getFrameInfo();
885  FI = MFFrame.CreateFixedObject(8, Offset, false);
886  ZFI->setFramePointerSaveIndex(FI);
887  }
888  return FI;
889 }
890 
892  bool HasPackedStackAttr = MF.getFunction().hasFnAttribute("packed-stack");
893  bool BackChain = MF.getFunction().hasFnAttribute("backchain");
894  bool SoftFloat = MF.getSubtarget<SystemZSubtarget>().hasSoftFloat();
895  if (HasPackedStackAttr && BackChain && !SoftFloat)
896  report_fatal_error("packed-stack + backchain + hard-float is unsupported.");
897  bool CallConv = MF.getFunction().getCallingConv() != CallingConv::GHC;
898  return HasPackedStackAttr && CallConv;
899 }
900 
902  : SystemZFrameLowering(TargetFrameLowering::StackGrowsDown, Align(32), 0,
903  Align(32), /* StackRealignable */ false),
904  RegSpillOffsets(-1) {
905 
906  // Create a mapping from register number to save slot offset.
907  // These offsets are relative to the start of the local are area.
908  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
909  for (const auto &Entry : XPLINKSpillOffsetTable)
910  RegSpillOffsets[Entry.Reg] = Entry.Offset;
911 }
912 
913 // Checks if the function is a potential candidate for being a XPLeaf routine.
914 static bool isXPLeafCandidate(const MachineFunction &MF) {
915  const MachineFrameInfo &MFFrame = MF.getFrameInfo();
916  const MachineRegisterInfo &MRI = MF.getRegInfo();
917  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
918  auto *Regs =
919  static_cast<SystemZXPLINK64Registers *>(Subtarget.getSpecialRegisters());
920 
921  // If function calls other functions including alloca, then it is not a XPLeaf
922  // routine.
923  if (MFFrame.hasCalls())
924  return false;
925 
926  // If the function has var Sized Objects, then it is not a XPLeaf routine.
927  if (MFFrame.hasVarSizedObjects())
928  return false;
929 
930  // If the function adjusts the stack, then it is not a XPLeaf routine.
931  if (MFFrame.adjustsStack())
932  return false;
933 
934  // If function modifies the stack pointer register, then it is not a XPLeaf
935  // routine.
936  if (MRI.isPhysRegModified(Regs->getStackPointerRegister()))
937  return false;
938 
939  // If function modifies the ADA register, then it is not a XPLeaf routine.
940  if (MRI.isPhysRegModified(Regs->getAddressOfCalleeRegister()))
941  return false;
942 
943  // If function modifies the return address register, then it is not a XPLeaf
944  // routine.
945  if (MRI.isPhysRegModified(Regs->getReturnFunctionAddressRegister()))
946  return false;
947 
948  // If the backchain pointer should be stored, then it is not a XPLeaf routine.
949  if (MF.getFunction().hasFnAttribute("backchain"))
950  return false;
951 
952  // If function acquires its own stack frame, then it is not a XPLeaf routine.
953  // At the time this function is called, only slots for local variables are
954  // allocated, so this is a very rough estimate.
955  if (MFFrame.estimateStackSize(MF) > 0)
956  return false;
957 
958  return true;
959 }
960 
963  std::vector<CalleeSavedInfo> &CSI) const {
964  MachineFrameInfo &MFFrame = MF.getFrameInfo();
966  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
967  auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
968  auto &GRRegClass = SystemZ::GR64BitRegClass;
969 
970  // At this point, the result of isXPLeafCandidate() is not accurate because
971  // the size of the save area has not yet been determined. If
972  // isXPLeafCandidate() indicates a potential leaf function, and there are no
973  // callee-save registers, then it is indeed a leaf function, and we can early
974  // exit.
975  // TODO: It is possible for leaf functions to use callee-saved registers.
976  // It can use the 0-2k range between R4 and the caller's stack frame without
977  // acquiring its own stack frame.
978  bool IsLeaf = CSI.empty() && isXPLeafCandidate(MF);
979  if (IsLeaf)
980  return true;
981 
982  // For non-leaf functions:
983  // - the address of callee (entry point) register R6 must be saved
984  CSI.push_back(CalleeSavedInfo(Regs.getAddressOfCalleeRegister()));
985  CSI.back().setRestored(false);
986 
987  // The return address register R7 must be saved and restored.
988  CSI.push_back(CalleeSavedInfo(Regs.getReturnFunctionAddressRegister()));
989 
990  // If the function needs a frame pointer, or if the backchain pointer should
991  // be stored, then save the stack pointer register R4.
992  if (hasFP(MF) || MF.getFunction().hasFnAttribute("backchain"))
993  CSI.push_back(CalleeSavedInfo(Regs.getStackPointerRegister()));
994 
995  // Scan the call-saved GPRs and find the bounds of the register spill area.
996  Register LowRestoreGPR = 0;
997  int LowRestoreOffset = INT32_MAX;
998  Register LowSpillGPR = 0;
999  int LowSpillOffset = INT32_MAX;
1000  Register HighGPR = 0;
1001  int HighOffset = -1;
1002 
1003  for (auto &CS : CSI) {
1004  Register Reg = CS.getReg();
1005  int Offset = RegSpillOffsets[Reg];
1006  if (Offset >= 0) {
1007  if (GRRegClass.contains(Reg)) {
1008  if (LowSpillOffset > Offset) {
1009  LowSpillOffset = Offset;
1010  LowSpillGPR = Reg;
1011  }
1012  if (CS.isRestored() && LowRestoreOffset > Offset) {
1013  LowRestoreOffset = Offset;
1014  LowRestoreGPR = Reg;
1015  }
1016 
1017  if (Offset > HighOffset) {
1018  HighOffset = Offset;
1019  HighGPR = Reg;
1020  }
1021  // Non-volatile GPRs are saved in the dedicated register save area at
1022  // the bottom of the stack and are not truly part of the "normal" stack
1023  // frame. Mark the frame index as NoAlloc to indicate it as such.
1024  unsigned RegSize = 8;
1025  int FrameIdx = MFFrame.CreateFixedSpillStackObject(RegSize, Offset);
1026  CS.setFrameIdx(FrameIdx);
1027  MFFrame.setStackID(FrameIdx, TargetStackID::NoAlloc);
1028  }
1029  } else {
1030  Register Reg = CS.getReg();
1032  Align Alignment = TRI->getSpillAlign(*RC);
1033  unsigned Size = TRI->getSpillSize(*RC);
1034  Alignment = std::min(Alignment, getStackAlign());
1035  int FrameIdx = MFFrame.CreateStackObject(Size, Alignment, true);
1036  CS.setFrameIdx(FrameIdx);
1037  }
1038  }
1039 
1040  // Save the range of call-saved registers, for use by the
1041  // prologue/epilogue inserters.
1042  if (LowRestoreGPR)
1043  MFI->setRestoreGPRRegs(LowRestoreGPR, HighGPR, LowRestoreOffset);
1044 
1045  // Save the range of call-saved registers, for use by the epilogue inserter.
1046  assert(LowSpillGPR && "Expected registers to spill");
1047  MFI->setSpillGPRRegs(LowSpillGPR, HighGPR, LowSpillOffset);
1048 
1049  return true;
1050 }
1051 
1053  BitVector &SavedRegs,
1054  RegScavenger *RS) const {
1055  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1056 
1057  bool HasFP = hasFP(MF);
1058  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
1059  auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
1060 
1061  // If the function requires a frame pointer, record that the hard
1062  // frame pointer will be clobbered.
1063  if (HasFP)
1064  SavedRegs.set(Regs.getFramePointerRegister());
1065 }
1066 
1069  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
1070  if (CSI.empty())
1071  return true;
1072 
1073  MachineFunction &MF = *MBB.getParent();
1075  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
1076  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1077  auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
1078  SystemZ::GPRRegs SpillGPRs = ZFI->getSpillGPRRegs();
1079  DebugLoc DL;
1080 
1081  // Save GPRs
1082  if (SpillGPRs.LowGPR) {
1083  assert(SpillGPRs.LowGPR != SpillGPRs.HighGPR &&
1084  "Should be saving multiple registers");
1085 
1086  // Build an STM/STMG instruction.
1087  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
1088 
1089  // Add the explicit register operands.
1090  addSavedGPR(MBB, MIB, SpillGPRs.LowGPR, false);
1091  addSavedGPR(MBB, MIB, SpillGPRs.HighGPR, false);
1092 
1093  // Add the address r4
1094  MIB.addReg(Regs.getStackPointerRegister());
1095 
1096  // Add the partial offset
1097  // We cannot add the actual offset as, at the stack is not finalized
1098  MIB.addImm(SpillGPRs.GPROffset);
1099 
1100  // Make sure all call-saved GPRs are included as operands and are
1101  // marked as live on entry.
1102  auto &GRRegClass = SystemZ::GR64BitRegClass;
1103  for (const CalleeSavedInfo &I : CSI) {
1104  Register Reg = I.getReg();
1105  if (GRRegClass.contains(Reg))
1106  addSavedGPR(MBB, MIB, Reg, true);
1107  }
1108  }
1109 
1110  // Spill FPRs to the stack in the normal TargetInstrInfo way
1111  for (const CalleeSavedInfo &I : CSI) {
1112  Register Reg = I.getReg();
1113  if (SystemZ::FP64BitRegClass.contains(Reg)) {
1114  MBB.addLiveIn(Reg);
1115  TII->storeRegToStackSlot(MBB, MBBI, Reg, true, I.getFrameIdx(),
1116  &SystemZ::FP64BitRegClass, TRI);
1117  }
1118  if (SystemZ::VR128BitRegClass.contains(Reg)) {
1119  MBB.addLiveIn(Reg);
1120  TII->storeRegToStackSlot(MBB, MBBI, Reg, true, I.getFrameIdx(),
1121  &SystemZ::VR128BitRegClass, TRI);
1122  }
1123  }
1124 
1125  return true;
1126 }
1127 
1131 
1132  if (CSI.empty())
1133  return false;
1134 
1135  MachineFunction &MF = *MBB.getParent();
1137  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
1138  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1139  auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
1140 
1141  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1142 
1143  // Restore FPRs in the normal TargetInstrInfo way.
1144  for (const CalleeSavedInfo &I : CSI) {
1145  Register Reg = I.getReg();
1146  if (SystemZ::FP64BitRegClass.contains(Reg))
1147  TII->loadRegFromStackSlot(MBB, MBBI, Reg, I.getFrameIdx(),
1148  &SystemZ::FP64BitRegClass, TRI);
1149  if (SystemZ::VR128BitRegClass.contains(Reg))
1150  TII->loadRegFromStackSlot(MBB, MBBI, Reg, I.getFrameIdx(),
1151  &SystemZ::VR128BitRegClass, TRI);
1152  }
1153 
1154  // Restore call-saved GPRs (but not call-clobbered varargs, which at
1155  // this point might hold return values).
1156  SystemZ::GPRRegs RestoreGPRs = ZFI->getRestoreGPRRegs();
1157  if (RestoreGPRs.LowGPR) {
1158  assert(isInt<20>(Regs.getStackPointerBias() + RestoreGPRs.GPROffset));
1159  if (RestoreGPRs.LowGPR == RestoreGPRs.HighGPR)
1160  // Build an LG/L instruction.
1161  BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LG), RestoreGPRs.LowGPR)
1162  .addReg(Regs.getStackPointerRegister())
1163  .addImm(Regs.getStackPointerBias() + RestoreGPRs.GPROffset)
1164  .addReg(0);
1165  else {
1166  // Build an LMG/LM instruction.
1167  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
1168 
1169  // Add the explicit register operands.
1170  MIB.addReg(RestoreGPRs.LowGPR, RegState::Define);
1171  MIB.addReg(RestoreGPRs.HighGPR, RegState::Define);
1172 
1173  // Add the address.
1174  MIB.addReg(Regs.getStackPointerRegister());
1175  MIB.addImm(Regs.getStackPointerBias() + RestoreGPRs.GPROffset);
1176 
1177  // Do a second scan adding regs as being defined by instruction
1178  for (const CalleeSavedInfo &I : CSI) {
1179  Register Reg = I.getReg();
1180  if (Reg > RestoreGPRs.LowGPR && Reg < RestoreGPRs.HighGPR)
1182  }
1183  }
1184  }
1185 
1186  return true;
1187 }
1188 
1190  MachineBasicBlock &MBB) const {
1191  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
1192  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
1195  auto *ZII = static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
1196  auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
1197  MachineFrameInfo &MFFrame = MF.getFrameInfo();
1198  MachineInstr *StoreInstr = nullptr;
1199 
1201 
1202  bool HasFP = hasFP(MF);
1203  // Debug location must be unknown since the first debug location is used
1204  // to determine the end of the prologue.
1205  DebugLoc DL;
1206  uint64_t Offset = 0;
1207 
1208  const uint64_t StackSize = MFFrame.getStackSize();
1209 
1210  if (ZFI->getSpillGPRRegs().LowGPR) {
1211  // Skip over the GPR saves.
1212  if ((MBBI != MBB.end()) && ((MBBI->getOpcode() == SystemZ::STMG))) {
1213  const int Operand = 3;
1214  // Now we can set the offset for the operation, since now the Stack
1215  // has been finalized.
1216  Offset = Regs.getStackPointerBias() + MBBI->getOperand(Operand).getImm();
1217  // Maximum displacement for STMG instruction.
1218  if (isInt<20>(Offset - StackSize))
1219  Offset -= StackSize;
1220  else
1221  StoreInstr = &*MBBI;
1222  MBBI->getOperand(Operand).setImm(Offset);
1223  ++MBBI;
1224  } else
1225  llvm_unreachable("Couldn't skip over GPR saves");
1226  }
1227 
1228  if (StackSize) {
1229  MachineBasicBlock::iterator InsertPt = StoreInstr ? StoreInstr : MBBI;
1230  // Allocate StackSize bytes.
1231  int64_t Delta = -int64_t(StackSize);
1232 
1233  // In case the STM(G) instruction also stores SP (R4), but the displacement
1234  // is too large, the SP register is manipulated first before storing,
1235  // resulting in the wrong value stored and retrieved later. In this case, we
1236  // need to temporarily save the value of SP, and store it later to memory.
1237  if (StoreInstr && HasFP) {
1238  // Insert LR r0,r4 before STMG instruction.
1239  BuildMI(MBB, InsertPt, DL, ZII->get(SystemZ::LGR))
1240  .addReg(SystemZ::R0D, RegState::Define)
1241  .addReg(SystemZ::R4D);
1242  // Insert ST r0,xxx(,r4) after STMG instruction.
1243  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
1244  .addReg(SystemZ::R0D, RegState::Kill)
1245  .addReg(SystemZ::R4D)
1246  .addImm(Offset)
1247  .addReg(0);
1248  }
1249 
1250  emitIncrement(MBB, InsertPt, DL, Regs.getStackPointerRegister(), Delta,
1251  ZII);
1252 
1253  // If the requested stack size is larger than the guard page, then we need
1254  // to check if we need to call the stack extender. This requires adding a
1255  // conditional branch, but splitting the prologue block is not possible at
1256  // this point since it would invalidate the SaveBlocks / RestoreBlocks sets
1257  // of PEI in the single block function case. Build a pseudo to be handled
1258  // later by inlineStackProbe().
1259  const uint64_t GuardPageSize = 1024 * 1024;
1260  if (StackSize > GuardPageSize) {
1261  assert(StoreInstr && "Wrong insertion point");
1262  BuildMI(MBB, InsertPt, DL, ZII->get(SystemZ::XPLINK_STACKALLOC));
1263  }
1264  }
1265 
1266  if (HasFP) {
1267  // Copy the base of the frame to Frame Pointer Register.
1268  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR),
1269  Regs.getFramePointerRegister())
1270  .addReg(Regs.getStackPointerRegister());
1271 
1272  // Mark the FramePtr as live at the beginning of every block except
1273  // the entry block. (We'll have marked R8 as live on entry when
1274  // saving the GPRs.)
1275  for (MachineBasicBlock &B : llvm::drop_begin(MF))
1276  B.addLiveIn(Regs.getFramePointerRegister());
1277  }
1278 }
1279 
1281  MachineBasicBlock &MBB) const {
1282  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
1285  MachineFrameInfo &MFFrame = MF.getFrameInfo();
1286  auto *ZII = static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
1287  auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
1288 
1289  // Skip the return instruction.
1290  assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
1291 
1292  uint64_t StackSize = MFFrame.getStackSize();
1293  if (StackSize) {
1294  unsigned SPReg = Regs.getStackPointerRegister();
1295  if (ZFI->getRestoreGPRRegs().LowGPR != SPReg) {
1296  DebugLoc DL = MBBI->getDebugLoc();
1297  emitIncrement(MBB, MBBI, DL, SPReg, StackSize, ZII);
1298  }
1299  }
1300 }
1301 
1302 // Emit a compare of the stack pointer against the stack floor, and a call to
1303 // the LE stack extender if needed.
1305  MachineFunction &MF, MachineBasicBlock &PrologMBB) const {
1306  auto *ZII =
1307  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
1308 
1309  MachineInstr *StackAllocMI = nullptr;
1310  for (MachineInstr &MI : PrologMBB)
1311  if (MI.getOpcode() == SystemZ::XPLINK_STACKALLOC) {
1312  StackAllocMI = &MI;
1313  break;
1314  }
1315  if (StackAllocMI == nullptr)
1316  return;
1317 
1318  MachineBasicBlock &MBB = PrologMBB;
1319  const DebugLoc DL = StackAllocMI->getDebugLoc();
1320 
1321  // The 2nd half of block MBB after split.
1322  MachineBasicBlock *NextMBB;
1323 
1324  // Add new basic block for the call to the stack overflow function.
1325  MachineBasicBlock *StackExtMBB =
1327  MF.push_back(StackExtMBB);
1328 
1329  // LG r3,72(,r3)
1330  BuildMI(StackExtMBB, DL, ZII->get(SystemZ::LG), SystemZ::R3D)
1331  .addReg(SystemZ::R3D)
1332  .addImm(72)
1333  .addReg(0);
1334  // BASR r3,r3
1335  BuildMI(StackExtMBB, DL, ZII->get(SystemZ::CallBASR_STACKEXT))
1336  .addReg(SystemZ::R3D);
1337 
1338  // LLGT r3,1208
1339  BuildMI(MBB, StackAllocMI, DL, ZII->get(SystemZ::LLGT), SystemZ::R3D)
1340  .addReg(0)
1341  .addImm(1208)
1342  .addReg(0);
1343  // CG r4,64(,r3)
1344  BuildMI(MBB, StackAllocMI, DL, ZII->get(SystemZ::CG))
1345  .addReg(SystemZ::R4D)
1346  .addReg(SystemZ::R3D)
1347  .addImm(64)
1348  .addReg(0);
1349  // JLL b'0100',F'37'
1350  BuildMI(MBB, StackAllocMI, DL, ZII->get(SystemZ::BRC))
1353  .addMBB(StackExtMBB);
1354 
1355  NextMBB = SystemZ::splitBlockBefore(StackAllocMI, &MBB);
1356  MBB.addSuccessor(NextMBB);
1357  MBB.addSuccessor(StackExtMBB);
1358 
1359  // Add jump back from stack extension BB.
1360  BuildMI(StackExtMBB, DL, ZII->get(SystemZ::J)).addMBB(NextMBB);
1361  StackExtMBB->addSuccessor(NextMBB);
1362 
1363  StackAllocMI->eraseFromParent();
1364 
1365  // Compute the live-in lists for the new blocks.
1366  recomputeLiveIns(*NextMBB);
1367  recomputeLiveIns(*StackExtMBB);
1368 }
1369 
1371  return (MF.getFrameInfo().hasVarSizedObjects());
1372 }
1373 
1375  MachineFunction &MF, RegScavenger *RS) const {
1376  MachineFrameInfo &MFFrame = MF.getFrameInfo();
1377  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
1378  auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
1379 
1380  // Setup stack frame offset
1381  MFFrame.setOffsetAdjustment(Regs.getStackPointerBias());
1382 }
1383 
1384 // Determines the size of the frame, and creates the deferred spill objects.
1386  MachineFunction &MF) const {
1387  MachineFrameInfo &MFFrame = MF.getFrameInfo();
1388  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
1389  auto *Regs =
1390  static_cast<SystemZXPLINK64Registers *>(Subtarget.getSpecialRegisters());
1391 
1392  uint64_t StackSize = MFFrame.getStackSize();
1393  if (StackSize == 0)
1394  return;
1395 
1396  // Add the size of the register save area and the reserved area to the size.
1397  StackSize += Regs->getCallFrameSize();
1398  MFFrame.setStackSize(StackSize);
1399 
1400  // We now know the stack size. Create the fixed spill stack objects for the
1401  // register save area now. This has no impact on the stack frame layout, as
1402  // this is already computed. However, it makes sure that all callee saved
1403  // registers have a valid frame index assigned.
1404  const unsigned RegSize = MF.getDataLayout().getPointerSize();
1405  for (auto &CS : MFFrame.getCalleeSavedInfo()) {
1406  int Offset = RegSpillOffsets[CS.getReg()];
1407  if (Offset >= 0)
1408  CS.setFrameIdx(
1409  MFFrame.CreateFixedSpillStackObject(RegSize, Offset - StackSize));
1410  }
1411 }
i
i
Definition: README.txt:29
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
SystemZInstrBuilder.h
llvm::SystemZSubtarget::getTargetLowering
const SystemZTargetLowering * getTargetLowering() const override
Definition: SystemZSubtarget.h:117
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:387
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:591
llvm::SystemZMachineFunctionInfo::getFramePointerSaveIndex
int getFramePointerSaveIndex() const
Definition: SystemZMachineFunctionInfo.h:88
llvm::SystemZXPLINKFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: SystemZFrameLowering.cpp:1052
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:143
llvm::SystemZXPLINKFrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: SystemZFrameLowering.cpp:1067
llvm::SystemZELFFrameLowering::inlineStackProbe
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
Definition: SystemZFrameLowering.cpp:747
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:124
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:450
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::SystemZELFFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: SystemZFrameLowering.cpp:441
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SystemZTargetLowering
Definition: SystemZISelLowering.h:386
emitIncrement
static void emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, Register Reg, int64_t NumBytes, const TargetInstrInfo *TII)
Definition: SystemZFrameLowering.cpp:485
llvm::SmallVector< unsigned, 8 >
llvm::SystemZ::emitBlockAfter
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1921
llvm::SystemZFrameLowering::create
static std::unique_ptr< SystemZFrameLowering > create(const SystemZSubtarget &STI)
Definition: SystemZFrameLowering.cpp:62
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::recomputeLiveIns
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
Definition: LivePhysRegs.h:198
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SystemZ::CCMASK_CMP_LT
const unsigned CCMASK_CMP_LT
Definition: SystemZ.h:36
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::AArch64ISD::STG
@ STG
Definition: AArch64ISelLowering.h:462
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::SystemZXPLINKFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: SystemZFrameLowering.cpp:1374
llvm::SystemZFrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: SystemZFrameLowering.cpp:165
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:588
llvm::SystemZ::splitBlockBefore
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1937
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SystemZELFFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: SystemZFrameLowering.cpp:241
llvm::SystemZMachineFunctionInfo::getVarArgsFirstGPR
Register getVarArgsFirstGPR() const
Definition: SystemZMachineFunctionInfo.h:71
llvm::SystemZELFFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: SystemZFrameLowering.cpp:538
SystemZCallingConv.h
llvm::SystemZELFFrameLowering::usePackedStack
bool usePackedStack(MachineFunction &MF) const
Definition: SystemZFrameLowering.cpp:891
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::SystemZInstrInfo
Definition: SystemZInstrInfo.h:174
llvm::SystemZSubtarget::isTargetXPLINK64
bool isTargetXPLINK64() const
Definition: SystemZSubtarget.h:301
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:410
llvm::SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBII, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: SystemZFrameLowering.cpp:1128
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:330
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SystemZXPLINK64Registers
XPLINK64 calling convention specific use registers Particular to z/OS when in 64 bit mode.
Definition: SystemZRegisterInfo.h:82
llvm::SystemZ::GPRRegs
Definition: SystemZMachineFunctionInfo.h:19
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::SystemZMachineFunctionInfo::setRestoreGPRRegs
void setRestoreGPRRegs(Register Low, Register High, unsigned Offs)
Definition: SystemZMachineFunctionInfo.h:63
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:548
MachineRegisterInfo.h
llvm::TargetFrameLowering::StackDirection
StackDirection
Definition: TargetFrameLowering.h:45
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
llvm::SystemZFrameLowering::SystemZFrameLowering
SystemZFrameLowering(StackDirection D, Align StackAl, int LAO, Align TransAl, bool StackReal)
Definition: SystemZFrameLowering.cpp:56
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:534
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SystemZ::GPRRegs::GPROffset
unsigned GPROffset
Definition: SystemZMachineFunctionInfo.h:22
llvm::SystemZELFFrameLowering::getBackchainOffset
unsigned getBackchainOffset(MachineFunction &MF) const
Definition: SystemZFrameLowering.h:92
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:28
SystemZInstrInfo.h
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static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:74
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
llvm::BitVector
Definition: BitVector.h:75
llvm::SystemZFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: SystemZFrameLowering.cpp:68
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::SystemZMachineFunctionInfo::getRestoreGPRRegs
SystemZ::GPRRegs getRestoreGPRRegs() const
Definition: SystemZMachineFunctionInfo.h:62
llvm::SystemZMachineFunctionInfo::setSpillGPRRegs
void setSpillGPRRegs(Register Low, Register High, unsigned Offs)
Definition: SystemZMachineFunctionInfo.h:53
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SystemZ::CCMASK_CMP_GT
const unsigned CCMASK_CMP_GT
Definition: SystemZ.h:37
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:407
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:541
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFrameInfo::isDeadObjectIndex
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
Definition: MachineFrameInfo.h:745
llvm::SystemZ::ELFArgGPRs
const MCPhysReg ELFArgGPRs[ELFNumArgGPRs]
Definition: SystemZCallingConv.cpp:14
llvm::SystemZELFFrameLowering::orderFrameObjects
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack frame.
Definition: SystemZFrameLowering.cpp:96
llvm::SystemZELFFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: SystemZFrameLowering.cpp:847
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:23
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:608
buildDefCFAReg
static void buildDefCFAReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Reg, const SystemZInstrInfo *ZII)
Definition: SystemZFrameLowering.cpp:524
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::MachineFunction::push_back
void push_back(MachineBasicBlock *MBB)
Definition: MachineFunction.h:871
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:286
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::SystemZMC::ELFCFAOffsetFromInitialSP
const int64_t ELFCFAOffsetFromInitialSP
Definition: SystemZMCTargetDesc.h:34
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
SystemZMachineFunctionInfo.h
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::SystemZXPLINKFrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: SystemZFrameLowering.cpp:1280
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::SystemZELFFrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: SystemZFrameLowering.cpp:175
llvm::SystemZ::CCMASK_ICMP
const unsigned CCMASK_ICMP
Definition: SystemZ.h:47
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:956
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
addSavedGPR
static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, unsigned GPR64, bool IsImplicit)
Definition: SystemZFrameLowering.cpp:312
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:117
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::SystemZELFFrameLowering::getRegSpillOffset
unsigned getRegSpillOffset(MachineFunction &MF, Register Reg) const
Definition: SystemZFrameLowering.cpp:861
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:143
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineFunction::getLandingPads
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
Definition: MachineFunction.h:1111
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::MachineFunction
Definition: MachineFunction.h:257
SystemZSubtarget.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::IndexedMap::grow
void grow(IndexT n)
Definition: IndexedMap.h:68
isXPLeafCandidate
static bool isXPLeafCandidate(const MachineFunction &MF)
Definition: SystemZFrameLowering.cpp:914
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:736
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:1001
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::TargetStackID::NoAlloc
@ NoAlloc
Definition: TargetFrameLowering.h:32
llvm::SystemZ::GPRRegs::LowGPR
unsigned LowGPR
Definition: SystemZMachineFunctionInfo.h:20
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::SystemZELFFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: SystemZFrameLowering.cpp:852
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZXPLINKFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: SystemZFrameLowering.cpp:1189
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZELFFrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: SystemZFrameLowering.cpp:701
llvm::MachineFunction::addFrameInst
unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:613
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SystemZMachineFunctionInfo
Definition: SystemZMachineFunctionInfo.h:27
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::stable_sort
void stable_sort(R &&Range)
Definition: STLExtras.h:1947
llvm::SystemZELFFrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: SystemZFrameLowering.cpp:325
llvm::CallingConv::GHC
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::TargetFrameLowering::getFrameIndexReference
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: TargetFrameLoweringImpl.cpp:50
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::SystemZXPLINKFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: SystemZFrameLowering.cpp:1370
Function.h
llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBII, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: SystemZFrameLowering.cpp:385
llvm::SystemZSubtarget::getInstrInfo
const SystemZInstrInfo * getInstrInfo() const override
Definition: SystemZSubtarget.h:113
llvm::SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: SystemZFrameLowering.cpp:961
llvm::SystemZMachineFunctionInfo::getSpillGPRRegs
SystemZ::GPRRegs getSpillGPRRegs() const
Definition: SystemZMachineFunctionInfo.h:52
SystemZFrameLowering.h
llvm::MachineRegisterInfo::isPhysRegModified
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
Definition: MachineRegisterInfo.cpp:572
llvm::SystemZFrameLowering
Definition: SystemZFrameLowering.h:22
llvm::SystemZXPLINKFrameLowering::inlineStackProbe
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
Definition: SystemZFrameLowering.cpp:1304
llvm::SystemZELFFrameLowering::getOrCreateFramePointerSaveIndex
int getOrCreateFramePointerSaveIndex(MachineFunction &MF) const
Definition: SystemZFrameLowering.cpp:878
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:188
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
SystemZRegisterInfo.h
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:99
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
buildCFAOffs
static void buildCFAOffs(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, int Offset, const SystemZInstrInfo *ZII)
Definition: SystemZFrameLowering.cpp:513
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::SystemZXPLINKFrameLowering::determineFrameLayout
void determineFrameLayout(MachineFunction &MF) const
Definition: SystemZFrameLowering.cpp:1385
llvm::SmallVectorImpl< int >
llvm::SystemZELFFrameLowering::SystemZELFFrameLowering
SystemZELFFrameLowering()
Definition: SystemZFrameLowering.cpp:290
llvm::TargetLoweringBase::hasInlineStackProbe
virtual bool hasInlineStackProbe(const MachineFunction &MF) const
Definition: TargetLowering.h:1917
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1142
llvm::MachineFrameInfo::setOffsetAdjustment
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
Definition: MachineFrameInfo.h:597
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:572
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:83
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::adjustsStack
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Definition: MachineFrameInfo.h:609
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
llvm::SystemZII::Has20BitOffset
@ Has20BitOffset
Definition: SystemZInstrInfo.h:38
RegisterScavenging.h
llvm::SystemZXPLINKFrameLowering::SystemZXPLINKFrameLowering
SystemZXPLINKFrameLowering()
Definition: SystemZFrameLowering.cpp:901
llvm::SystemZ::GPRRegs::HighGPR
unsigned HighGPR
Definition: SystemZMachineFunctionInfo.h:21
llvm::SystemZSubtarget::getSpecialRegisters
SystemZCallingConventionRegisters * getSpecialRegisters() const
Definition: SystemZSubtarget.h:96
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:692
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:543
llvm::TargetFrameLowering::SpillSlot
Definition: TargetFrameLowering.h:51
llvm::SystemZ::ELFNumArgGPRs
const unsigned ELFNumArgGPRs
Definition: SystemZCallingConv.h:19
llvm::SystemZMachineFunctionInfo::setFramePointerSaveIndex
void setFramePointerSaveIndex(int Idx)
Definition: SystemZMachineFunctionInfo.h:89
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:708
llvm::SystemZMC::ELFCallFrameSize
const int64_t ELFCallFrameSize
Definition: SystemZMCTargetDesc.h:31
LivePhysRegs.h