LLVM  15.0.0git
PPCRegisterInfo.cpp
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1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCRegisterInfo.h"
15 #include "PPCFrameLowering.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/Type.h"
37 #include "llvm/Support/Debug.h"
43 #include <cstdlib>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "reginfo"
48 
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
51 
52 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
53 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
54 
55 static cl::opt<bool>
56 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
57  cl::desc("Enable use of a base pointer for complex stack frames"));
58 
59 static cl::opt<bool>
60 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
61  cl::desc("Force the use of a base pointer in every function"));
62 
63 static cl::opt<bool>
64 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
65  cl::desc("Enable spills from gpr to vsr rather than stack"));
66 
67 static cl::opt<bool>
68 StackPtrConst("ppc-stack-ptr-caller-preserved",
69  cl::desc("Consider R1 caller preserved so stack saves of "
70  "caller preserved registers can be LICM candidates"),
71  cl::init(true), cl::Hidden);
72 
73 static cl::opt<unsigned>
74 MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
75  cl::desc("Maximum search distance for definition of CR bit "
76  "spill on ppc"),
77  cl::Hidden, cl::init(100));
78 
79 // Copies/moves of physical accumulators are expensive operations
80 // that should be avoided whenever possible. MMA instructions are
81 // meant to be used in performance-sensitive computational kernels.
82 // This option is provided, at least for the time being, to give the
83 // user a tool to detect this expensive operation and either rework
84 // their code or report a compiler bug if that turns out to be the
85 // cause.
86 #ifndef NDEBUG
87 static cl::opt<bool>
88 ReportAccMoves("ppc-report-acc-moves",
89  cl::desc("Emit information about accumulator register spills "
90  "and copies"),
91  cl::Hidden, cl::init(false));
92 #endif
93 
94 static unsigned offsetMinAlignForOpcode(unsigned OpC);
95 
97  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
98  TM.isPPC64() ? 0 : 1,
99  TM.isPPC64() ? 0 : 1),
100  TM(TM) {
101  ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
102  ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
103  ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
104  ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
105  ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
106  ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
107  ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
108  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
109  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
110 
111  // 64-bit
112  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
113  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
114  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
115  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
116  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
117 
118  // VSX
119  ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
120  ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
121  ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
122  ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
123  ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
124  ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
125  ImmToIdxMap[PPC::LXV] = PPC::LXVX;
126  ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
127  ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
128  ImmToIdxMap[PPC::STXV] = PPC::STXVX;
129  ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
130  ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
131 
132  // SPE
133  ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
134  ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
135  ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
136  ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
137 
138  // Power10
139  ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8;
140  ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8;
141  ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8;
142  ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8;
143  ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX;
144  ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX;
145 
146  ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8;
147  ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8;
148  ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8;
149 
150  ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX;
151  ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX;
152  ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX;
153  ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX;
154  ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX;
155 
156  ImmToIdxMap[PPC::LXVP] = PPC::LXVPX;
157  ImmToIdxMap[PPC::STXVP] = PPC::STXVPX;
158  ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX;
159  ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX;
160 }
161 
162 /// getPointerRegClass - Return the register class to use to hold pointers.
163 /// This is used for addressing modes.
164 const TargetRegisterClass *
166  const {
167  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
168  // when it checks for ZERO folding.
169  if (Kind == 1) {
170  if (TM.isPPC64())
171  return &PPC::G8RC_NOX0RegClass;
172  return &PPC::GPRC_NOR0RegClass;
173  }
174 
175  if (TM.isPPC64())
176  return &PPC::G8RCRegClass;
177  return &PPC::GPRCRegClass;
178 }
179 
180 const MCPhysReg*
182  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
184  if (!TM.isPPC64() && Subtarget.isAIXABI())
185  report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
186  if (Subtarget.hasVSX()) {
187  if (Subtarget.pairedVectorMemops())
188  return CSR_64_AllRegs_VSRP_SaveList;
189  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
190  return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
191  return CSR_64_AllRegs_VSX_SaveList;
192  }
193  if (Subtarget.hasAltivec()) {
194  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
195  return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList;
196  return CSR_64_AllRegs_Altivec_SaveList;
197  }
198  return CSR_64_AllRegs_SaveList;
199  }
200 
201  // On PPC64, we might need to save r2 (but only if it is not reserved).
202  // We do not need to treat R2 as callee-saved when using PC-Relative calls
203  // because any direct uses of R2 will cause it to be reserved. If the function
204  // is a leaf or the only uses of R2 are implicit uses for calls, the calls
205  // will use the @notoc relocation which will cause this function to set the
206  // st_other bit to 1, thereby communicating to its caller that it arbitrarily
207  // clobbers the TOC.
208  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) &&
209  !Subtarget.isUsingPCRelativeCalls();
210 
211  // Cold calling convention CSRs.
213  if (Subtarget.isAIXABI())
214  report_fatal_error("Cold calling unimplemented on AIX.");
215  if (TM.isPPC64()) {
216  if (Subtarget.pairedVectorMemops())
217  return SaveR2 ? CSR_SVR64_ColdCC_R2_VSRP_SaveList
218  : CSR_SVR64_ColdCC_VSRP_SaveList;
219  if (Subtarget.hasAltivec())
220  return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
221  : CSR_SVR64_ColdCC_Altivec_SaveList;
222  return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
223  : CSR_SVR64_ColdCC_SaveList;
224  }
225  // 32-bit targets.
226  if (Subtarget.pairedVectorMemops())
227  return CSR_SVR32_ColdCC_VSRP_SaveList;
228  else if (Subtarget.hasAltivec())
229  return CSR_SVR32_ColdCC_Altivec_SaveList;
230  else if (Subtarget.hasSPE())
231  return CSR_SVR32_ColdCC_SPE_SaveList;
232  return CSR_SVR32_ColdCC_SaveList;
233  }
234  // Standard calling convention CSRs.
235  if (TM.isPPC64()) {
236  if (Subtarget.pairedVectorMemops())
237  return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
238  if (Subtarget.hasAltivec() &&
239  (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
240  return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
241  : CSR_PPC64_Altivec_SaveList;
242  }
243  return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
244  }
245  // 32-bit targets.
246  if (Subtarget.isAIXABI()) {
247  if (Subtarget.hasAltivec())
248  return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
249  : CSR_AIX32_SaveList;
250  return CSR_AIX32_SaveList;
251  }
252  if (Subtarget.pairedVectorMemops())
253  return CSR_SVR432_VSRP_SaveList;
254  if (Subtarget.hasAltivec())
255  return CSR_SVR432_Altivec_SaveList;
256  else if (Subtarget.hasSPE())
257  return CSR_SVR432_SPE_SaveList;
258  return CSR_SVR432_SaveList;
259 }
260 
261 const uint32_t *
263  CallingConv::ID CC) const {
264  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
265  if (CC == CallingConv::AnyReg) {
266  if (Subtarget.hasVSX()) {
267  if (Subtarget.pairedVectorMemops())
268  return CSR_64_AllRegs_VSRP_RegMask;
269  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
270  return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
271  return CSR_64_AllRegs_VSX_RegMask;
272  }
273  if (Subtarget.hasAltivec()) {
274  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
275  return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask;
276  return CSR_64_AllRegs_Altivec_RegMask;
277  }
278  return CSR_64_AllRegs_RegMask;
279  }
280 
281  if (Subtarget.isAIXABI()) {
282  return TM.isPPC64()
283  ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
284  ? CSR_PPC64_Altivec_RegMask
285  : CSR_PPC64_RegMask)
286  : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
287  ? CSR_AIX32_Altivec_RegMask
288  : CSR_AIX32_RegMask);
289  }
290 
291  if (CC == CallingConv::Cold) {
292  if (TM.isPPC64())
293  return Subtarget.pairedVectorMemops()
294  ? CSR_SVR64_ColdCC_VSRP_RegMask
295  : (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
296  : CSR_SVR64_ColdCC_RegMask);
297  else
298  return Subtarget.pairedVectorMemops()
299  ? CSR_SVR32_ColdCC_VSRP_RegMask
300  : (Subtarget.hasAltivec()
301  ? CSR_SVR32_ColdCC_Altivec_RegMask
302  : (Subtarget.hasSPE() ? CSR_SVR32_ColdCC_SPE_RegMask
303  : CSR_SVR32_ColdCC_RegMask));
304  }
305 
306  if (TM.isPPC64())
307  return Subtarget.pairedVectorMemops()
308  ? CSR_SVR464_VSRP_RegMask
309  : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
310  : CSR_PPC64_RegMask);
311  else
312  return Subtarget.pairedVectorMemops()
313  ? CSR_SVR432_VSRP_RegMask
314  : (Subtarget.hasAltivec()
315  ? CSR_SVR432_Altivec_RegMask
316  : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
317  : CSR_SVR432_RegMask));
318 }
319 
320 const uint32_t*
322  return CSR_NoRegs_RegMask;
323 }
324 
326  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
327  Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
328 }
329 
331  BitVector Reserved(getNumRegs());
332  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
333  const PPCFrameLowering *TFI = getFrameLowering(MF);
334 
335  // The ZERO register is not really a register, but the representation of r0
336  // when used in instructions that treat r0 as the constant 0.
337  markSuperRegs(Reserved, PPC::ZERO);
338 
339  // The FP register is also not really a register, but is the representation
340  // of the frame pointer register used by ISD::FRAMEADDR.
341  markSuperRegs(Reserved, PPC::FP);
342 
343  // The BP register is also not really a register, but is the representation
344  // of the base pointer register used by setjmp.
345  markSuperRegs(Reserved, PPC::BP);
346 
347  // The counter registers must be reserved so that counter-based loops can
348  // be correctly formed (and the mtctr instructions are not DCE'd).
349  markSuperRegs(Reserved, PPC::CTR);
350  markSuperRegs(Reserved, PPC::CTR8);
351 
352  markSuperRegs(Reserved, PPC::R1);
353  markSuperRegs(Reserved, PPC::LR);
354  markSuperRegs(Reserved, PPC::LR8);
355  markSuperRegs(Reserved, PPC::RM);
356 
357  markSuperRegs(Reserved, PPC::VRSAVE);
358 
359  // The SVR4 ABI reserves r2 and r13
360  if (Subtarget.isSVR4ABI()) {
361  // We only reserve r2 if we need to use the TOC pointer. If we have no
362  // explicit uses of the TOC pointer (meaning we're a leaf function with
363  // no constant-pool loads, etc.) and we have no potential uses inside an
364  // inline asm block, then we can treat r2 has an ordinary callee-saved
365  // register.
366  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
367  if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
368  markSuperRegs(Reserved, PPC::R2); // System-reserved register
369  markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
370  }
371 
372  // Always reserve r2 on AIX for now.
373  // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
374  if (Subtarget.isAIXABI())
375  markSuperRegs(Reserved, PPC::R2); // System-reserved register
376 
377  // On PPC64, r13 is the thread pointer. Never allocate this register.
378  if (TM.isPPC64())
379  markSuperRegs(Reserved, PPC::R13);
380 
381  if (TFI->needsFP(MF))
382  markSuperRegs(Reserved, PPC::R31);
383 
384  bool IsPositionIndependent = TM.isPositionIndependent();
385  if (hasBasePointer(MF)) {
386  if (Subtarget.is32BitELFABI() && IsPositionIndependent)
387  markSuperRegs(Reserved, PPC::R29);
388  else
389  markSuperRegs(Reserved, PPC::R30);
390  }
391 
392  if (Subtarget.is32BitELFABI() && IsPositionIndependent)
393  markSuperRegs(Reserved, PPC::R30);
394 
395  // Reserve Altivec registers when Altivec is unavailable.
396  if (!Subtarget.hasAltivec())
397  for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
398  IE = PPC::VRRCRegClass.end(); I != IE; ++I)
399  markSuperRegs(Reserved, *I);
400 
401  if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
402  !TM.getAIXExtendedAltivecABI()) {
403  // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved
404  // and cannot be used.
405  for (auto Reg : CSR_Altivec_SaveList) {
406  if (Reg == 0)
407  break;
408  markSuperRegs(Reserved, Reg);
409  for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) {
410  Reserved.set(*AS);
411  }
412  }
413  }
414 
415  assert(checkAllSuperRegsMarked(Reserved));
416  return Reserved;
417 }
418 
420  MCRegister PhysReg) const {
421  // We cannot use getReservedRegs() to find the registers that are not asm
422  // clobberable because there are some reserved registers which can be
423  // clobbered by inline asm. For example, when LR is clobbered, the register is
424  // saved and restored. We will hardcode the registers that are not asm
425  // cloberable in this function.
426 
427  // The stack pointer (R1/X1) is not clobberable by inline asm
428  return PhysReg != PPC::R1 && PhysReg != PPC::X1;
429 }
430 
432  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
433  const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo();
434  const MachineFrameInfo &MFI = MF.getFrameInfo();
435  const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
436 
437  LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName()
438  << ".\n");
439  // If the callee saved info is invalid we have to default to true for safety.
440  if (!MFI.isCalleeSavedInfoValid()) {
441  LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n");
442  return true;
443  }
444 
445  // We will require the use of X-Forms because the frame is larger than what
446  // can be represented in signed 16 bits that fit in the immediate of a D-Form.
447  // If we need an X-Form then we need a register to store the address offset.
448  unsigned FrameSize = MFI.getStackSize();
449  // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
450  if (FrameSize & ~0x7FFF) {
451  LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n");
452  return true;
453  }
454 
455  // The callee saved info is valid so it can be traversed.
456  // Checking for registers that need saving that do not have load or store
457  // forms where the address offset is an immediate.
458  for (unsigned i = 0; i < Info.size(); i++) {
459  // If the spill is to a register no scavenging is required.
460  if (Info[i].isSpilledToReg())
461  continue;
462 
463  int FrIdx = Info[i].getFrameIdx();
464  Register Reg = Info[i].getReg();
465 
466  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
467  unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC);
468  if (!MFI.isFixedObjectIndex(FrIdx)) {
469  // This is not a fixed object. If it requires alignment then we may still
470  // need to use the XForm.
471  if (offsetMinAlignForOpcode(Opcode) > 1) {
472  LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
473  << " for register " << printReg(Reg, this) << ".\n");
474  LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires "
475  << "alignment.\n");
476  return true;
477  }
478  }
479 
480  // This is eiher:
481  // 1) A fixed frame index object which we know are aligned so
482  // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
483  // need to consider the alignment here.
484  // 2) A not fixed object but in that case we now know that the min required
485  // alignment is no more than 1 based on the previous check.
486  if (InstrInfo->isXFormMemOp(Opcode)) {
487  LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
488  << " for register " << printReg(Reg, this) << ".\n");
489  LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n");
490  return true;
491  }
492  }
493  LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n");
494  return false;
495 }
496 
498  const MachineFunction &MF) const {
499  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
500  // Do not use virtual base registers when ROP protection is turned on.
501  // Virtual base registers break the layout of the local variable space and may
502  // push the ROP Hash location past the 512 byte range of the ROP store
503  // instruction.
504  return !Subtarget.hasROPProtect();
505 }
506 
508  const MachineFunction &MF) const {
510  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
511  const MachineFrameInfo &MFI = MF.getFrameInfo();
512 
513  if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
514  return false;
515  if (PhysReg == Subtarget.getTOCPointerRegister())
516  // X2/R2 is guaranteed to be preserved within a function if it is reserved.
517  // The reason it's reserved is that it's the TOC pointer (and the function
518  // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
519  // with no TOC access), we can't claim that it is preserved.
520  return (getReservedRegs(MF).test(PhysReg));
521  if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
522  !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
523  // The value of the stack pointer does not change within a function after
524  // the prologue and before the epilogue if there are no dynamic allocations
525  // and no inline asm which clobbers X1/R1.
526  return true;
527  return false;
528 }
529 
531  ArrayRef<MCPhysReg> Order,
533  const MachineFunction &MF,
534  const VirtRegMap *VRM,
535  const LiveRegMatrix *Matrix) const {
536  const MachineRegisterInfo *MRI = &MF.getRegInfo();
537 
538  // Call the base implementation first to set any hints based on the usual
539  // heuristics and decide what the return value should be. We want to return
540  // the same value returned by the base implementation. If the base
541  // implementation decides to return true and force the allocation then we
542  // will leave it as such. On the other hand if the base implementation
543  // decides to return false the following code will not force the allocation
544  // as we are just looking to provide a hint.
545  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
546  VirtReg, Order, Hints, MF, VRM, Matrix);
547  // We are interested in instructions that copy values to ACC/UACC.
548  // The copy into UACC will be simply a COPY to a subreg so we
549  // want to allocate the corresponding physical subreg for the source.
550  // The copy into ACC will be a BUILD_UACC so we want to allocate
551  // the same number UACC for the source.
552  for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
553  const MachineOperand *ResultOp = nullptr;
554  Register ResultReg;
555  switch (Use.getOpcode()) {
556  case TargetOpcode::COPY: {
557  ResultOp = &Use.getOperand(0);
558  ResultReg = ResultOp->getReg();
559  if (Register::isVirtualRegister(ResultReg) &&
560  MRI->getRegClass(ResultReg)->contains(PPC::UACC0) &&
561  VRM->hasPhys(ResultReg)) {
562  Register UACCPhys = VRM->getPhys(ResultReg);
563  Register HintReg = getSubReg(UACCPhys, ResultOp->getSubReg());
564  // Ensure that the hint is a VSRp register.
565  if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
566  Hints.push_back(HintReg);
567  }
568  break;
569  }
570  case PPC::BUILD_UACC: {
571  ResultOp = &Use.getOperand(0);
572  ResultReg = ResultOp->getReg();
573  if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) &&
574  VRM->hasPhys(ResultReg)) {
575  Register ACCPhys = VRM->getPhys(ResultReg);
576  assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) &&
577  "Expecting an ACC register for BUILD_UACC.");
578  Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0);
579  Hints.push_back(HintReg);
580  }
581  break;
582  }
583  }
584  }
585  return BaseImplRetVal;
586 }
587 
589  MachineFunction &MF) const {
590  const PPCFrameLowering *TFI = getFrameLowering(MF);
591  const unsigned DefaultSafety = 1;
592 
593  switch (RC->getID()) {
594  default:
595  return 0;
596  case PPC::G8RC_NOX0RegClassID:
597  case PPC::GPRC_NOR0RegClassID:
598  case PPC::SPERCRegClassID:
599  case PPC::G8RCRegClassID:
600  case PPC::GPRCRegClassID: {
601  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
602  return 32 - FP - DefaultSafety;
603  }
604  case PPC::F4RCRegClassID:
605  case PPC::F8RCRegClassID:
606  case PPC::VSLRCRegClassID:
607  return 32 - DefaultSafety;
608  case PPC::VFRCRegClassID:
609  case PPC::VRRCRegClassID: {
610  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
611  // Vector registers VR20-VR31 are reserved and cannot be used in the default
612  // Altivec ABI on AIX.
613  if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
614  return 20 - DefaultSafety;
615  }
616  return 32 - DefaultSafety;
617  case PPC::VSFRCRegClassID:
618  case PPC::VSSRCRegClassID:
619  case PPC::VSRCRegClassID: {
620  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
621  if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
622  // Vector registers VR20-VR31 are reserved and cannot be used in the
623  // default Altivec ABI on AIX.
624  return 52 - DefaultSafety;
625  }
626  return 64 - DefaultSafety;
627  case PPC::CRRCRegClassID:
628  return 8 - DefaultSafety;
629  }
630 }
631 
632 const TargetRegisterClass *
634  const MachineFunction &MF) const {
635  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
636  const auto *DefaultSuperclass =
638  if (Subtarget.hasVSX()) {
639  // With VSX, we can inflate various sub-register classes to the full VSX
640  // register set.
641 
642  // For Power9 we allow the user to enable GPR to vector spills.
643  // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
644  // support to spill GPRC.
645  if (TM.isELFv2ABI() || Subtarget.isAIXABI()) {
646  if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
647  RC == &PPC::G8RCRegClass) {
648  InflateGP8RC++;
649  return &PPC::SPILLTOVSRRCRegClass;
650  }
651  if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
652  InflateGPRC++;
653  }
654 
655  for (const auto *I = RC->getSuperClasses(); *I; ++I) {
656  if (getRegSizeInBits(**I) != getRegSizeInBits(*RC))
657  continue;
658 
659  switch ((*I)->getID()) {
660  case PPC::VSSRCRegClassID:
661  return Subtarget.hasP8Vector() ? *I : DefaultSuperclass;
662  case PPC::VSFRCRegClassID:
663  case PPC::VSRCRegClassID:
664  return *I;
665  case PPC::VSRpRCRegClassID:
666  return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass;
667  case PPC::ACCRCRegClassID:
668  case PPC::UACCRCRegClassID:
669  return Subtarget.hasMMA() ? *I : DefaultSuperclass;
670  }
671  }
672  }
673 
674  return DefaultSuperclass;
675 }
676 
677 //===----------------------------------------------------------------------===//
678 // Stack Frame Processing methods
679 //===----------------------------------------------------------------------===//
680 
681 /// lowerDynamicAlloc - Generate the code for allocating an object in the
682 /// current frame. The sequence of code will be in the general form
683 ///
684 /// addi R0, SP, \#frameSize ; get the address of the previous frame
685 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
686 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
687 ///
689  // Get the instruction.
690  MachineInstr &MI = *II;
691  // Get the instruction's basic block.
692  MachineBasicBlock &MBB = *MI.getParent();
693  // Get the basic block's function.
694  MachineFunction &MF = *MBB.getParent();
695  // Get the frame info.
696  MachineFrameInfo &MFI = MF.getFrameInfo();
697  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
698  // Get the instruction info.
699  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
700  // Determine whether 64-bit pointers are used.
701  bool LP64 = TM.isPPC64();
702  DebugLoc dl = MI.getDebugLoc();
703 
704  // Get the maximum call stack size.
705  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
706  Align MaxAlign = MFI.getMaxAlign();
707  assert(isAligned(MaxAlign, maxCallFrameSize) &&
708  "Maximum call-frame size not sufficiently aligned");
709  (void)MaxAlign;
710 
711  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
712  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
713  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
714  bool KillNegSizeReg = MI.getOperand(1).isKill();
715  Register NegSizeReg = MI.getOperand(1).getReg();
716 
717  prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, Reg);
718  // Grow the stack and update the stack pointer link, then determine the
719  // address of new allocated space.
720  if (LP64) {
721  BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
723  .addReg(PPC::X1)
724  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
725  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
726  .addReg(PPC::X1)
727  .addImm(maxCallFrameSize);
728  } else {
729  BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
731  .addReg(PPC::R1)
732  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
733  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
734  .addReg(PPC::R1)
735  .addImm(maxCallFrameSize);
736  }
737 
738  // Discard the DYNALLOC instruction.
739  MBB.erase(II);
740 }
741 
742 /// To accomplish dynamic stack allocation, we have to calculate exact size
743 /// subtracted from the stack pointer according alignment information and get
744 /// previous frame pointer.
746  Register &NegSizeReg,
747  bool &KillNegSizeReg,
748  Register &FramePointer) const {
749  // Get the instruction.
750  MachineInstr &MI = *II;
751  // Get the instruction's basic block.
752  MachineBasicBlock &MBB = *MI.getParent();
753  // Get the basic block's function.
754  MachineFunction &MF = *MBB.getParent();
755  // Get the frame info.
756  MachineFrameInfo &MFI = MF.getFrameInfo();
757  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
758  // Get the instruction info.
759  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
760  // Determine whether 64-bit pointers are used.
761  bool LP64 = TM.isPPC64();
762  DebugLoc dl = MI.getDebugLoc();
763  // Get the total frame size.
764  unsigned FrameSize = MFI.getStackSize();
765 
766  // Get stack alignments.
767  const PPCFrameLowering *TFI = getFrameLowering(MF);
768  Align TargetAlign = TFI->getStackAlign();
769  Align MaxAlign = MFI.getMaxAlign();
770 
771  // Determine the previous frame's address. If FrameSize can't be
772  // represented as 16 bits or we need special alignment, then we load the
773  // previous frame's address from 0(SP). Why not do an addis of the hi?
774  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
775  // Constructing the constant and adding would take 3 instructions.
776  // Fortunately, a frame greater than 32K is rare.
777  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
778  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
779 
780  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
781  if (LP64)
782  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer)
783  .addReg(PPC::X31)
784  .addImm(FrameSize);
785  else
786  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer)
787  .addReg(PPC::R31)
788  .addImm(FrameSize);
789  } else if (LP64) {
790  BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer)
791  .addImm(0)
792  .addReg(PPC::X1);
793  } else {
794  BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer)
795  .addImm(0)
796  .addReg(PPC::R1);
797  }
798  // Determine the actual NegSizeReg according to alignment info.
799  if (LP64) {
800  if (MaxAlign > TargetAlign) {
801  unsigned UnalNegSizeReg = NegSizeReg;
802  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
803 
804  // Unfortunately, there is no andi, only andi., and we can't insert that
805  // here because we might clobber cr0 while it is live.
806  BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
807  .addImm(~(MaxAlign.value() - 1));
808 
809  unsigned NegSizeReg1 = NegSizeReg;
810  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
811  BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
812  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
813  .addReg(NegSizeReg1, RegState::Kill);
814  KillNegSizeReg = true;
815  }
816  } else {
817  if (MaxAlign > TargetAlign) {
818  unsigned UnalNegSizeReg = NegSizeReg;
819  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
820 
821  // Unfortunately, there is no andi, only andi., and we can't insert that
822  // here because we might clobber cr0 while it is live.
823  BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
824  .addImm(~(MaxAlign.value() - 1));
825 
826  unsigned NegSizeReg1 = NegSizeReg;
827  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
828  BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
829  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
830  .addReg(NegSizeReg1, RegState::Kill);
831  KillNegSizeReg = true;
832  }
833  }
834 }
835 
837  MachineBasicBlock::iterator II) const {
838  MachineInstr &MI = *II;
839  // Get the instruction's basic block.
840  MachineBasicBlock &MBB = *MI.getParent();
841  // Get the basic block's function.
842  MachineFunction &MF = *MBB.getParent();
843  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
844  // Get the instruction info.
845  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
846  // Determine whether 64-bit pointers are used.
847  bool LP64 = TM.isPPC64();
848  DebugLoc dl = MI.getDebugLoc();
849  Register FramePointer = MI.getOperand(0).getReg();
850  const Register ActualNegSizeReg = MI.getOperand(1).getReg();
851  bool KillNegSizeReg = MI.getOperand(2).isKill();
852  Register NegSizeReg = MI.getOperand(2).getReg();
853  const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR);
854  // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg.
855  if (FramePointer == NegSizeReg) {
856  assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, "
857  "NegSizeReg should be killed");
858  // FramePointer is clobbered earlier than the use of NegSizeReg in
859  // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid
860  // misuse.
861  BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
862  .addReg(NegSizeReg)
863  .addReg(NegSizeReg);
864  NegSizeReg = ActualNegSizeReg;
865  KillNegSizeReg = false;
866  }
867  prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
868  // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign >
869  // TargetAlign.
870  if (NegSizeReg != ActualNegSizeReg)
871  BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
872  .addReg(NegSizeReg)
873  .addReg(NegSizeReg);
874  MBB.erase(II);
875 }
876 
878  MachineBasicBlock::iterator II) const {
879  // Get the instruction.
880  MachineInstr &MI = *II;
881  // Get the instruction's basic block.
882  MachineBasicBlock &MBB = *MI.getParent();
883  // Get the basic block's function.
884  MachineFunction &MF = *MBB.getParent();
885  // Get the frame info.
886  MachineFrameInfo &MFI = MF.getFrameInfo();
887  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
888  // Get the instruction info.
889  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
890 
891  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
892  bool is64Bit = TM.isPPC64();
893  DebugLoc dl = MI.getDebugLoc();
894  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
895  MI.getOperand(0).getReg())
896  .addImm(maxCallFrameSize);
897  MBB.erase(II);
898 }
899 
900 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
901 /// reserving a whole register (R0), we scrounge for one here. This generates
902 /// code like this:
903 ///
904 /// mfcr rA ; Move the conditional register into GPR rA.
905 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
906 /// stw rA, FI ; Store rA to the frame.
907 ///
909  unsigned FrameIndex) const {
910  // Get the instruction.
911  MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
912  // Get the instruction's basic block.
913  MachineBasicBlock &MBB = *MI.getParent();
914  MachineFunction &MF = *MBB.getParent();
915  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
916  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
917  DebugLoc dl = MI.getDebugLoc();
918 
919  bool LP64 = TM.isPPC64();
920  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
921  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
922 
923  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
924  Register SrcReg = MI.getOperand(0).getReg();
925 
926  // We need to store the CR in the low 4-bits of the saved value. First, issue
927  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
928  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
929  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
930 
931  // If the saved register wasn't CR0, shift the bits left so that they are in
932  // CR0's slot.
933  if (SrcReg != PPC::CR0) {
934  Register Reg1 = Reg;
935  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
936 
937  // rlwinm rA, rA, ShiftBits, 0, 31.
938  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
939  .addReg(Reg1, RegState::Kill)
940  .addImm(getEncodingValue(SrcReg) * 4)
941  .addImm(0)
942  .addImm(31);
943  }
944 
945  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
947  FrameIndex);
948 
949  // Discard the pseudo instruction.
950  MBB.erase(II);
951 }
952 
954  unsigned FrameIndex) const {
955  // Get the instruction.
956  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
957  // Get the instruction's basic block.
958  MachineBasicBlock &MBB = *MI.getParent();
959  MachineFunction &MF = *MBB.getParent();
960  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
961  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
962  DebugLoc dl = MI.getDebugLoc();
963 
964  bool LP64 = TM.isPPC64();
965  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
966  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
967 
968  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
969  Register DestReg = MI.getOperand(0).getReg();
970  assert(MI.definesRegister(DestReg) &&
971  "RESTORE_CR does not define its destination");
972 
973  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
974  Reg), FrameIndex);
975 
976  // If the reloaded register isn't CR0, shift the bits right so that they are
977  // in the right CR's slot.
978  if (DestReg != PPC::CR0) {
979  Register Reg1 = Reg;
980  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
981 
982  unsigned ShiftBits = getEncodingValue(DestReg)*4;
983  // rlwinm r11, r11, 32-ShiftBits, 0, 31.
984  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
985  .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
986  .addImm(31);
987  }
988 
989  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
991 
992  // Discard the pseudo instruction.
993  MBB.erase(II);
994 }
995 
997  unsigned FrameIndex) const {
998  // Get the instruction.
999  MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
1000  // Get the instruction's basic block.
1001  MachineBasicBlock &MBB = *MI.getParent();
1002  MachineFunction &MF = *MBB.getParent();
1003  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1004  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1005  const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
1006  DebugLoc dl = MI.getDebugLoc();
1007 
1008  bool LP64 = TM.isPPC64();
1009  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1010  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1011 
1012  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1013  Register SrcReg = MI.getOperand(0).getReg();
1014 
1015  // Search up the BB to find the definition of the CR bit.
1018  ++Ins;
1019  unsigned CRBitSpillDistance = 0;
1020  bool SeenUse = false;
1021  for (; Ins != Rend; ++Ins) {
1022  // Definition found.
1023  if (Ins->modifiesRegister(SrcReg, TRI))
1024  break;
1025  // Use found.
1026  if (Ins->readsRegister(SrcReg, TRI))
1027  SeenUse = true;
1028  // Unable to find CR bit definition within maximum search distance.
1029  if (CRBitSpillDistance == MaxCRBitSpillDist) {
1030  Ins = MI;
1031  break;
1032  }
1033  // Skip debug instructions when counting CR bit spill distance.
1034  if (!Ins->isDebugInstr())
1035  CRBitSpillDistance++;
1036  }
1037 
1038  // Unable to find the definition of the CR bit in the MBB.
1039  if (Ins == MBB.rend())
1040  Ins = MI;
1041 
1042  bool SpillsKnownBit = false;
1043  // There is no need to extract the CR bit if its value is already known.
1044  switch (Ins->getOpcode()) {
1045  case PPC::CRUNSET:
1046  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
1047  .addImm(0);
1048  SpillsKnownBit = true;
1049  break;
1050  case PPC::CRSET:
1051  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
1052  .addImm(-32768);
1053  SpillsKnownBit = true;
1054  break;
1055  default:
1056  // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
1057  // bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
1058  // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
1059  // register), and SETNBC will set this.
1060  if (Subtarget.isISA3_1()) {
1061  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg)
1062  .addReg(SrcReg, RegState::Undef);
1063  break;
1064  }
1065 
1066  // On Power9, we can use SETB to extract the LT bit. This only works for
1067  // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
1068  // of the bit we care about (32-bit sign bit) will be set to the value of
1069  // the LT bit (regardless of the other bits in the CR field).
1070  if (Subtarget.isISA3_0()) {
1071  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
1072  SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
1073  SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
1074  SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
1075  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
1077  break;
1078  }
1079  }
1080 
1081  // We need to move the CR field that contains the CR bit we are spilling.
1082  // The super register may not be explicitly defined (i.e. it can be defined
1083  // by a CR-logical that only defines the subreg) so we state that the CR
1084  // field is undef. Also, in order to preserve the kill flag on the CR bit,
1085  // we add it as an implicit use.
1086  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
1088  .addReg(SrcReg,
1089  RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
1090 
1091  // If the saved register wasn't CR0LT, shift the bits left so that the bit
1092  // to store is the first one. Mask all but that bit.
1093  Register Reg1 = Reg;
1094  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1095 
1096  // rlwinm rA, rA, ShiftBits, 0, 0.
1097  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
1098  .addReg(Reg1, RegState::Kill)
1099  .addImm(getEncodingValue(SrcReg))
1100  .addImm(0).addImm(0);
1101  }
1102  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
1104  FrameIndex);
1105 
1106  bool KillsCRBit = MI.killsRegister(SrcReg, TRI);
1107  // Discard the pseudo instruction.
1108  MBB.erase(II);
1109  if (SpillsKnownBit && KillsCRBit && !SeenUse) {
1110  Ins->setDesc(TII.get(PPC::UNENCODED_NOP));
1111  Ins->removeOperand(0);
1112  }
1113 }
1114 
1116  unsigned FrameIndex) const {
1117  // Get the instruction.
1118  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
1119  // Get the instruction's basic block.
1120  MachineBasicBlock &MBB = *MI.getParent();
1121  MachineFunction &MF = *MBB.getParent();
1122  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1123  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1124  DebugLoc dl = MI.getDebugLoc();
1125 
1126  bool LP64 = TM.isPPC64();
1127  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1128  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1129 
1130  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1131  Register DestReg = MI.getOperand(0).getReg();
1132  assert(MI.definesRegister(DestReg) &&
1133  "RESTORE_CRBIT does not define its destination");
1134 
1135  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
1136  Reg), FrameIndex);
1137 
1138  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
1139 
1140  Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1141  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
1142  .addReg(getCRFromCRBit(DestReg));
1143 
1144  unsigned ShiftBits = getEncodingValue(DestReg);
1145  // rlwimi r11, r10, 32-ShiftBits, ..., ...
1146  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
1147  .addReg(RegO, RegState::Kill)
1149  .addImm(ShiftBits ? 32 - ShiftBits : 0)
1150  .addImm(ShiftBits)
1151  .addImm(ShiftBits);
1152 
1153  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
1154  getCRFromCRBit(DestReg))
1155  .addReg(RegO, RegState::Kill)
1156  // Make sure we have a use dependency all the way through this
1157  // sequence of instructions. We can't have the other bits in the CR
1158  // modified in between the mfocrf and the mtocrf.
1160 
1161  // Discard the pseudo instruction.
1162  MBB.erase(II);
1163 }
1164 
1166  MCRegister DestReg, MCRegister SrcReg) {
1167 #ifdef NDEBUG
1168  return;
1169 #else
1170  if (ReportAccMoves) {
1171  std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc";
1172  std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc";
1173  dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n";
1174  MBB.dump();
1175  }
1176 #endif
1177 }
1178 
1179 static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
1180  bool IsRestore) {
1181 #ifdef NDEBUG
1182  return;
1183 #else
1184  if (ReportAccMoves) {
1185  dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc") << " register "
1186  << (IsRestore ? "restore" : "spill") << ":\n";
1187  MBB.dump();
1188  }
1189 #endif
1190 }
1191 
1192 /// lowerACCSpilling - Generate the code for spilling the accumulator register.
1193 /// Similarly to other spills/reloads that use pseudo-ops, we do not actually
1194 /// eliminate the FrameIndex here nor compute the stack offset. We simply
1195 /// create a real instruction with an FI and rely on eliminateFrameIndex to
1196 /// handle the FI elimination.
1198  unsigned FrameIndex) const {
1199  MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset>
1200  MachineBasicBlock &MBB = *MI.getParent();
1201  MachineFunction &MF = *MBB.getParent();
1202  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1203  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1204  DebugLoc DL = MI.getDebugLoc();
1205  Register SrcReg = MI.getOperand(0).getReg();
1206  bool IsKilled = MI.getOperand(0).isKill();
1207 
1208  bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1209  Register Reg =
1210  PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1211  bool IsLittleEndian = Subtarget.isLittleEndian();
1212 
1213  emitAccSpillRestoreInfo(MBB, IsPrimed, false);
1214 
1215  // De-prime the register being spilled, create two stores for the pair
1216  // subregisters accounting for endianness and then re-prime the register if
1217  // it isn't killed. This uses the Offset parameter to addFrameReference() to
1218  // adjust the offset of the store that is within the 64-byte stack slot.
1219  if (IsPrimed)
1220  BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
1221  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1222  .addReg(Reg, getKillRegState(IsKilled)),
1223  FrameIndex, IsLittleEndian ? 32 : 0);
1224  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1225  .addReg(Reg + 1, getKillRegState(IsKilled)),
1226  FrameIndex, IsLittleEndian ? 0 : 32);
1227  if (IsPrimed && !IsKilled)
1228  BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
1229 
1230  // Discard the pseudo instruction.
1231  MBB.erase(II);
1232 }
1233 
1234 /// lowerACCRestore - Generate the code to restore the accumulator register.
1236  unsigned FrameIndex) const {
1237  MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset>
1238  MachineBasicBlock &MBB = *MI.getParent();
1239  MachineFunction &MF = *MBB.getParent();
1240  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1241  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1242  DebugLoc DL = MI.getDebugLoc();
1243 
1244  Register DestReg = MI.getOperand(0).getReg();
1245  assert(MI.definesRegister(DestReg) &&
1246  "RESTORE_ACC does not define its destination");
1247 
1248  bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg);
1249  Register Reg =
1250  PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1251  bool IsLittleEndian = Subtarget.isLittleEndian();
1252 
1253  emitAccSpillRestoreInfo(MBB, IsPrimed, true);
1254 
1255  // Create two loads for the pair subregisters accounting for endianness and
1256  // then prime the accumulator register being restored.
1257  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg),
1258  FrameIndex, IsLittleEndian ? 32 : 0);
1259  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1),
1260  FrameIndex, IsLittleEndian ? 0 : 32);
1261  if (IsPrimed)
1262  BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg);
1263 
1264  // Discard the pseudo instruction.
1265  MBB.erase(II);
1266 }
1267 
1268 /// lowerQuadwordSpilling - Generate code to spill paired general register.
1270  unsigned FrameIndex) const {
1271  MachineInstr &MI = *II;
1272  MachineBasicBlock &MBB = *MI.getParent();
1273  MachineFunction &MF = *MBB.getParent();
1274  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1275  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1276  DebugLoc DL = MI.getDebugLoc();
1277 
1278  Register SrcReg = MI.getOperand(0).getReg();
1279  bool IsKilled = MI.getOperand(0).isKill();
1280 
1281  Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2;
1282  bool IsLittleEndian = Subtarget.isLittleEndian();
1283 
1284  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1285  .addReg(Reg, getKillRegState(IsKilled)),
1286  FrameIndex, IsLittleEndian ? 8 : 0);
1287  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1288  .addReg(Reg + 1, getKillRegState(IsKilled)),
1289  FrameIndex, IsLittleEndian ? 0 : 8);
1290 
1291  // Discard the pseudo instruction.
1292  MBB.erase(II);
1293 }
1294 
1295 /// lowerQuadwordRestore - Generate code to restore paired general register.
1297  unsigned FrameIndex) const {
1298  MachineInstr &MI = *II;
1299  MachineBasicBlock &MBB = *MI.getParent();
1300  MachineFunction &MF = *MBB.getParent();
1301  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1302  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1303  DebugLoc DL = MI.getDebugLoc();
1304 
1305  Register DestReg = MI.getOperand(0).getReg();
1306  assert(MI.definesRegister(DestReg) &&
1307  "RESTORE_QUADWORD does not define its destination");
1308 
1309  Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2;
1310  bool IsLittleEndian = Subtarget.isLittleEndian();
1311 
1313  IsLittleEndian ? 8 : 0);
1315  IsLittleEndian ? 0 : 8);
1316 
1317  // Discard the pseudo instruction.
1318  MBB.erase(II);
1319 }
1320 
1322  Register Reg, int &FrameIdx) const {
1323  // For the nonvolatile condition registers (CR2, CR3, CR4) return true to
1324  // prevent allocating an additional frame slot.
1325  // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
1326  // for 32-bit AIX the CR save area is in the linkage area at SP+4.
1327  // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
1328  // valid.
1329  // For 32-bit ELF, we have previously created the stack slot if needed, so
1330  // return its FrameIdx.
1331  if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
1332  FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
1333  return true;
1334  }
1335  return false;
1336 }
1337 
1338 // If the offset must be a multiple of some value, return what that value is.
1339 static unsigned offsetMinAlignForOpcode(unsigned OpC) {
1340  switch (OpC) {
1341  default:
1342  return 1;
1343  case PPC::LWA:
1344  case PPC::LWA_32:
1345  case PPC::LD:
1346  case PPC::LDU:
1347  case PPC::STD:
1348  case PPC::STDU:
1349  case PPC::DFLOADf32:
1350  case PPC::DFLOADf64:
1351  case PPC::DFSTOREf32:
1352  case PPC::DFSTOREf64:
1353  case PPC::LXSD:
1354  case PPC::LXSSP:
1355  case PPC::STXSD:
1356  case PPC::STXSSP:
1357  case PPC::STQ:
1358  return 4;
1359  case PPC::EVLDD:
1360  case PPC::EVSTDD:
1361  return 8;
1362  case PPC::LXV:
1363  case PPC::STXV:
1364  case PPC::LQ:
1365  case PPC::LXVP:
1366  case PPC::STXVP:
1367  return 16;
1368  }
1369 }
1370 
1371 // If the offset must be a multiple of some value, return what that value is.
1372 static unsigned offsetMinAlign(const MachineInstr &MI) {
1373  unsigned OpC = MI.getOpcode();
1374  return offsetMinAlignForOpcode(OpC);
1375 }
1376 
1377 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
1378 static unsigned getOffsetONFromFION(const MachineInstr &MI,
1379  unsigned FIOperandNum) {
1380  // Take into account whether it's an add or mem instruction
1381  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
1382  if (MI.isInlineAsm())
1383  OffsetOperandNo = FIOperandNum - 1;
1384  else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
1385  MI.getOpcode() == TargetOpcode::PATCHPOINT)
1386  OffsetOperandNo = FIOperandNum + 1;
1387 
1388  return OffsetOperandNo;
1389 }
1390 
1391 void
1393  int SPAdj, unsigned FIOperandNum,
1394  RegScavenger *RS) const {
1395  assert(SPAdj == 0 && "Unexpected");
1396 
1397  // Get the instruction.
1398  MachineInstr &MI = *II;
1399  // Get the instruction's basic block.
1400  MachineBasicBlock &MBB = *MI.getParent();
1401  // Get the basic block's function.
1402  MachineFunction &MF = *MBB.getParent();
1403  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1404  // Get the instruction info.
1405  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1406  // Get the frame info.
1407  MachineFrameInfo &MFI = MF.getFrameInfo();
1408  DebugLoc dl = MI.getDebugLoc();
1409 
1410  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1411 
1412  // Get the frame index.
1413  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
1414 
1415  // Get the frame pointer save index. Users of this index are primarily
1416  // DYNALLOC instructions.
1418  int FPSI = FI->getFramePointerSaveIndex();
1419  // Get the instruction opcode.
1420  unsigned OpC = MI.getOpcode();
1421 
1422  if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
1424  return;
1425  }
1426 
1427  // Special case for dynamic alloca.
1428  if (FPSI && FrameIndex == FPSI &&
1429  (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
1430  lowerDynamicAlloc(II);
1431  return;
1432  }
1433 
1434  if (FPSI && FrameIndex == FPSI &&
1435  (OpC == PPC::PREPARE_PROBED_ALLOCA_64 ||
1436  OpC == PPC::PREPARE_PROBED_ALLOCA_32 ||
1437  OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 ||
1438  OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) {
1440  return;
1441  }
1442 
1443  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1444  if (OpC == PPC::SPILL_CR) {
1446  return;
1447  } else if (OpC == PPC::RESTORE_CR) {
1449  return;
1450  } else if (OpC == PPC::SPILL_CRBIT) {
1452  return;
1453  } else if (OpC == PPC::RESTORE_CRBIT) {
1455  return;
1456  } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) {
1458  return;
1459  } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) {
1461  return;
1462  } else if (OpC == PPC::SPILL_QUADWORD) {
1464  return;
1465  } else if (OpC == PPC::RESTORE_QUADWORD) {
1467  return;
1468  }
1469 
1470  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1471  MI.getOperand(FIOperandNum).ChangeToRegister(
1472  FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
1473 
1474  // If the instruction is not present in ImmToIdxMap, then it has no immediate
1475  // form (and must be r+r).
1476  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1477  OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
1478 
1479  // Now add the frame object offset to the offset from r1.
1480  int Offset = MFI.getObjectOffset(FrameIndex);
1481  Offset += MI.getOperand(OffsetOperandNo).getImm();
1482 
1483  // If we're not using a Frame Pointer that has been set to the value of the
1484  // SP before having the stack size subtracted from it, then add the stack size
1485  // to Offset to get the correct offset.
1486  // Naked functions have stack size 0, although getStackSize may not reflect
1487  // that because we didn't call all the pieces that compute it for naked
1488  // functions.
1489  if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
1490  if (!(hasBasePointer(MF) && FrameIndex < 0))
1491  Offset += MFI.getStackSize();
1492  }
1493 
1494  // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can
1495  // transform it to the prefixed version so we don't have to use the XForm.
1496  if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
1497  (!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
1498  Subtarget.hasPrefixInstrs()) {
1499  unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
1500  MI.setDesc(TII.get(NewOpc));
1501  OpC = NewOpc;
1502  }
1503 
1504  // If we can, encode the offset directly into the instruction. If this is a
1505  // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
1506  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1507  // clear can be encoded. This is extremely uncommon, because normally you
1508  // only "std" to a stack slot that is at least 4-byte aligned, but it can
1509  // happen in invalid code.
1510  assert(OpC != PPC::DBG_VALUE &&
1511  "This should be handled in a target-independent way");
1512  // FIXME: This should be factored out to a separate function as prefixed
1513  // instructions add a number of opcodes for which we can use 34-bit imm.
1514  bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
1515  isUInt<8>(Offset) :
1516  isInt<16>(Offset);
1517  if (TII.isPrefixed(MI.getOpcode()))
1518  OffsetFitsMnemonic = isInt<34>(Offset);
1519  if (!noImmForm && ((OffsetFitsMnemonic &&
1520  ((Offset % offsetMinAlign(MI)) == 0)) ||
1521  OpC == TargetOpcode::STACKMAP ||
1522  OpC == TargetOpcode::PATCHPOINT)) {
1523  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1524  return;
1525  }
1526 
1527  // The offset doesn't fit into a single register, scavenge one to build the
1528  // offset in.
1529 
1530  bool is64Bit = TM.isPPC64();
1531  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1532  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1533  const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
1534  Register SRegHi = MF.getRegInfo().createVirtualRegister(RC),
1535  SReg = MF.getRegInfo().createVirtualRegister(RC);
1536 
1537  // Insert a set of rA with the full offset value before the ld, st, or add
1538  if (isInt<16>(Offset))
1539  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1540  .addImm(Offset);
1541  else {
1542  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1543  .addImm(Offset >> 16);
1544  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1545  .addReg(SRegHi, RegState::Kill)
1546  .addImm(Offset);
1547  }
1548 
1549  // Convert into indexed form of the instruction:
1550  //
1551  // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1552  // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1553  unsigned OperandBase;
1554 
1555  if (noImmForm)
1556  OperandBase = 1;
1557  else if (OpC != TargetOpcode::INLINEASM &&
1558  OpC != TargetOpcode::INLINEASM_BR) {
1559  assert(ImmToIdxMap.count(OpC) &&
1560  "No indexed form of load or store available!");
1561  unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
1562  MI.setDesc(TII.get(NewOpcode));
1563  OperandBase = 1;
1564  } else {
1565  OperandBase = OffsetOperandNo;
1566  }
1567 
1568  Register StackReg = MI.getOperand(FIOperandNum).getReg();
1569  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1570  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1571 }
1572 
1574  const PPCFrameLowering *TFI = getFrameLowering(MF);
1575 
1576  if (!TM.isPPC64())
1577  return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1578  else
1579  return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1580 }
1581 
1583  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1584  if (!hasBasePointer(MF))
1585  return getFrameRegister(MF);
1586 
1587  if (TM.isPPC64())
1588  return PPC::X30;
1589 
1590  if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1591  return PPC::R29;
1592 
1593  return PPC::R30;
1594 }
1595 
1597  if (!EnableBasePointer)
1598  return false;
1599  if (AlwaysBasePointer)
1600  return true;
1601 
1602  // If we need to realign the stack, then the stack pointer can no longer
1603  // serve as an offset into the caller's stack space. As a result, we need a
1604  // base pointer.
1605  return hasStackRealignment(MF);
1606 }
1607 
1608 /// Returns true if the instruction's frame index
1609 /// reference would be better served by a base register other than FP
1610 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1611 /// references it should create new base registers for.
1612 bool PPCRegisterInfo::
1613 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1614  assert(Offset < 0 && "Local offset must be negative");
1615 
1616  // It's the load/store FI references that cause issues, as it can be difficult
1617  // to materialize the offset if it won't fit in the literal field. Estimate
1618  // based on the size of the local frame and some conservative assumptions
1619  // about the rest of the stack frame (note, this is pre-regalloc, so
1620  // we don't know everything for certain yet) whether this offset is likely
1621  // to be out of range of the immediate. Return true if so.
1622 
1623  // We only generate virtual base registers for loads and stores that have
1624  // an r+i form. Return false for everything else.
1625  unsigned OpC = MI->getOpcode();
1626  if (!ImmToIdxMap.count(OpC))
1627  return false;
1628 
1629  // Don't generate a new virtual base register just to add zero to it.
1630  if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1631  MI->getOperand(2).getImm() == 0)
1632  return false;
1633 
1634  MachineBasicBlock &MBB = *MI->getParent();
1635  MachineFunction &MF = *MBB.getParent();
1636  const PPCFrameLowering *TFI = getFrameLowering(MF);
1637  unsigned StackEst = TFI->determineFrameLayout(MF, true);
1638 
1639  // If we likely don't need a stack frame, then we probably don't need a
1640  // virtual base register either.
1641  if (!StackEst)
1642  return false;
1643 
1644  // Estimate an offset from the stack pointer.
1645  // The incoming offset is relating to the SP at the start of the function,
1646  // but when we access the local it'll be relative to the SP after local
1647  // allocation, so adjust our SP-relative offset by that allocation size.
1648  Offset += StackEst;
1649 
1650  // The frame pointer will point to the end of the stack, so estimate the
1651  // offset as the difference between the object offset and the FP location.
1652  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1653 }
1654 
1655 /// Insert defining instruction(s) for BaseReg to
1656 /// be a pointer to FrameIdx at the beginning of the basic block.
1658  int FrameIdx,
1659  int64_t Offset) const {
1660  unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1661 
1663  DebugLoc DL; // Defaults to "unknown"
1664  if (Ins != MBB->end())
1665  DL = Ins->getDebugLoc();
1666 
1667  const MachineFunction &MF = *MBB->getParent();
1668  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1669  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1670  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1672  const TargetRegisterClass *RC = getPointerRegClass(MF);
1673  Register BaseReg = MRI.createVirtualRegister(RC);
1674  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1675 
1676  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1677  .addFrameIndex(FrameIdx).addImm(Offset);
1678 
1679  return BaseReg;
1680 }
1681 
1683  int64_t Offset) const {
1684  unsigned FIOperandNum = 0;
1685  while (!MI.getOperand(FIOperandNum).isFI()) {
1686  ++FIOperandNum;
1687  assert(FIOperandNum < MI.getNumOperands() &&
1688  "Instr doesn't have FrameIndex operand!");
1689  }
1690 
1691  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1692  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1693  Offset += MI.getOperand(OffsetOperandNo).getImm();
1694  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1695 
1696  MachineBasicBlock &MBB = *MI.getParent();
1697  MachineFunction &MF = *MBB.getParent();
1698  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1699  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1700  const MCInstrDesc &MCID = MI.getDesc();
1702  MRI.constrainRegClass(BaseReg,
1703  TII.getRegClass(MCID, FIOperandNum, this, MF));
1704 }
1705 
1707  Register BaseReg,
1708  int64_t Offset) const {
1709  unsigned FIOperandNum = 0;
1710  while (!MI->getOperand(FIOperandNum).isFI()) {
1711  ++FIOperandNum;
1712  assert(FIOperandNum < MI->getNumOperands() &&
1713  "Instr doesn't have FrameIndex operand!");
1714  }
1715 
1716  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1717  Offset += MI->getOperand(OffsetOperandNo).getImm();
1718 
1719  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1720  MI->getOpcode() == TargetOpcode::STACKMAP ||
1721  MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1722  (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1723 }
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:788
llvm::MachineFunction::hasInlineAsm
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
Definition: MachineFunction.h:713
llvm::PPCRegisterInfo::lowerDynamicAlloc
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
Definition: PPCRegisterInfo.cpp:688
CmpMode::FP
@ FP
llvm::PPCRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
Definition: PPCRegisterInfo.cpp:165
llvm::getCRFromCRBit
static unsigned getCRFromCRBit(unsigned SrcReg)
Definition: PPCRegisterInfo.h:26
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:138
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::PPCSubtarget::getRegisterInfo
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:223
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::PPCRegisterInfo::lowerQuadwordRestore
void lowerQuadwordRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordRestore - Generate code to restore paired general register.
Definition: PPCRegisterInfo.cpp:1296
llvm::PPCFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: PPCFrameLowering.cpp:359
llvm::PPCRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:431
TargetFrameLowering.h
PPCRegisterInfo.h
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::PPCSubtarget::hasPrefixInstrs
bool hasPrefixInstrs() const
Definition: PPCSubtarget.h:287
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::PPCSubtarget::hasMMA
bool hasMMA() const
Definition: PPCSubtarget.h:289
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
PPCInstrBuilder.h
Statistic.h
llvm::PPCSubtarget::hasP8Vector
bool hasP8Vector() const
Definition: PPCSubtarget.h:281
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::PPCSubtarget::isLittleEndian
bool isLittleEndian() const
Definition: PPCSubtarget.h:261
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::PPCSubtarget::hasROPProtect
bool hasROPProtect() const
Definition: PPCSubtarget.h:290
llvm::PPCRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:633
llvm::PPCSubtarget::hasVSX
bool hasVSX() const
Definition: PPCSubtarget.h:279
llvm::PPCRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:1573
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::PPCSubtarget::hasP9Vector
bool hasP9Vector() const
Definition: PPCSubtarget.h:284
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::PPCFunctionInfo
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
Definition: PPCMachineFunctionInfo.h:24
llvm::PPCISD::DYNALLOC
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
Definition: PPCISelLowering.h:144
getOffsetONFromFION
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
Definition: PPCRegisterInfo.cpp:1378
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
STLExtras.h
llvm::PPCSubtarget::getStackPointerRegister
MCRegister getStackPointerRegister() const
Definition: PPCSubtarget.h:428
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::PPCSubtarget::is64BitELFABI
bool is64BitELFABI() const
Definition: PPCSubtarget.h:369
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:646
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MaxCRBitSpillDist
static cl::opt< unsigned > MaxCRBitSpillDist("ppc-max-crbit-spill-dist", cl::desc("Maximum search distance for definition of CR bit " "spill on ppc"), cl::Hidden, cl::init(100))
MachineRegisterInfo.h
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1018
llvm::MachineBasicBlock::dump
void dump() const
Definition: MachineBasicBlock.cpp:291
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1295
llvm::PPCRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Definition: PPCRegisterInfo.cpp:1657
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
PPCSubtarget.h
CommandLine.h
llvm::MachineRegisterInfo::reg_nodbg_instructions
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:362
R2
#define R2(n)
llvm::PPCRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: PPCRegisterInfo.cpp:1682
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
StackPtrConst
static cl::opt< bool > StackPtrConst("ppc-stack-ptr-caller-preserved", cl::desc("Consider R1 caller preserved so stack saves of " "caller preserved registers can be LICM candidates"), cl::init(true), cl::Hidden)
Constants.h
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCSubtarget::getTOCPointerRegister
MCRegister getTOCPointerRegister() const
Definition: PPCSubtarget.h:422
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::PPCFrameLowering
Definition: PPCFrameLowering.h:22
AlwaysBasePointer
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::PPCSubtarget::isISA3_1
bool isISA3_1() const
Definition: PPCSubtarget.h:338
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::PPCSubtarget::isISA3_0
bool isISA3_0() const
Definition: PPCSubtarget.h:337
llvm::PPCRegisterInfo::lowerQuadwordSpilling
void lowerQuadwordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordSpilling - Generate code to spill paired general register.
Definition: PPCRegisterInfo.cpp:1269
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
PPCFrameLowering.h
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:287
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:577
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::BitVector
Definition: BitVector.h:75
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::PPCRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: PPCRegisterInfo.cpp:321
llvm::PPCSubtarget::getInstrInfo
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:216
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::PPCRegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: PPCRegisterInfo.cpp:530
llvm::MachineFrameInfo::isCalleeSavedInfoValid
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
Definition: MachineFrameInfo.h:792
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::PPCISD::XXMFACC
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
Definition: PPCISelLowering.h:488
llvm::VirtRegMap::hasPhys
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:99
ReportAccMoves
static cl::opt< bool > ReportAccMoves("ppc-report-acc-moves", cl::desc("Emit information about accumulator register spills " "and copies"), cl::Hidden, cl::init(false))
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::PPCSubtarget::isAIXABI
bool isAIXABI() const
Definition: PPCSubtarget.h:365
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::PPCSubtarget::isSVR4ABI
bool isSVR4ABI() const
Definition: PPCSubtarget.h:366
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::cl::opt< bool >
llvm::TargetMachine::getAIXExtendedAltivecABI
bool getAIXExtendedAltivecABI() const
Definition: TargetMachine.h:262
llvm::PPCRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition: PPCRegisterInfo.cpp:1613
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
VirtRegMap.h
llvm::PPCRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: PPCRegisterInfo.cpp:181
llvm::PPCSubtarget::is32BitELFABI
bool is32BitELFABI() const
Definition: PPCSubtarget.h:370
llvm::PPCRegisterInfo::lowerDynamicAreaOffset
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
Definition: PPCRegisterInfo.cpp:877
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:422
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:152
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:943
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::PPCRegisterInfo::lowerCRBitRestore
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:1115
llvm::PPCRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: PPCRegisterInfo.cpp:419
llvm::PPCRegisterInfo::getBaseRegister
Register getBaseRegister(const MachineFunction &MF) const
Definition: PPCRegisterInfo.cpp:1582
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::PPCRegisterInfo::lowerCRBitSpilling
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:996
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::PPCISD::DYNAREAOFFSET
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
Definition: PPCISelLowering.h:149
EnableBasePointer
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::PPCRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:588
llvm::PPCRegisterInfo::adjustStackMapLiveOutMask
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
Definition: PPCRegisterInfo.cpp:325
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:779
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:481
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::PPCRegisterInfo::hasReservedSpillSlot
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
Definition: PPCRegisterInfo.cpp:1321
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
emitAccSpillRestoreInfo
static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed, bool IsRestore)
Definition: PPCRegisterInfo.cpp:1179
offsetMinAlignForOpcode
static unsigned offsetMinAlignForOpcode(unsigned OpC)
Definition: PPCRegisterInfo.cpp:1339
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCTargetMachine::isPPC64
bool isPPC64() const
Definition: PPCTargetMachine.h:60
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:593
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::PPCRegisterInfo::emitAccCopyInfo
static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg, MCRegister SrcReg)
Definition: PPCRegisterInfo.cpp:1165
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::PPCRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: PPCRegisterInfo.cpp:1596
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::PPCRegisterInfo::PPCRegisterInfo
PPCRegisterInfo(const PPCTargetMachine &TM)
Definition: PPCRegisterInfo.cpp:96
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
uint16_t
llvm::PPCFrameLowering::determineFrameLayout
uint64_t determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
Definition: PPCFrameLowering.cpp:297
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:177
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::PPCRegisterInfo::lowerACCRestore
void lowerACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCRestore - Generate the code to restore the accumulator register.
Definition: PPCRegisterInfo.cpp:1235
offsetMinAlign
static unsigned offsetMinAlign(const MachineInstr &MI)
Definition: PPCRegisterInfo.cpp:1372
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1021
llvm::PPCRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: PPCRegisterInfo.cpp:262
Function.h
PPCGenRegisterInfo
llvm::PPCSubtarget::hasSPE
bool hasSPE() const
Definition: PPCSubtarget.h:276
llvm::PPCRegisterInfo::lowerCRSpilling
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
Definition: PPCRegisterInfo.cpp:908
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::PPCISD::MFOCRF
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
Definition: PPCISelLowering.h:217
llvm::PPCRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:330
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::PPCRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: PPCRegisterInfo.cpp:1706
llvm::PPCSubtarget::isUsingPCRelativeCalls
bool isUsingPCRelativeCalls() const
Definition: PPCSubtarget.cpp:256
llvm::PPCSubtarget::hasAltivec
bool hasAltivec() const
Definition: PPCSubtarget.h:275
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::PPCRegisterInfo::lowerPrepareProbedAlloca
void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const
Definition: PPCRegisterInfo.cpp:836
llvm::PPCTargetMachine::isELFv2ABI
bool isELFv2ABI() const
Definition: PPCTargetMachine.h:59
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
PPCMachineFunctionInfo.h
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::PPCFunctionInfo::getFramePointerSaveIndex
int getFramePointerSaveIndex() const
Definition: PPCMachineFunctionInfo.h:156
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl< MCPhysReg >
llvm::PPCRegisterInfo::isCallerPreservedPhysReg
bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:507
llvm::PPCRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:497
EnableGPRToVecSpills
static cl::opt< bool > EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), cl::desc("Enable spills from gpr to vsr rather than stack"))
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::PPCRegisterInfo::lowerCRRestore
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:953
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:405
RegisterScavenging.h
llvm::PPCFunctionInfo::usesTOCBasePtr
bool usesTOCBasePtr() const
Definition: PPCMachineFunctionInfo.h:214
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
raw_ostream.h
llvm::PPCRegisterInfo::lowerACCSpilling
void lowerACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCSpilling - Generate the code for spilling the accumulator register.
Definition: PPCRegisterInfo.cpp:1197
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::PPCRegisterInfo::prepareDynamicAlloca
void prepareDynamicAlloca(MachineBasicBlock::iterator II, Register &NegSizeReg, bool &KillNegSizeReg, Register &FramePointer) const
To accomplish dynamic stack allocation, we have to calculate exact size subtracted from the stack poi...
Definition: PPCRegisterInfo.cpp:745
llvm::PPCRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: PPCRegisterInfo.cpp:1392
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
PPCTargetMachine.h
llvm::PPCSubtarget::pairedVectorMemops
bool pairedVectorMemops() const
Definition: PPCSubtarget.h:292
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40