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33 #define DEBUG_TYPE "framelowering"
34 STATISTIC(NumPESpillVSR,
"Number of spills to vector in prologue");
35 STATISTIC(NumPEReloadVSR,
"Number of reloads from vector in epilogue");
36 STATISTIC(NumPrologProbed,
"Number of prologues probed");
40 cl::desc(
"Enable spills in prologue to vector registers."),
58 return STI.
isPPC64() ? -8U : -4U;
75 return STI.
isPPC64() ? -16U : -8U;
84 STI.getPlatformStackAlignment(), 0),
94 unsigned &NumEntries)
const {
97 #define CALLEE_SAVED_FPRS \
119 #define CALLEE_SAVED_GPRS32 \
140 #define CALLEE_SAVED_GPRS64 \
161 #define CALLEE_SAVED_VRS \
178 static const SpillSlot ELFOffsets32[] = {
213 static const SpillSlot ELFOffsets64[] = {
228 static const SpillSlot AIXOffsets64[] = {
285 bool UseEstimate)
const {
286 unsigned NewMaxCallFrameSize = 0;
288 &NewMaxCallFrameSize);
299 unsigned *NewMaxCallFrameSize)
const {
314 unsigned LR = RegInfo->getRARegister();
327 if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
337 maxCallFrameSize =
std::max(maxCallFrameSize, minCallFrameSize);
342 maxCallFrameSize =
alignTo(maxCallFrameSize, Alignment);
345 if (NewMaxCallFrameSize)
346 *NewMaxCallFrameSize = maxCallFrameSize;
349 FrameSize += maxCallFrameSize;
352 FrameSize =
alignTo(FrameSize, Alignment);
387 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
388 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
392 unsigned BPReg = HasBP ? (unsigned) RegInfo->
getBaseRegister(MF) : FPReg;
393 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;
398 for (
unsigned I = 0,
E =
MBBI->getNumOperands();
I !=
E; ++
I) {
441 bool TwoUniqueRegsRequired,
453 assert (SR1 &&
"Asking for the second scratch register but not the first?");
496 for (
int i = 0; CSRegs[
i]; ++
i)
502 *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
509 int SecondScratchReg = BV.
find_next(*SR1);
510 if (SecondScratchReg != -1)
511 *SR2 = SecondScratchReg;
513 *SR2 = TwoUniqueRegsRequired ?
Register() : *SR1;
518 if (BV.
count() < (TwoUniqueRegsRequired ? 2U : 1U))
537 int NegFrameSize = -FrameSize;
538 bool IsLargeFrame = !
isInt<16>(NegFrameSize);
544 return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) ||
551 return findScratchRegister(TmpMBB,
false,
552 twoUniqueScratchRegsRequired(TmpMBB));
558 return findScratchRegister(TmpMBB,
true);
561 bool PPCFrameLowering::stackUpdateCanBeMoved(
MachineFunction &MF)
const {
620 bool isPPC64 = Subtarget.
isPPC64();
624 assert((isSVR4ABI || Subtarget.
isAIXABI()) &&
"Unsupported PPC ABI.");
628 int64_t NegFrameSize = -FrameSize;
640 bool MustSaveCR = !MustSaveCRs.empty();
642 bool HasFP =
hasFP(MF);
644 bool HasRedZone = isPPC64 || !isSVR4ABI;
648 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
650 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
651 Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
654 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
662 const MCInstrDesc& StoreUpdtIdxInst =
TII.get(isPPC64 ? PPC::STDUX
664 const MCInstrDesc& LoadImmShiftedInst =
TII.get(isPPC64 ? PPC::LIS8
670 const MCInstrDesc& SubtractCarryingInst =
TII.get(isPPC64 ? PPC::SUBFC8
672 const MCInstrDesc& SubtractImmCarryingInst =
TII.get(isPPC64 ? PPC::SUBFIC8
674 const MCInstrDesc &MoveFromCondRegInst =
TII.get(isPPC64 ? PPC::MFCR8
676 const MCInstrDesc &StoreWordInst =
TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
678 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHSTP8 : PPC::HASHST8)
679 : (HasPrivileged ? PPC::HASHSTP : PPC::HASHST));
686 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
689 bool SingleScratchReg = findScratchRegister(
690 &
MBB,
false, twoUniqueScratchRegsRequired(&
MBB), &ScratchReg, &TempReg);
691 assert(SingleScratchReg &&
692 "Required number of registers not available in this block");
694 SingleScratchReg = ScratchReg == TempReg;
698 int64_t FPOffset = 0;
702 assert(FPIndex &&
"No Frame Pointer Save Slot!");
706 int64_t BPOffset = 0;
710 assert(BPIndex &&
"No Base Pointer Save Slot!");
714 int64_t PBPOffset = 0;
718 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
724 if (HasBP && MaxAlign > 1)
725 assert(
Log2(MaxAlign) < 16 &&
"Invalid alignment!");
729 bool isLargeFrame = !
isInt<16>(NegFrameSize);
735 bool MovingStackUpdateDown =
false;
738 if (stackUpdateCanBeMoved(MF)) {
751 if (CSI.isSpilledToReg()) {
752 StackUpdateLoc =
MBBI;
753 MovingStackUpdateDown =
false;
757 int FrIdx = CSI.getFrameIdx();
766 MovingStackUpdateDown =
true;
770 StackUpdateLoc =
MBBI;
771 MovingStackUpdateDown =
false;
777 if (MovingStackUpdateDown) {
779 int FrIdx = CSI.getFrameIdx();
789 auto BuildMoveFromCR = [&]() {
790 if (isELFv2ABI && MustSaveCRs.size() == 1) {
795 assert(isPPC64 &&
"V2 ABI is 64-bit only.");
802 for (
unsigned CRfield : MustSaveCRs)
809 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
820 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR))
859 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
860 "ROP hash save offset out of range.");
861 assert(((ImmOffset & 0x7) == 0) &&
862 "ROP hash save offset must be 8 byte aligned.");
872 assert(HasRedZone &&
"A red zone is always available on PPC64");
886 if (HasBP && HasRedZone) {
895 bool HasSTUX =
false;
904 TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64
905 : PPC::PROBED_STACKALLOC_32))
920 if (HasBP && MaxAlign > 1) {
937 assert(!SingleScratchReg &&
"Only a single scratch reg available");
939 .
addImm(NegFrameSize >> 16);
942 .
addImm(NegFrameSize & 0xFFFF);
954 }
else if (!isLargeFrame) {
955 BuildMI(
MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
962 .
addImm(NegFrameSize >> 16);
965 .
addImm(NegFrameSize & 0xFFFF);
977 assert(isELFv2ABI &&
"TOC saves in the prologue only supported on ELFv2");
985 assert(!isPPC64 &&
"A red zone is always available on PPC64");
1001 if (ScratchReg == PPC::R0) {
1010 .
addImm(FPOffset-LastOffset);
1011 LastOffset = FPOffset;
1022 .
addImm(PBPOffset-LastOffset);
1023 LastOffset = PBPOffset;
1033 .
addImm(BPOffset-LastOffset);
1034 LastOffset = BPOffset;
1078 .
addImm(FrameSize + FPOffset)
1083 .
addImm(FrameSize + PBPOffset)
1088 .
addImm(FrameSize + BPOffset)
1105 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1119 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1128 unsigned Reg =
MRI->getDwarfRegNum(PPC::R30,
true);
1137 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1146 unsigned Reg =
MRI->getDwarfRegNum(LRReg,
true);
1160 if (!HasBP && needsCFI) {
1163 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1190 if (isSVR4ABI && (PPC::CR2 <=
Reg &&
Reg <= PPC::CR4)
1196 if (isSVR4ABI && isPPC64 && (PPC::CR2 <=
Reg &&
Reg <= PPC::CR4)) {
1202 nullptr,
MRI->getDwarfRegNum(CRReg,
true), CRSaveOffset));
1208 if (
I.isSpilledToReg()) {
1209 unsigned SpilledReg =
I.getDstReg();
1211 nullptr,
MRI->getDwarfRegNum(
Reg,
true),
1212 MRI->getDwarfRegNum(SpilledReg,
true)));
1220 if (MovingStackUpdateDown)
1221 Offset -= NegFrameSize;
1224 nullptr,
MRI->getDwarfRegNum(
Reg,
true), Offset));
1234 bool isPPC64 = Subtarget.
isPPC64();
1243 int Opc =
MI.getOpcode();
1244 return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32;
1246 if (StackAllocMIPos == PrologMBB.
end())
1252 int64_t NegFrameSize =
MI.getOperand(2).getImm();
1254 int64_t NegProbeSize = -(int64_t)ProbeSize;
1256 int64_t NumBlocks = NegFrameSize / NegProbeSize;
1257 int64_t NegResidualSize = NegFrameSize % NegProbeSize;
1258 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1259 Register ScratchReg =
MI.getOperand(0).getReg();
1270 unsigned RegNum =
MRI->getDwarfRegNum(
Reg,
true);
1279 unsigned RegNum =
MRI->getDwarfRegNum(
Reg,
true);
1306 Register NegSizeReg,
bool UseDForm,
1348 assert(HasBP &&
"The function is supposed to have base pointer when its "
1349 "stack is realigned.");
1357 "Probe size should be larger or equal to the size of red-zone so "
1358 "that red-zone is not clobbered by probing.");
1364 NegProbeSize =
std::max(NegProbeSize, -((int64_t)1 << 15));
1366 "NegProbeSize should be materializable by DForm");
1383 MF.
insert(MBBInsertPoint, ProbeLoopBodyMBB);
1385 MF.
insert(MBBInsertPoint, ProbeExitMBB);
1388 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1389 allocateAndProbe(*ProbeExitMBB, ProbeExitMBB->
end(), 0, ScratchReg,
false,
1394 BuildMI(*ProbeExitMBB, ProbeExitMBB->
end(),
DL, CopyInst, TempReg)
1402 BuildMI(&
MBB,
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), ScratchReg)
1419 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1420 allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->
end(), NegProbeSize,
1421 0,
true , BackChainPointer);
1422 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI),
1426 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI),
1433 .
addMBB(ProbeLoopBodyMBB);
1440 return ProbeExitMBB;
1445 if (HasBP && MaxAlign > 1) {
1458 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF),
1462 MaterializeImm(*CurrentMBB, {
MI}, NegFrameSize, ScratchReg);
1463 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
1467 CurrentMBB = probeRealignedStack(*CurrentMBB, {
MI}, ScratchReg, FPReg);
1475 buildDefCFA(*CurrentMBB, {
MI}, FPReg, 0);
1477 if (NegResidualSize) {
1478 bool ResidualUseDForm = CanUseDForm(NegResidualSize);
1479 if (!ResidualUseDForm)
1480 MaterializeImm(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg);
1481 allocateAndProbe(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg,
1482 ResidualUseDForm, FPReg);
1484 bool UseDForm = CanUseDForm(NegProbeSize);
1486 if (NumBlocks < 3) {
1488 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1489 for (
int i = 0;
i < NumBlocks; ++
i)
1490 allocateAndProbe(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg, UseDForm,
1501 MaterializeImm(*CurrentMBB, {
MI}, NumBlocks, ScratchReg);
1505 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1510 MF.
insert(MBBInsertPoint, LoopMBB);
1512 MF.
insert(MBBInsertPoint, ExitMBB);
1514 allocateAndProbe(*LoopMBB, LoopMBB->
end(), NegProbeSize, ScratchReg,
1521 ExitMBB->
splice(ExitMBB->
end(), CurrentMBB,
1536 MI.eraseFromParent();
1545 dl =
MBBI->getDebugLoc();
1557 bool isPPC64 = Subtarget.
isPPC64();
1563 bool MustSaveCR = !MustSaveCRs.empty();
1565 bool HasFP =
hasFP(MF);
1571 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1573 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1575 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
1580 const MCInstrDesc& LoadImmShiftedInst =
TII.get( isPPC64 ? PPC::LIS8
1592 const MCInstrDesc& MoveToCRInst =
TII.get( isPPC64 ? PPC::MTOCRF8
1595 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHCHKP8 : PPC::HASHCHK8)
1596 : (HasPrivileged ? PPC::HASHCHKP : PPC::HASHCHK));
1599 int64_t FPOffset = 0;
1602 bool SingleScratchReg = findScratchRegister(&
MBB,
true,
false, &ScratchReg,
1604 assert(SingleScratchReg &&
1605 "Could not find an available scratch register");
1607 SingleScratchReg = ScratchReg == TempReg;
1611 assert(FPIndex &&
"No Frame Pointer Save Slot!");
1615 int64_t BPOffset = 0;
1618 assert(BPIndex &&
"No Base Pointer Save Slot!");
1622 int64_t PBPOffset = 0;
1625 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
1631 if (IsReturnBlock) {
1632 unsigned RetOpcode =
MBBI->getOpcode();
1633 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1634 RetOpcode == PPC::TCRETURNdi ||
1635 RetOpcode == PPC::TCRETURNai ||
1636 RetOpcode == PPC::TCRETURNri8 ||
1637 RetOpcode == PPC::TCRETURNdi8 ||
1638 RetOpcode == PPC::TCRETURNai8;
1643 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
1645 int StackAdj = StackAdjust.
getImm();
1646 int Delta = StackAdj - MaxTCRetDelta;
1647 assert((Delta >= 0) &&
"Delta must be positive");
1648 if (MaxTCRetDelta>0)
1649 FrameSize += (StackAdj +Delta);
1651 FrameSize += StackAdj;
1657 bool isLargeFrame = !
isInt<16>(FrameSize);
1671 unsigned RBReg = SPReg;
1679 if (stackUpdateCanBeMoved(MF)) {
1684 if (CSI.isSpilledToReg()) {
1685 StackUpdateLoc =
MBBI;
1688 int FrIdx = CSI.getFrameIdx();
1700 StackUpdateLoc =
MBBI;
1713 if (HasRedZone && HasBP) {
1723 assert(HasFP &&
"Expecting a valid frame pointer.");
1726 if (!isLargeFrame) {
1731 .
addImm(FrameSize >> 16);
1734 .
addImm(FrameSize & 0xFFFF);
1742 BuildMI(
MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1748 assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1749 "Local offsets should be negative");
1751 FPOffset += FrameSize;
1752 BPOffset += FrameSize;
1753 PBPOffset += FrameSize;
1771 assert(RBReg != ScratchReg &&
"Should have avoided ScratchReg");
1778 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
1781 assert(HasRedZone &&
"Expecting red zone");
1785 for (
unsigned i = 0,
e = MustSaveCRs.size();
i !=
e; ++
i)
1794 bool LoadedLR =
false;
1802 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR)) {
1803 assert(RBReg == SPReg &&
"Should be using SP as a base register");
1812 if (HasRedZone || RBReg == SPReg)
1834 if (RBReg != SPReg || SPAdd != 0) {
1835 assert(!HasRedZone &&
"This should not happen with red zone");
1846 assert(RBReg != ScratchReg &&
"Should be using FP or SP as base register");
1861 for (
unsigned i = 0,
e = MustSaveCRs.size();
i !=
e; ++
i)
1868 if (HasROPProtect) {
1871 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
1872 "ROP hash check location offset out of range.");
1873 assert(((ImmOffset & 0x7) == 0) &&
1874 "ROP hash check location offset must be 8 byte aligned.");
1885 if (IsReturnBlock) {
1886 unsigned RetOpcode =
MBBI->getOpcode();
1888 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1893 if (CallerAllocatedAmt &&
isInt<16>(CallerAllocatedAmt)) {
1898 .
addImm(CallerAllocatedAmt >> 16);
1901 .
addImm(CallerAllocatedAmt & 0xFFFF);
1908 createTailCallBranchInstr(
MBB);
1929 unsigned RetOpcode =
MBBI->getOpcode();
1930 if (RetOpcode == PPC::TCRETURNdi) {
1941 }
else if (RetOpcode == PPC::TCRETURNri) {
1943 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1945 }
else if (RetOpcode == PPC::TCRETURNai) {
1949 }
else if (RetOpcode == PPC::TCRETURNdi8) {
1960 }
else if (RetOpcode == PPC::TCRETURNri8) {
1962 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1964 }
else if (RetOpcode == PPC::TCRETURNai8) {
1980 SavedRegs.
reset(PPC::VSRp26);
1981 SavedRegs.
reset(PPC::VSRp27);
1982 SavedRegs.
reset(PPC::VSRp28);
1983 SavedRegs.
reset(PPC::VSRp29);
1984 SavedRegs.
reset(PPC::VSRp30);
1985 SavedRegs.
reset(PPC::VSRp31);
1989 unsigned LR = RegInfo->getRARegister();
1991 SavedRegs.
reset(LR);
1995 const bool isPPC64 = Subtarget.
isPPC64();
2029 SavedRegs.
reset(isPPC64 ? PPC::X31 : PPC::R31);
2033 SavedRegs.
reset(PPC::R30);
2048 if ((SavedRegs.
test(PPC::CR2) || SavedRegs.
test(PPC::CR3) ||
2049 SavedRegs.
test(PPC::CR4))) {
2051 const int64_t SpillOffset =
2074 createTailCallBranchInstr(
MBB);
2079 if (CSI.empty() && !
needsFP(MF)) {
2084 unsigned MinGPR = PPC::R31;
2085 unsigned MinG8R = PPC::X31;
2086 unsigned MinFPR = PPC::F31;
2087 unsigned MinVR = Subtarget.
hasSPE() ? PPC::S31 : PPC::V31;
2089 bool HasGPSaveArea =
false;
2090 bool HasG8SaveArea =
false;
2091 bool HasFPSaveArea =
false;
2092 bool HasVRSaveArea =
false;
2103 "Not expecting to try to spill R2 in a function that must save TOC");
2105 HasGPSaveArea =
true;
2107 GPRegs.push_back(
I);
2113 HasG8SaveArea =
true;
2115 G8Regs.push_back(
I);
2121 HasFPSaveArea =
true;
2123 FPRegs.push_back(
I);
2135 HasVRSaveArea =
true;
2150 int64_t LowerBound = 0;
2156 LowerBound = TCSPDelta;
2161 if (HasFPSaveArea) {
2162 for (
unsigned i = 0,
e = FPRegs.size();
i !=
e; ++
i) {
2163 int FI = FPRegs[
i].getFrameIdx();
2175 assert(FI &&
"No Frame Pointer Save Slot!");
2178 HasGPSaveArea =
true;
2183 assert(FI &&
"No PIC Base Pointer Save Slot!");
2186 MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
2187 HasGPSaveArea =
true;
2193 assert(FI &&
"No Base Pointer Save Slot!");
2197 if (PPC::G8RCRegClass.
contains(BP)) {
2198 MinG8R = std::min<unsigned>(MinG8R, BP);
2199 HasG8SaveArea =
true;
2200 }
else if (PPC::GPRCRegClass.
contains(BP)) {
2201 MinGPR = std::min<unsigned>(MinGPR, BP);
2202 HasGPSaveArea =
true;
2208 if (HasGPSaveArea || HasG8SaveArea) {
2211 for (
unsigned i = 0,
e = GPRegs.size();
i !=
e; ++
i) {
2212 if (!GPRegs[
i].isSpilledToReg()) {
2213 int FI = GPRegs[
i].getFrameIdx();
2220 for (
unsigned i = 0,
e = G8Regs.size();
i !=
e; ++
i) {
2221 if (!G8Regs[
i].isSpilledToReg()) {
2222 int FI = G8Regs[
i].getFrameIdx();
2231 const unsigned GPRegSize = Subtarget.
isPPC64() ? 8 : 4;
2232 LowerBound -= (31 - MinReg + 1) * GPRegSize;
2242 for (
const auto &CSInfo : CSI) {
2243 if (CSInfo.getReg() == PPC::CR2) {
2244 int FI = CSInfo.getFrameIdx();
2255 if (HasVRSaveArea) {
2261 assert(LowerBound <= 0 &&
"Expect LowerBound have a non-positive value!");
2262 LowerBound &= ~(15);
2264 for (
unsigned i = 0,
e = VRegs.size();
i !=
e; ++
i) {
2265 int FI = VRegs[
i].getFrameIdx();
2320 std::vector<CalleeSavedInfo> &CSI)
const {
2335 for (
unsigned i = 0; CSRegs[
i]; ++
i)
2336 BVCalleeSaved.
set(CSRegs[
i]);
2346 bool AllSpilledToReg =
true;
2347 unsigned LastVSRUsedForSpill = 0;
2348 for (
auto &CS : CSI) {
2349 if (BVAllocatable.
none())
2355 AllSpilledToReg =
false;
2361 if (LastVSRUsedForSpill != 0) {
2362 CS.setDstReg(LastVSRUsedForSpill);
2363 BVAllocatable.
reset(LastVSRUsedForSpill);
2364 LastVSRUsedForSpill = 0;
2368 unsigned VolatileVFReg = BVAllocatable.
find_first();
2369 if (VolatileVFReg < BVAllocatable.
size()) {
2370 CS.setDstReg(VolatileVFReg);
2371 LastVSRUsedForSpill = VolatileVFReg;
2373 AllSpilledToReg =
false;
2376 return AllSpilledToReg;
2388 bool CRSpilled =
false;
2392 VSRContainingGPRs.clear();
2397 if (
Info.isSpilledToReg()) {
2399 VSRContainingGPRs.FindAndConstruct(Info.getDstReg()).second;
2400 assert(SpilledVSR.second == 0 &&
2401 "Can't spill more than two GPRs into VSR!");
2402 if (SpilledVSR.first == 0)
2403 SpilledVSR.first = Info.getReg();
2405 SpilledVSR.second = Info.getReg();
2413 bool IsCRField = PPC::CR2 <=
Reg &&
Reg <= PPC::CR4;
2425 if (CRSpilled && IsCRField) {
2456 if (
I.isSpilledToReg()) {
2457 unsigned Dst =
I.getDstReg();
2462 if (VSRContainingGPRs[Dst].second != 0) {
2464 "mtvsrdd is unavailable on pre-P9 targets.");
2470 }
else if (VSRContainingGPRs[Dst].second == 0) {
2472 "Can't move GPR to VSR on pre-P8 targets.");
2491 TII.storeRegToStackSlotNoUpd(
MBB,
MI,
Reg, !IsLiveIn,
2492 I.getFrameIdx(), RC,
TRI);
2502 static void restoreCRs(
bool is31,
bool CR2Spilled,
bool CR3Spilled,
2515 CSI[CSIIndex].getFrameIdx()));
2517 unsigned RestoreOp = PPC::MTOCRF;
2536 I->getOpcode() == PPC::ADJCALLSTACKUP) {
2538 if (
int CalleeAmt =
I->getOperand(1).getImm()) {
2541 unsigned StackReg =
is64Bit ? PPC::X1 : PPC::R1;
2542 unsigned TmpReg =
is64Bit ? PPC::X0 : PPC::R0;
2543 unsigned ADDIInstr =
is64Bit ? PPC::ADDI8 : PPC::ADDI;
2544 unsigned ADDInstr =
is64Bit ? PPC::ADD8 : PPC::ADD4;
2545 unsigned LISInstr =
is64Bit ? PPC::LIS8 : PPC::LIS;
2546 unsigned ORIInstr =
is64Bit ? PPC::ORI8 : PPC::ORI;
2556 .
addImm(CalleeAmt >> 16);
2559 .
addImm(CalleeAmt & 0xFFFF);
2571 return PPC::CR2 ==
Reg ||
Reg == PPC::CR3 ||
Reg == PPC::CR4;
2581 bool CR2Spilled =
false;
2582 bool CR3Spilled =
false;
2583 bool CR4Spilled =
false;
2584 unsigned CSIIndex = 0;
2595 for (
unsigned i = 0,
e = CSI.
size();
i !=
e; ++
i) {
2606 if (
Reg == PPC::CR2) {
2612 }
else if (
Reg == PPC::CR3) {
2615 }
else if (
Reg == PPC::CR4) {
2621 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2623 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI,
2625 CR2Spilled = CR3Spilled = CR4Spilled =
false;
2628 if (CSI[
i].isSpilledToReg()) {
2630 unsigned Dst = CSI[
i].getDstReg();
2635 if (VSRContainingGPRs[Dst].second != 0) {
2637 NumPEReloadVSR += 2;
2639 VSRContainingGPRs[Dst].second)
2642 VSRContainingGPRs[Dst].first)
2644 }
else if (VSRContainingGPRs[Dst].second == 0) {
2648 VSRContainingGPRs[Dst].first)
2664 TII.loadRegFromStackSlotNoUpd(
MBB,
I,
Reg, CSI[
i].getFrameIdx(), RC,
2670 "loadRegFromStackSlot didn't insert any code!");
2684 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2686 "Only set CR[2|3|4]Spilled on 32-bit SVR4.");
2688 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI, CSIIndex);
2695 return TOCSaveOffset;
2699 return FramePointerSaveOffset;
2703 return BasePointerSaveOffset;
int getBasePointerSaveIndex() const
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
void addMustSaveCR(Register Reg)
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
#define CALLEE_SAVED_GPRS32
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
def_iterator def_begin(Register RegNo) const
const PPCRegisterInfo * getRegisterInfo() const override
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
This is an optimization pass for GlobalISel generic memory operations.
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
Information about stack frame layout on the target.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
const MCContext & getContext() const
unsigned getMinReservedArea() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const GlobalValue * getGlobal() const
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const MCRegisterInfo * getRegisterInfo() const
static bool isCalleeSavedCR(unsigned Reg)
static bool is64Bit(const char *name)
bool none() const
none - Returns true if none of the bits are set.
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
return AArch64::GPR64RegClass contains(Reg)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
This function will assign callee saved gprs to volatile vector registers for prologue spills when app...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
Reg
All possible values of the reg field in the ModR/M byte.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
static bool hasSpills(const MachineFunction &MF)
bool hasROPProtect() const
iterator_range< const_set_bits_iterator > set_bits() const
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
void replaceFPWithRealFP(MachineFunction &MF) const
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
uint64_t getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only.
void setStackSize(uint64_t Size)
Set the size of the stack.
void insert(iterator MBBI, MachineBasicBlock *MBB)
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
void setMaxCallFrameSize(unsigned S)
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const PPCTargetMachine & getTargetMachine() const
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool needsFP(const MachineFunction &MF) const
int64_t getOffset() const
Return the offset from the symbol in this operand.
unsigned const TargetRegisterInfo * TRI
bool is64BitELFABI() const
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
LLVM Basic Block Representation.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const MachineBasicBlock & front() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
uint64_t getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
TargetInstrInfo - Interface to description of machine instruction set.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
size_type count() const
count - Returns the number of bits which are set.
unsigned Log2(Align A)
Returns the log2 of the alignment.
size_type size() const
size - Returns the number of bits in this bitvector.
static bool spillsCR(const MachineFunction &MF)
@ Kill
The last use of a register.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const HexagonInstrInfo * TII
PPCFrameLowering(const PPCSubtarget &STI)
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
int getPICBasePointerSaveIndex() const
This class contains meta information specific to a module.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
MachineBasicBlock * getRestorePoint() const
STATISTIC(NumFunctions, "Total number of functions")
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Analysis containing CSE Info
void setCRSpillFrameIndex(int idx)
unsigned getRedZoneSize() const
const PPCInstrInfo * getInstrInfo() const override
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
This struct is a compact representation of a valid (non-zero power of two) alignment.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
bool isPositionIndependent() const
bool isLRStoreRequired() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
MachineModuleInfo & getMMI() const
static void buildDefCFAReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Reg, const SystemZInstrInfo *ZII)
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
bool hasInlineStackProbe(MachineFunction &MF) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
An instruction for storing to memory.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
constexpr bool isInt< 32 >(int64_t x)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
UnaryFunction for_each(R &&Range, UnaryFunction F)
Provide wrappers to std::for_each which take ranges instead of having to pass begin/end explicitly.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
bool is32BitELFABI() const
bool needsSwapsForVSXMemOps() const
#define CALLEE_SAVED_FPRS
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasNonRISpills() const
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
initializer< Ty > init(const Ty &Val)
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
unsigned getStackProbeSize(MachineFunction &MF) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Register getBaseRegister(const MachineFunction &MF) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
#define CALLEE_SAVED_GPRS64
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
static def_iterator def_end()
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineBasicBlock MachineBasicBlock::iterator MBBI
static cl::opt< bool > EnablePEVectorSpills("ppc-enable-pe-vector-spills", cl::desc("Enable spills in prologue to vector registers."), cl::init(false), cl::Hidden)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
self_iterator getIterator()
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
static bool hasNonRISpills(const MachineFunction &MF)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
An instruction for reading from memory.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
static void restoreCRs(bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, unsigned CSIIndex)
unsigned const MachineRegisterInfo * MRI
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
bool hasCalls() const
Return true if the current function has any function calls.
const PPCTargetLowering * getTargetLowering() const override
constexpr bool isInt< 16 >(int64_t x)
bool hasBasePointer(const MachineFunction &MF) const
MachineBasicBlock * getSavePoint() const
void setBasePointerSaveIndex(int Idx)
bool test(unsigned Idx) const
bool isLiveIn(Register Reg) const
Function & getFunction()
Return the LLVM function that this machine code represents.
bool hasPrivileged() const
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
uint64_t determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
uint64_t getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Iterator for intrusive lists based on ilist_node.
int getTailCallSPDelta() const
uint64_t getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
static unsigned computeLinkageSize(const PPCSubtarget &STI)
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
void forward()
Move the internal MBB iterator and update register states.
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function.
bool shrinkWrapDisabled() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getKillRegState(bool B)
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
const char * getSymbolName() const
const SmallVectorImpl< Register > & getMustSaveCRs() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void setReg(Register Reg)
Change the register this operand corresponds to.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
size_t size() const
size - Get the array size.
Align max(MaybeAlign Lhs, Align Rhs)
uint64_t determineFrameLayoutAndUpdate(MachineFunction &MF, bool UseEstimate=false) const
Determine the frame layout and update the machine function.
int getFramePointerSaveIndex() const
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
static unsigned computeCRSaveOffset(const PPCSubtarget &STI)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
void setFramePointerSaveIndex(int Idx)
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool hasTailCall() const
Returns true if the function contains a tail call.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
int getROPProtectionHashSaveIndex() const
void setPICBasePointerSaveIndex(int Idx)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.