SI Implementation of TargetInstrInfo. More...

#include "SIInstrInfo.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPULaneMaskUtils.h"
#include "GCNHazardRecognizer.h"
#include "GCNSubtarget.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineCycleAnalysis.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"

Classes
struct	llvm::SIInstrInfo::ThreeAddressUpdates
	Helper struct for the implementation of 3-address conversion to communicate updates made to instruction operands. More...

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::AMDGPU

Macros
#define	DEBUG_TYPE "si-instr-info"
#define	GET_INSTRINFO_CTOR_DTOR
#define	GET_D16ImageDimIntrinsics_IMPL
#define	GET_ImageDimIntrinsicTable_IMPL
#define	GET_RsrcIntrinsics_IMPL
#define	GENERATE_RENAMED_GFX9_CASES(OPCODE)

Functions
static unsigned	getNumOperandsNoGlue (SDNode *Node)
static bool	nodesHaveSameOperandValue (SDNode N0, SDNode N1, AMDGPU::OpName OpName)
	Returns true if both nodes have the same value for the given operand `Op`, or if both nodes do not have this operand.
static bool	canRemat (const MachineInstr &MI)
static bool	isStride64 (unsigned Opc)
static bool	memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
static void	reportIllegalCopy (const SIInstrInfo TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const char Msg="illegal VGPR to SGPR copy")
static void	indirectCopyToAGPR (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, RegScavenger &RS, bool RegsOverlap, Register ImpUseSuperReg=Register())
	Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908.
static void	expandSGPRCopy (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RC, bool Forward)
static unsigned	getIndirectVGPRWriteMovRelPseudoOpc (unsigned VecSize)
static unsigned	getIndirectSGPRWriteMovRelPseudo32 (unsigned VecSize)
static unsigned	getIndirectSGPRWriteMovRelPseudo64 (unsigned VecSize)
static unsigned	getSGPRSpillSaveOpcode (unsigned Size, bool NeedsCFI)
static unsigned	getVGPRSpillSaveOpcode (unsigned Size, bool NeedsCFI)
static unsigned	getAVSpillSaveOpcode (unsigned Size, bool NeedsCFI)
static unsigned	getWWMRegSpillSaveOpcode (unsigned Size, bool IsVectorSuperClass)
static unsigned	getSGPRSpillRestoreOpcode (unsigned Size)
static unsigned	getVGPRSpillRestoreOpcode (unsigned Size)
static unsigned	getAVSpillRestoreOpcode (unsigned Size)
static unsigned	getWWMRegSpillRestoreOpcode (unsigned Size, bool IsVectorSuperClass)
static MachineInstr *	swapRegAndNonRegOperand (MachineInstr &MI, MachineOperand &RegOp, MachineOperand &NonRegOp)
static MachineInstr *	swapImmOperands (MachineInstr &MI, MachineOperand &NonRegOp1, MachineOperand &NonRegOp2)
static void	preserveCondRegFlags (MachineOperand &CondReg, const MachineOperand &OrigCond)
static unsigned	getNewFMAAKInst (const GCNSubtarget &ST, unsigned Opc)
static unsigned	getNewFMAMKInst (const GCNSubtarget &ST, unsigned Opc)
static bool	memOpsHaveSameBaseOperands (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2)
static bool	offsetsDoNotOverlap (LocationSize WidthA, int OffsetA, LocationSize WidthB, int OffsetB)
static bool	getFoldableImm (Register Reg, const MachineRegisterInfo &MRI, int64_t &Imm, MachineInstr **DefMI=nullptr)
static bool	getFoldableImm (const MachineOperand MO, int64_t &Imm, MachineInstr *DefMI=nullptr)
static void	updateLiveVariables (LiveVariables *LV, MachineInstr &MI, MachineInstr &NewMI)
static unsigned	getNewFMAInst (const GCNSubtarget &ST, unsigned Opc)
static bool	changesVGPRIndexingMode (const MachineInstr &MI)
static bool	compareMachineOp (const MachineOperand &Op0, const MachineOperand &Op1)
static void	copyFlagsToImplicitVCC (MachineInstr &MI, const MachineOperand &Orig)
static Register	findImplicitSGPRRead (const MachineInstr &MI)
static bool	shouldReadExec (const MachineInstr &MI)
static bool	isRegOrFI (const MachineOperand &MO)
static bool	isSubRegOf (const SIRegisterInfo &TRI, const MachineOperand &SuperVec, const MachineOperand &SubReg)
static void	emitLoadScalarOpsFromVGPRLoop (const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &PredBB, MachineBasicBlock &LoopBB, MachineBasicBlock &BodyBB, const DebugLoc &DL, ArrayRef< MachineOperand * > ScalarOps, ArrayRef< Register > PhySGPRs={})
static MachineBasicBlock *	generateWaterFallLoop (const SIInstrInfo &TII, MachineInstr &MI, ArrayRef< MachineOperand * > ScalarOps, MachineDominatorTree *MDT, MachineBasicBlock::iterator Begin=nullptr, MachineBasicBlock::iterator End=nullptr, ArrayRef< Register > PhySGPRs={})
static std::tuple< unsigned, unsigned >	extractRsrcPtr (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc)
static unsigned	subtargetEncodingFamily (const GCNSubtarget &ST)
static bool	isRenamedInGFX9 (int Opcode)
static TargetInstrInfo::RegSubRegPair	getRegOrUndef (const MachineOperand &RegOpnd)
static bool	followSubRegDef (MachineInstr &MI, TargetInstrInfo::RegSubRegPair &RSR)
static bool	isSCCDeadOnExit (MachineBasicBlock *MBB)
static bool	foldableSelect (const MachineInstr &Def)
static bool	setsSCCIfResultIsZero (const MachineInstr &Def, bool &NeedInversion, unsigned &NewDefOpc)

Variables
static cl::opt< unsigned >	BranchOffsetBits ("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))
static cl::opt< bool >	Fix16BitCopies ("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden)
static constexpr AMDGPU::OpName	ModifierOpNames []

Detailed Description

SI Implementation of TargetInstrInfo.

Definition in file SIInstrInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "si-instr-info"

Definition at line 41 of file SIInstrInfo.cpp.

◆ GENERATE_RENAMED_GFX9_CASES

#define GENERATE_RENAMED_GFX9_CASES ( OPCODE )

Value:

  case OPCODE##_dpp:                                                           \
  case OPCODE##_e32:                                                           \
  case OPCODE##_e64:                                                           \
  case OPCODE##_e64_dpp:                                                       \
  case OPCODE##_sdwa:

Definition at line 10475 of file SIInstrInfo.cpp.

Referenced by isRenamedInGFX9().

◆ GET_D16ImageDimIntrinsics_IMPL

#define GET_D16ImageDimIntrinsics_IMPL

Definition at line 47 of file SIInstrInfo.cpp.

◆ GET_ImageDimIntrinsicTable_IMPL

#define GET_ImageDimIntrinsicTable_IMPL

Definition at line 48 of file SIInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 43 of file SIInstrInfo.cpp.

◆ GET_RsrcIntrinsics_IMPL

#define GET_RsrcIntrinsics_IMPL

Definition at line 49 of file SIInstrInfo.cpp.

Function Documentation

◆ canRemat()

bool canRemat ( const MachineInstr & MI )

static

Definition at line 112 of file SIInstrInfo.cpp.

References llvm::all_of(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isSDWA(), llvm::SIInstrInfo::isSMRD(), llvm::SIInstrInfo::isVOP1(), llvm::SIInstrInfo::isVOP2(), llvm::SIInstrInfo::isVOP3(), and MI.

Referenced by llvm::SIInstrInfo::isReMaterializableImpl().

◆ changesVGPRIndexingMode()

bool changesVGPRIndexingMode ( const MachineInstr & MI )

static

Definition at line 4385 of file SIInstrInfo.cpp.

References MI.

Referenced by llvm::SIInstrInfo::isSchedulingBoundary().

◆ compareMachineOp()

bool compareMachineOp	(	const MachineOperand &	Op0,
		const MachineOperand &	Op1 )

static

Definition at line 4738 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getType(), llvm_unreachable, llvm::MachineOperand::MO_Immediate, and llvm::MachineOperand::MO_Register.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ copyFlagsToImplicitVCC()

void copyFlagsToImplicitVCC	(	MachineInstr &	MI,
		const MachineOperand &	Orig )

static

Definition at line 4897 of file SIInstrInfo.cpp.

References llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), and MI.

Referenced by llvm::SIInstrInfo::buildShrunkInst().

◆ emitLoadScalarOpsFromVGPRLoop()

void emitLoadScalarOpsFromVGPRLoop	(	const SIInstrInfo &	TII,
		MachineRegisterInfo &	MRI,
		MachineBasicBlock &	PredBB,
		MachineBasicBlock &	LoopBB,
		MachineBasicBlock &	BodyBB,
		const DebugLoc &	DL,
		ArrayRef< MachineOperand * >	ScalarOps,
		ArrayRef< Register >	PhySGPRs = {} )

static

Definition at line 7018 of file SIInstrInfo.cpp.

References DL, and TII.

◆ expandSGPRCopy()

void expandSGPRCopy	(	const SIInstrInfo &	TII,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		const TargetRegisterClass *	RC,
		bool	Forward )

static

Definition at line 739 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::SIRegisterInfo::getChannelFromSubReg(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::getSubRegFromChannel(), I, llvm::Implicit, MBB, MI, llvm::ArrayRef< T >::size(), std::swap(), and TII.

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ extractRsrcPtr()

std::tuple< unsigned, unsigned > extractRsrcPtr	(	const SIInstrInfo &	TII,
		MachineInstr &	MI,
		MachineOperand &	Rsrc )

static

Definition at line 7365 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::getRegInfo(), llvm::Hi_32(), llvm::Lo_32(), MBB, MI, and TII.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ findImplicitSGPRRead()

Register findImplicitSGPRRead ( const MachineInstr & MI )

static

Definition at line 4992 of file SIInstrInfo.cpp.

References MI, and Register.

Referenced by llvm::SIInstrInfo::legalizeOperandsVOP2(), and llvm::SIInstrInfo::verifyInstruction().

◆ foldableSelect()

bool foldableSelect ( const MachineInstr & Def )

static

Definition at line 11222 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::optimizeCompareInstr().

◆ followSubRegDef()

bool followSubRegDef	(	MachineInstr &	MI,
		TargetInstrInfo::RegSubRegPair &	RSR )

static

Definition at line 10598 of file SIInstrInfo.cpp.

References getRegOrUndef(), llvm::getRegSequenceSubReg(), MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

Referenced by llvm::getVRegSubRegDef().

◆ generateWaterFallLoop()

MachineBasicBlock * generateWaterFallLoop	(	const SIInstrInfo &	TII,
		MachineInstr &	MI,
		ArrayRef< MachineOperand * >	ScalarOps,
		MachineDominatorTree *	MDT,
		MachineBasicBlock::iterator	Begin = nullptr,
		MachineBasicBlock::iterator	End = nullptr,
		ArrayRef< Register >	PhySGPRs = {} )

static

Definition at line 7254 of file SIInstrInfo.cpp.

References MI, and TII.

Referenced by llvm::SIInstrInfo::createWaterFallForSiCall(), and llvm::SIInstrInfo::legalizeOperands().

◆ getAVSpillRestoreOpcode()

unsigned getAVSpillRestoreOpcode ( unsigned Size )

static

Definition at line 1710 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::getVectorRegSpillRestoreOpcode().

◆ getAVSpillSaveOpcode()

unsigned getAVSpillSaveOpcode	(	unsigned	Size,
		bool	NeedsCFI )

static

Definition at line 1492 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::getVectorRegSpillSaveOpcode().

◆ getFoldableImm() [1/2]

bool getFoldableImm	(	const MachineOperand *	MO,
		int64_t &	Imm,
		MachineInstr **	DefMI = nullptr )

static

Definition at line 4034 of file SIInstrInfo.cpp.

References DefMI, getFoldableImm(), llvm::MachineInstr::getMF(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), and llvm::MachineOperand::isReg().

◆ getFoldableImm() [2/2]

bool getFoldableImm	(	Register	Reg,
		const MachineRegisterInfo &	MRI,
		int64_t &	Imm,
		MachineInstr **	DefMI = nullptr )

static

Definition at line 4020 of file SIInstrInfo.cpp.

References DefMI, llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::SIInstrInfo::isFoldableCopy(), and Reg.

Referenced by getFoldableImm(), llvm::SIInstrInfo::optimizeCompareInstr(), and setsSCCIfResultIsZero().

◆ getIndirectSGPRWriteMovRelPseudo32()

unsigned getIndirectSGPRWriteMovRelPseudo32 ( unsigned VecSize )

static

Definition at line 1337 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getIndirectSGPRWriteMovRelPseudo64()

unsigned getIndirectSGPRWriteMovRelPseudo64 ( unsigned VecSize )

static

Definition at line 1370 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getIndirectVGPRWriteMovRelPseudoOpc()

unsigned getIndirectVGPRWriteMovRelPseudoOpc ( unsigned VecSize )

static

Definition at line 1304 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getNewFMAAKInst()

unsigned getNewFMAAKInst	(	const GCNSubtarget &	ST,
		unsigned	Opc )

static

Definition at line 3504 of file SIInstrInfo.cpp.

References llvm_unreachable, and Opc.

Referenced by llvm::SIInstrInfo::foldImmediate().

◆ getNewFMAInst()

unsigned getNewFMAInst	(	const GCNSubtarget &	ST,
		unsigned	Opc )

static

Definition at line 4055 of file SIInstrInfo.cpp.

References llvm_unreachable, and Opc.

◆ getNewFMAMKInst()

unsigned getNewFMAMKInst	(	const GCNSubtarget &	ST,
		unsigned	Opc )

static

Definition at line 3538 of file SIInstrInfo.cpp.

References llvm_unreachable, and Opc.

Referenced by llvm::SIInstrInfo::foldImmediate().

◆ getNumOperandsNoGlue()

unsigned getNumOperandsNoGlue ( SDNode * Node )

static

Definition at line 77 of file SIInstrInfo.cpp.

References N.

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ getRegOrUndef()

TargetInstrInfo::RegSubRegPair getRegOrUndef ( const MachineOperand & RegOpnd )

static

Definition at line 10579 of file SIInstrInfo.cpp.

References assert(), llvm::getRegSubRegPair(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUndef().

Referenced by followSubRegDef(), and llvm::getRegSequenceSubReg().

◆ getSGPRSpillRestoreOpcode()

unsigned getSGPRSpillRestoreOpcode ( unsigned Size )

static

Definition at line 1638 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getSGPRSpillSaveOpcode()

unsigned getSGPRSpillSaveOpcode	(	unsigned	Size,
		bool	NeedsCFI )

static

Definition at line 1403 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

◆ getVGPRSpillRestoreOpcode()

unsigned getVGPRSpillRestoreOpcode ( unsigned Size )

static

Definition at line 1673 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::getVectorRegSpillRestoreOpcode().

◆ getVGPRSpillSaveOpcode()

unsigned getVGPRSpillSaveOpcode	(	unsigned	Size,
		bool	NeedsCFI )

static

Definition at line 1444 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::getVectorRegSpillSaveOpcode().

◆ getWWMRegSpillRestoreOpcode()

unsigned getWWMRegSpillRestoreOpcode	(	unsigned	Size,
		bool	IsVectorSuperClass )

static

Definition at line 1745 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::getVectorRegSpillRestoreOpcode().

◆ getWWMRegSpillSaveOpcode()

unsigned getWWMRegSpillSaveOpcode	(	unsigned	Size,
		bool	IsVectorSuperClass )

static

Definition at line 1537 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::getVectorRegSpillSaveOpcode().

◆ indirectCopyToAGPR()

void indirectCopyToAGPR	(	const SIInstrInfo &	TII,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		RegScavenger &	RS,
		bool	RegsOverlap,
		Register	ImpUseSuperReg = Register() )

static

Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908.

It is not possible to have a direct copy in these cases on GFX908, so an intermediate VGPR copy is required.

Definition at line 626 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, E(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::getKillRegState(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegPressureLimit(), I, llvm::Implicit, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::Kill, MBB, MI, and TII.

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ isRegOrFI()

bool isRegOrFI ( const MachineOperand & MO )

static

Definition at line 5036 of file SIInstrInfo.cpp.

References llvm::MachineOperand::isFI(), and llvm::MachineOperand::isReg().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ isRenamedInGFX9()

bool isRenamedInGFX9 ( int Opcode )

static

Definition at line 10482 of file SIInstrInfo.cpp.

References GENERATE_RENAMED_GFX9_CASES.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ isSCCDeadOnExit()

bool isSCCDeadOnExit ( MachineBasicBlock * MBB )

static

Definition at line 11134 of file SIInstrInfo.cpp.

References MBB.

◆ isStride64()

bool isStride64 ( unsigned Opc )

static

Definition at line 336 of file SIInstrInfo.cpp.

References Opc.

Referenced by llvm::SIInstrInfo::getMemOperandsWithOffsetWidth().

◆ isSubRegOf()

bool isSubRegOf	(	const SIRegisterInfo &	TRI,
		const MachineOperand &	SuperVec,
		const MachineOperand &	SubReg )

static

Definition at line 5040 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::Register::isPhysical(), and TRI.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ memOpsHaveSameBaseOperands()

bool memOpsHaveSameBaseOperands	(	ArrayRef< const MachineOperand * >	BaseOps1,
		ArrayRef< const MachineOperand * >	BaseOps2 )

static

Definition at line 3908 of file SIInstrInfo.cpp.

References E(), I, and llvm::ArrayRef< T >::size().

◆ memOpsHaveSameBasePtr()

bool memOpsHaveSameBasePtr	(	const MachineInstr &	MI1,
		ArrayRef< const MachineOperand * >	BaseOps1,
		const MachineInstr &	MI2,
		ArrayRef< const MachineOperand * >	BaseOps2 )

static

Definition at line 514 of file SIInstrInfo.cpp.

References llvm::ArrayRef< T >::front(), llvm::getUnderlyingObject(), llvm::MachineInstr::hasOneMemOperand(), llvm::isa(), and llvm::MachineInstr::memoperands_begin().

Referenced by llvm::RISCVInstrInfo::shouldClusterMemOps(), and llvm::SIInstrInfo::shouldClusterMemOps().

◆ nodesHaveSameOperandValue()

bool nodesHaveSameOperandValue	(	SDNode *	N0,
		SDNode *	N1,
		AMDGPU::OpName	OpName )

static

Returns true if both nodes have the same value for the given operand Op, or if both nodes do not have this operand.

Definition at line 86 of file SIInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), and llvm::SDNode::getOperand().

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ offsetsDoNotOverlap()

bool offsetsDoNotOverlap	(	LocationSize	WidthA,
		int	OffsetA,
		LocationSize	WidthB,
		int	OffsetB )

static

Definition at line 3919 of file SIInstrInfo.cpp.

References llvm::LocationSize::getValue(), and llvm::LocationSize::hasValue().

◆ preserveCondRegFlags()

void preserveCondRegFlags	(	MachineOperand &	CondReg,
		const MachineOperand &	OrigCond )

static

Definition at line 3152 of file SIInstrInfo.cpp.

References llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setIsUndef().

Referenced by llvm::SIInstrInfo::insertBranch(), and llvm::SIInstrInfo::insertSelect().

◆ reportIllegalCopy()

void reportIllegalCopy	(	const SIInstrInfo *	TII,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		const char *	Msg = "illegal VGPR to SGPR copy" )

static

Definition at line 609 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::CallingConv::C, DL, llvm::DS_Error, llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::getKillRegState(), MBB, MI, Msg, and TII.

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ setsSCCIfResultIsZero()

bool setsSCCIfResultIsZero	(	const MachineInstr &	Def,
		bool &	NeedInversion,
		unsigned &	NewDefOpc )

static

Definition at line 11235 of file SIInstrInfo.cpp.

References getFoldableImm(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isDead(), and llvm::MachineOperand::isImm().

Referenced by llvm::SIInstrInfo::optimizeCompareInstr().

◆ shouldReadExec()

bool shouldReadExec ( const MachineInstr & MI )

static

Definition at line 5014 of file SIInstrInfo.cpp.

References llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isSMRD(), llvm::SIInstrInfo::isVALU(), and MI.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ subtargetEncodingFamily()

◆ swapImmOperands()

MachineInstr * swapImmOperands	(	MachineInstr &	MI,
		MachineOperand &	NonRegOp1,
		MachineOperand &	NonRegOp2 )

static

Definition at line 2698 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getTargetFlags(), MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setTargetFlags().

Referenced by llvm::SIInstrInfo::commuteInstructionImpl().

◆ swapRegAndNonRegOperand()

MachineInstr * swapRegAndNonRegOperand	(	MachineInstr &	MI,
		MachineOperand &	RegOp,
		MachineOperand &	NonRegOp )

static

Definition at line 2669 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::commuteInstructionImpl().

◆ updateLiveVariables()

void updateLiveVariables	(	LiveVariables *	LV,
		MachineInstr &	MI,
		MachineInstr &	NewMI )

static

Definition at line 4043 of file SIInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, I, MI, and llvm::LiveVariables::replaceKillInstruction().

Referenced by llvm::SIInstrInfo::convertToThreeAddress().

Variable Documentation

◆ BranchOffsetBits

cl::opt< unsigned > BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))	(	"amdgpu-s-branch-bits"	,
		cl::ReallyHidden	,
		cl::init(16)	,
		cl::desc("Restrict range of branch instructions (DEBUG)")	)

static

Referenced by llvm::SIInstrInfo::isBranchOffsetInRange().

◆ Fix16BitCopies

cl::opt< bool > Fix16BitCopies("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden)	(	"amdgpu-fix-16-bit-physreg-copies"	,
		cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit")	,
		cl::init(true)	,
		cl::ReallyHidden	)

static

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ ModifierOpNames

AMDGPU::OpName ModifierOpNames[]

staticconstexpr

Initial value:

= {
    AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
    AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::clamp,
    AMDGPU::OpName::omod,           AMDGPU::OpName::op_sel}

Definition at line 3451 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::hasAnyModifiersSet(), and llvm::SIInstrInfo::removeModOperands().

Classes

Namespaces

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GENERATE_RENAMED_GFX9_CASES

◆ GET_D16ImageDimIntrinsics_IMPL

◆ GET_ImageDimIntrinsicTable_IMPL

◆ GET_INSTRINFO_CTOR_DTOR

◆ GET_RsrcIntrinsics_IMPL

Function Documentation

◆ canRemat()

◆ changesVGPRIndexingMode()

◆ compareMachineOp()

◆ copyFlagsToImplicitVCC()

◆ emitLoadScalarOpsFromVGPRLoop()

◆ expandSGPRCopy()

◆ extractRsrcPtr()

◆ findImplicitSGPRRead()

◆ foldableSelect()

◆ followSubRegDef()

◆ generateWaterFallLoop()

◆ getAVSpillRestoreOpcode()

◆ getAVSpillSaveOpcode()

◆ getFoldableImm() [1/2]

◆ getFoldableImm() [2/2]

◆ getIndirectSGPRWriteMovRelPseudo32()

◆ getIndirectSGPRWriteMovRelPseudo64()

◆ getIndirectVGPRWriteMovRelPseudoOpc()

◆ getNewFMAAKInst()

◆ getNewFMAInst()

◆ getNewFMAMKInst()

◆ getNumOperandsNoGlue()

◆ getRegOrUndef()

◆ getSGPRSpillRestoreOpcode()

◆ getSGPRSpillSaveOpcode()

◆ getVGPRSpillRestoreOpcode()

◆ getVGPRSpillSaveOpcode()

◆ getWWMRegSpillRestoreOpcode()

◆ getWWMRegSpillSaveOpcode()

◆ indirectCopyToAGPR()

◆ isRegOrFI()

◆ isRenamedInGFX9()

◆ isSCCDeadOnExit()

◆ isStride64()

◆ isSubRegOf()

◆ memOpsHaveSameBaseOperands()

◆ memOpsHaveSameBasePtr()

◆ nodesHaveSameOperandValue()

◆ offsetsDoNotOverlap()

◆ preserveCondRegFlags()

◆ reportIllegalCopy()

◆ setsSCCIfResultIsZero()

◆ shouldReadExec()

◆ subtargetEncodingFamily()

◆ swapImmOperands()

◆ swapRegAndNonRegOperand()

◆ updateLiveVariables()

Variable Documentation

◆ BranchOffsetBits

◆ Fix16BitCopies

◆ ModifierOpNames