LLVM  14.0.0git
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SIInstrInfo.cpp File Reference
#include "SIInstrInfo.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "GCNHazardRecognizer.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"
Include dependency graph for SIInstrInfo.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This file implements support for optimizing divisions by a constant.
 
 llvm::AMDGPU
 

Macros

#define DEBUG_TYPE   "si-instr-info"
 
#define GET_INSTRINFO_CTOR_DTOR
 
#define GET_D16ImageDimIntrinsics_IMPL
 
#define GET_ImageDimIntrinsicTable_IMPL
 
#define GET_RsrcIntrinsics_IMPL
 

Enumerations

enum  SIEncodingFamily {
  SI = 0, VI = 1, SDWA = 2, SDWA9 = 3,
  GFX80 = 4, GFX9 = 5, GFX10 = 6, SDWA10 = 7,
  GFX90A = 8
}
 

Functions

static unsigned getNumOperandsNoGlue (SDNode *Node)
 
static bool nodesHaveSameOperandValue (SDNode *N0, SDNode *N1, unsigned OpName)
 Returns true if both nodes have the same value for the given operand Op, or if both nodes do not have this operand. More...
 
static bool isStride64 (unsigned Opc)
 
static bool memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
 
static void reportIllegalCopy (const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const char *Msg="illegal SGPR to VGPR copy")
 
static void indirectCopyToAGPR (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, RegScavenger &RS, Register ImpDefSuperReg=Register(), Register ImpUseSuperReg=Register())
 Handle copying from SGPR to AGPR, or from AGPR to AGPR. More...
 
static void expandSGPRCopy (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RC, bool Forward)
 
static unsigned getIndirectVGPRWriteMovRelPseudoOpc (unsigned VecSize)
 
static unsigned getIndirectSGPRWriteMovRelPseudo32 (unsigned VecSize)
 
static unsigned getIndirectSGPRWriteMovRelPseudo64 (unsigned VecSize)
 
static unsigned getSGPRSpillSaveOpcode (unsigned Size)
 
static unsigned getVGPRSpillSaveOpcode (unsigned Size)
 
static unsigned getAGPRSpillSaveOpcode (unsigned Size)
 
static unsigned getSGPRSpillRestoreOpcode (unsigned Size)
 
static unsigned getVGPRSpillRestoreOpcode (unsigned Size)
 
static unsigned getAGPRSpillRestoreOpcode (unsigned Size)
 
static MachineInstrswapRegAndNonRegOperand (MachineInstr &MI, MachineOperand &RegOp, MachineOperand &NonRegOp)
 
static void preserveCondRegFlags (MachineOperand &CondReg, const MachineOperand &OrigCond)
 
static void removeModOperands (MachineInstr &MI)
 
static bool memOpsHaveSameBaseOperands (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2)
 
static bool offsetsDoNotOverlap (int WidthA, int OffsetA, int WidthB, int OffsetB)
 
static bool getFoldableImm (Register Reg, const MachineRegisterInfo &MRI, int64_t &Imm)
 
static bool getFoldableImm (const MachineOperand *MO, int64_t &Imm)
 
static void updateLiveVariables (LiveVariables *LV, MachineInstr &MI, MachineInstr &NewMI)
 
static bool changesVGPRIndexingMode (const MachineInstr &MI)
 
static bool compareMachineOp (const MachineOperand &Op0, const MachineOperand &Op1)
 
static void copyFlagsToImplicitVCC (MachineInstr &MI, const MachineOperand &Orig)
 
static Register findImplicitSGPRRead (const MachineInstr &MI)
 
static bool shouldReadExec (const MachineInstr &MI)
 
static bool isSubRegOf (const SIRegisterInfo &TRI, const MachineOperand &SuperVec, const MachineOperand &SubReg)
 
static unsigned adjustAllocatableRegClass (const GCNSubtarget &ST, const MachineRegisterInfo &MRI, const MCInstrDesc &TID, unsigned RCID, bool IsAllocatable)
 
static void emitLoadSRsrcFromVGPRLoop (const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, MachineOperand &Rsrc)
 
static MachineBasicBlockloadSRsrcFromVGPR (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc, MachineDominatorTree *MDT, MachineBasicBlock::iterator Begin=nullptr, MachineBasicBlock::iterator End=nullptr)
 
static std::tuple< unsigned, unsigned > extractRsrcPtr (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc)
 
static SIEncodingFamily subtargetEncodingFamily (const GCNSubtarget &ST)
 
static TargetInstrInfo::RegSubRegPair getRegOrUndef (const MachineOperand &RegOpnd)
 
static bool followSubRegDef (MachineInstr &MI, TargetInstrInfo::RegSubRegPair &RSR)
 

Variables

static cl::opt< unsigned > BranchOffsetBits ("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))
 
static cl::opt< bool > Fix16BitCopies ("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden)
 

Detailed Description

SI Implementation of TargetInstrInfo.

Definition in file SIInstrInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "si-instr-info"

Definition at line 35 of file SIInstrInfo.cpp.

◆ GET_D16ImageDimIntrinsics_IMPL

#define GET_D16ImageDimIntrinsics_IMPL

Definition at line 45 of file SIInstrInfo.cpp.

◆ GET_ImageDimIntrinsicTable_IMPL

#define GET_ImageDimIntrinsicTable_IMPL

Definition at line 46 of file SIInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 37 of file SIInstrInfo.cpp.

◆ GET_RsrcIntrinsics_IMPL

#define GET_RsrcIntrinsics_IMPL

Definition at line 47 of file SIInstrInfo.cpp.

Enumeration Type Documentation

◆ SIEncodingFamily

Enumerator
SI 
VI 
SDWA 
SDWA9 
GFX80 
GFX9 
GFX10 
SDWA10 
GFX90A 

Definition at line 7687 of file SIInstrInfo.cpp.

Function Documentation

◆ adjustAllocatableRegClass()

static unsigned adjustAllocatableRegClass ( const GCNSubtarget ST,
const MachineRegisterInfo MRI,
const MCInstrDesc TID,
unsigned  RCID,
bool  IsAllocatable 
)
static

◆ changesVGPRIndexingMode()

static bool changesVGPRIndexingMode ( const MachineInstr MI)
static

Definition at line 3248 of file SIInstrInfo.cpp.

References MI.

Referenced by llvm::SIInstrInfo::isSchedulingBoundary().

◆ compareMachineOp()

static bool compareMachineOp ( const MachineOperand Op0,
const MachineOperand Op1 
)
static

◆ copyFlagsToImplicitVCC()

static void copyFlagsToImplicitVCC ( MachineInstr MI,
const MachineOperand Orig 
)
static

◆ emitLoadSRsrcFromVGPRLoop()

static void emitLoadSRsrcFromVGPRLoop ( const SIInstrInfo TII,
MachineRegisterInfo MRI,
MachineBasicBlock OrigBB,
MachineBasicBlock LoopBB,
const DebugLoc DL,
MachineOperand Rsrc 
)
static

◆ expandSGPRCopy()

static void expandSGPRCopy ( const SIInstrInfo TII,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
const TargetRegisterClass RC,
bool  Forward 
)
static

◆ extractRsrcPtr()

static std::tuple<unsigned, unsigned> extractRsrcPtr ( const SIInstrInfo TII,
MachineInstr MI,
MachineOperand Rsrc 
)
static

◆ findImplicitSGPRRead()

static Register findImplicitSGPRRead ( const MachineInstr MI)
static

◆ followSubRegDef()

static bool followSubRegDef ( MachineInstr MI,
TargetInstrInfo::RegSubRegPair RSR 
)
static

◆ getAGPRSpillRestoreOpcode()

static unsigned getAGPRSpillRestoreOpcode ( unsigned  Size)
static

Definition at line 1531 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getAGPRSpillSaveOpcode()

static unsigned getAGPRSpillSaveOpcode ( unsigned  Size)
static

Definition at line 1392 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ getFoldableImm() [1/2]

static bool getFoldableImm ( const MachineOperand MO,
int64_t &  Imm 
)
static

◆ getFoldableImm() [2/2]

static bool getFoldableImm ( Register  Reg,
const MachineRegisterInfo MRI,
int64_t &  Imm 
)
static

◆ getIndirectSGPRWriteMovRelPseudo32()

static unsigned getIndirectSGPRWriteMovRelPseudo32 ( unsigned  VecSize)
static

◆ getIndirectSGPRWriteMovRelPseudo64()

static unsigned getIndirectSGPRWriteMovRelPseudo64 ( unsigned  VecSize)
static

◆ getIndirectVGPRWriteMovRelPseudoOpc()

static unsigned getIndirectVGPRWriteMovRelPseudoOpc ( unsigned  VecSize)
static

◆ getNumOperandsNoGlue()

static unsigned getNumOperandsNoGlue ( SDNode Node)
static

Definition at line 76 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ getRegOrUndef()

static TargetInstrInfo::RegSubRegPair getRegOrUndef ( const MachineOperand RegOpnd)
static

◆ getSGPRSpillRestoreOpcode()

static unsigned getSGPRSpillRestoreOpcode ( unsigned  Size)
static

Definition at line 1477 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getSGPRSpillSaveOpcode()

static unsigned getSGPRSpillSaveOpcode ( unsigned  Size)
static

Definition at line 1338 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ getVGPRSpillRestoreOpcode()

static unsigned getVGPRSpillRestoreOpcode ( unsigned  Size)
static

Definition at line 1504 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getVGPRSpillSaveOpcode()

static unsigned getVGPRSpillSaveOpcode ( unsigned  Size)
static

Definition at line 1365 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ indirectCopyToAGPR()

static void indirectCopyToAGPR ( const SIInstrInfo TII,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
RegScavenger RS,
Register  ImpDefSuperReg = Register(),
Register  ImpUseSuperReg = Register() 
)
static

◆ isStride64()

static bool isStride64 ( unsigned  Opc)
static

Definition at line 241 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::getMemOperandsWithOffsetWidth().

◆ isSubRegOf()

static bool isSubRegOf ( const SIRegisterInfo TRI,
const MachineOperand SuperVec,
const MachineOperand SubReg 
)
static

◆ loadSRsrcFromVGPR()

static MachineBasicBlock* loadSRsrcFromVGPR ( const SIInstrInfo TII,
MachineInstr MI,
MachineOperand Rsrc,
MachineDominatorTree MDT,
MachineBasicBlock::iterator  Begin = nullptr,
MachineBasicBlock::iterator  End = nullptr 
)
static

Definition at line 5337 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ memOpsHaveSameBaseOperands()

static bool memOpsHaveSameBaseOperands ( ArrayRef< const MachineOperand * >  BaseOps1,
ArrayRef< const MachineOperand * >  BaseOps2 
)
static

Definition at line 2997 of file SIInstrInfo.cpp.

References E, I, and llvm::ArrayRef< T >::size().

◆ memOpsHaveSameBasePtr()

static bool memOpsHaveSameBasePtr ( const MachineInstr MI1,
ArrayRef< const MachineOperand * >  BaseOps1,
const MachineInstr MI2,
ArrayRef< const MachineOperand * >  BaseOps2 
)
static

◆ nodesHaveSameOperandValue()

static bool nodesHaveSameOperandValue ( SDNode N0,
SDNode N1,
unsigned  OpName 
)
static

Returns true if both nodes have the same value for the given operand Op, or if both nodes do not have this operand.

Definition at line 85 of file SIInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), and llvm::SDNode::getOperand().

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ offsetsDoNotOverlap()

static bool offsetsDoNotOverlap ( int  WidthA,
int  OffsetA,
int  WidthB,
int  OffsetB 
)
static

Definition at line 3008 of file SIInstrInfo.cpp.

◆ preserveCondRegFlags()

static void preserveCondRegFlags ( MachineOperand CondReg,
const MachineOperand OrigCond 
)
static

◆ removeModOperands()

static void removeModOperands ( MachineInstr MI)
static

Definition at line 2753 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), and MI.

Referenced by llvm::SIInstrInfo::FoldImmediate().

◆ reportIllegalCopy()

static void reportIllegalCopy ( const SIInstrInfo TII,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
const char *  Msg = "illegal SGPR to VGPR copy" 
)
static

◆ shouldReadExec()

static bool shouldReadExec ( const MachineInstr MI)
static

◆ subtargetEncodingFamily()

static SIEncodingFamily subtargetEncodingFamily ( const GCNSubtarget ST)
static

◆ swapRegAndNonRegOperand()

static MachineInstr* swapRegAndNonRegOperand ( MachineInstr MI,
MachineOperand RegOp,
MachineOperand NonRegOp 
)
static

◆ updateLiveVariables()

static void updateLiveVariables ( LiveVariables LV,
MachineInstr MI,
MachineInstr NewMI 
)
static

Variable Documentation

◆ BranchOffsetBits

cl::opt<unsigned> BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))
static

◆ Fix16BitCopies

cl::opt<bool> Fix16BitCopies("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden)
static