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58 cl::desc(
"Enable the machine combiner pass"),
100 if (TT.isOSBinFormatMachO()) {
102 return std::make_unique<X86_64MachoTargetObjectFile>();
103 return std::make_unique<TargetLoweringObjectFileMachO>();
106 if (TT.isOSBinFormatCOFF())
107 return std::make_unique<TargetLoweringObjectFileCOFF>();
108 return std::make_unique<X86ELFTargetObjectFile>();
113 std::string
Ret =
"e";
117 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
121 Ret +=
"-p270:32:32-p271:32:32-p272:64:64";
124 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
126 else if (TT.isOSIAMCU())
127 Ret +=
"-i64:32-f64:32";
132 if (TT.isOSNaCl() || TT.isOSIAMCU())
134 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
143 if (TT.isArch64Bit())
144 Ret +=
"-n8:16:32:64";
149 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
150 Ret +=
"-a:0:32-S32";
170 if (TT.isOSDarwin()) {
175 if (TT.isOSWindows() &&
is64Bit)
187 if (!TT.isOSDarwin())
200 bool JIT,
bool Is64Bit) {
227 if (TT.isPS() || TT.isOSBinFormatMachO()) {
244 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
245 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
246 Attribute FSAttr =
F.getFnAttribute(
"target-features");
262 unsigned PreferVectorWidthOverride = 0;
263 Attribute PreferVecWidthAttr =
F.getFnAttribute(
"prefer-vector-width");
264 if (PreferVecWidthAttr.
isValid()) {
270 PreferVectorWidthOverride =
Width;
275 unsigned RequiredVectorWidth = UINT32_MAX;
276 Attribute MinLegalVecWidthAttr =
F.getFnAttribute(
"min-legal-vector-width");
277 if (MinLegalVecWidthAttr.
isValid()) {
283 RequiredVectorWidth =
Width;
294 unsigned FSStart =
Key.size();
301 bool SoftFloat =
F.getFnAttribute(
"use-soft-float").getValueAsBool();
305 Key +=
FS.empty() ?
"+soft-float" :
"+soft-float,";
311 FS =
Key.substr(FSStart);
313 auto &
I = SubtargetMap[
Key];
319 I = std::make_unique<X86Subtarget>(
321 MaybeAlign(
F.getParent()->getOverrideStackAlignment()),
322 PreferVectorWidthOverride, RequiredVectorWidth);
328 unsigned DestAS)
const {
329 assert(SrcAS != DestAS &&
"Expected different address spaces!");
332 return SrcAS < 256 && DestAS < 256;
357 return getTM<X86TargetMachine>();
374 void addIRPasses()
override;
375 bool addInstSelector()
override;
376 bool addIRTranslator()
override;
377 bool addLegalizeMachineIR()
override;
378 bool addRegBankSelect()
override;
379 bool addGlobalInstructionSelect()
override;
380 bool addILPOpts()
override;
381 bool addPreISel()
override;
382 void addMachineSSAOptimization()
override;
383 void addPreRegAlloc()
override;
384 bool addPostFastRegAllocRewrite()
override;
385 void addPostRegAlloc()
override;
386 void addPreEmitPass()
override;
387 void addPreEmitPass2()
override;
388 void addPreSched2()
override;
389 bool addPreRewrite()
override;
391 std::unique_ptr<CSEConfigBase> getCSEConfig()
const override;
399 return "X86 Execution Dependency Fix";
407 "X86 Execution Domain Fix",
false,
false)
413 return new X86PassConfig(*
this, PM);
416 void X86PassConfig::addIRPasses() {
437 const Triple &TT =
TM->getTargetTriple();
438 if (TT.isOSWindows()) {
446 if (
TM->Options.JMCInstrument)
450 bool X86PassConfig::addInstSelector() {
455 if (
TM->getTargetTriple().isOSBinFormatELF() &&
463 bool X86PassConfig::addIRTranslator() {
468 bool X86PassConfig::addLegalizeMachineIR() {
473 bool X86PassConfig::addRegBankSelect() {
478 bool X86PassConfig::addGlobalInstructionSelect() {
483 bool X86PassConfig::addILPOpts() {
491 bool X86PassConfig::addPreISel() {
499 void X86PassConfig::addPreRegAlloc() {
518 void X86PassConfig::addMachineSSAOptimization() {
523 void X86PassConfig::addPostRegAlloc() {
536 void X86PassConfig::addPreEmitPass() {
538 addPass(
new X86ExecutionDomainFix());
557 void X86PassConfig::addPreEmitPass2() {
581 if (!
TT.isOSDarwin() &&
582 (!
TT.isOSWindows() ||
586 if (
TT.isOSWindows()) {
605 return M->getFunction(
"objc_retainAutoreleasedReturnValue") ||
606 M->getFunction(
"objc_unsafeClaimAutoreleasedReturnValue");
610 bool X86PassConfig::addPostFastRegAllocRewrite() {
615 bool X86PassConfig::addPreRewrite() {
620 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig()
const {
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
This is an optimization pass for GlobalISel generic memory operations.
bool isValid() const
Return true if the attribute is any kind of attribute.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
This class provides the reaching def analysis.
void initializeX86FastPreTileConfigPass(PassRegistry &)
Target & getTheX86_64Target()
static bool is64Bit(const char *name)
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Target - Wrapper for Target specific information.
void initializeEvexToVexInstPassPass(PassRegistry &)
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
Triple - Helper class for working with autoconf configuration names.
static const char * getManglingComponent(const Triple &T)
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
void initializeX86ExpandPseudoPass(PassRegistry &)
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
void setMachineOutliner(bool Enable)
x86 execution domain X86 Execution Domain Fix
(vector float) vec_cmpeq(*A, *B) C
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionPass * createX86SpeculativeLoadHardeningPass()
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
This pass is responsible for selecting generic machine instructions to target-specific instructions.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
void initializePseudoProbeInserterPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
StringRef getValueAsString() const
Return the attribute's value as a string.
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Target & getTheX86_32Target()
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeFPSPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
#define LLVM_EXTERNAL_VISIBILITY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
initializer< Ty > init(const Ty &Val)
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
char & LiveRangeShrinkID
LiveRangeShrink pass.
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
A Module instance is used to store all the information related to an LLVM module.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerTileCopyPass(PassRegistry &)
const X86Subtarget * getSubtargetImpl() const =delete
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
StringRef - Represent a constant reference to a string, i.e.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createIndirectBrExpandPass()
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void initializeFixupBWInstPassPass(PassRegistry &)
Function & getFunction()
Return the LLVM function that this machine code represents.
void initializeFixupLEAPassPass(PassRegistry &)
static std::string computeDataLayout(const Triple &TT)
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
void initializeX86PreTileConfigPass(PassRegistry &)
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
void initializeX86CallFrameOptimizationPass(PassRegistry &)
ExceptionHandling getExceptionHandlingType() const
void initializeX86PartialReductionPass(PassRegistry &)
void initializeX86FixupSetCCPassPass(PassRegistry &)
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86AvoidSFBPassPass(PassRegistry &)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
void initializeX86OptimizeLEAPassPass(PassRegistry &)
void initializeX86ExecutionDomainFixPass(PassRegistry &)
const char LLVMTargetMachineRef TM
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
~X86TargetMachine() override
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
void setSupportsDebugEntryValues(bool Enable)
void initializeX86DomainReassignmentPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
A ScheduleDAG for scheduling lists of MachineInstr.
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
@ DwarfCFI
DWARF-like instruction based exceptions.
void initializeX86PreAMXConfigPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.