LLVM 18.0.0git
X86TargetMachine.cpp
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1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86 specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86TargetMachine.h"
16#include "X86.h"
18#include "X86MacroFusion.h"
19#include "X86Subtarget.h"
20#include "X86TargetObjectFile.h"
22#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringRef.h"
35#include "llvm/CodeGen/Passes.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/DataLayout.h"
40#include "llvm/IR/Function.h"
41#include "llvm/MC/MCAsmInfo.h"
43#include "llvm/Pass.h"
51#include <memory>
52#include <optional>
53#include <string>
54
55using namespace llvm;
56
57static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58 cl::desc("Enable the machine combiner pass"),
59 cl::init(true), cl::Hidden);
60
61static cl::opt<bool>
62 EnableTileRAPass("x86-tile-ra",
63 cl::desc("Enable the tile register allocation pass"),
64 cl::init(true), cl::Hidden);
65
67 // Register the target.
70
106}
107
108static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
109 if (TT.isOSBinFormatMachO()) {
110 if (TT.getArch() == Triple::x86_64)
111 return std::make_unique<X86_64MachoTargetObjectFile>();
112 return std::make_unique<TargetLoweringObjectFileMachO>();
113 }
114
115 if (TT.isOSBinFormatCOFF())
116 return std::make_unique<TargetLoweringObjectFileCOFF>();
117 return std::make_unique<X86ELFTargetObjectFile>();
118}
119
120static std::string computeDataLayout(const Triple &TT) {
121 // X86 is little endian
122 std::string Ret = "e";
123
125 // X86 and x32 have 32 bit pointers.
126 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
127 Ret += "-p:32:32";
128
129 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
130 Ret += "-p270:32:32-p271:32:32-p272:64:64";
131
132 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
133 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
134 Ret += "-i64:64";
135 else if (TT.isOSIAMCU())
136 Ret += "-i64:32-f64:32";
137 else
138 Ret += "-f64:32:64";
139
140 // Some ABIs align long double to 128 bits, others to 32.
141 if (TT.isOSNaCl() || TT.isOSIAMCU())
142 ; // No f80
143 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
144 Ret += "-f80:128";
145 else
146 Ret += "-f80:32";
147
148 if (TT.isOSIAMCU())
149 Ret += "-f128:32";
150
151 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
152 if (TT.isArch64Bit())
153 Ret += "-n8:16:32:64";
154 else
155 Ret += "-n8:16:32";
156
157 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
158 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
159 Ret += "-a:0:32-S32";
160 else
161 Ret += "-S128";
162
163 return Ret;
164}
165
166static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
167 std::optional<Reloc::Model> RM) {
168 bool is64Bit = TT.getArch() == Triple::x86_64;
169 if (!RM) {
170 // JIT codegen should use static relocations by default, since it's
171 // typically executed in process and not relocatable.
172 if (JIT)
173 return Reloc::Static;
174
175 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
176 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
177 // use static relocation model by default.
178 if (TT.isOSDarwin()) {
179 if (is64Bit)
180 return Reloc::PIC_;
181 return Reloc::DynamicNoPIC;
182 }
183 if (TT.isOSWindows() && is64Bit)
184 return Reloc::PIC_;
185 return Reloc::Static;
186 }
187
188 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
189 // is defined as a model for code which may be used in static or dynamic
190 // executables but not necessarily a shared library. On X86-32 we just
191 // compile in -static mode, in x86-64 we use PIC.
192 if (*RM == Reloc::DynamicNoPIC) {
193 if (is64Bit)
194 return Reloc::PIC_;
195 if (!TT.isOSDarwin())
196 return Reloc::Static;
197 }
198
199 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
200 // the Mach-O file format doesn't support it.
201 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
202 return Reloc::PIC_;
203
204 return *RM;
205}
206
207static CodeModel::Model
208getEffectiveX86CodeModel(std::optional<CodeModel::Model> CM, bool JIT,
209 bool Is64Bit) {
210 if (CM) {
211 if (*CM == CodeModel::Tiny)
212 report_fatal_error("Target does not support the tiny CodeModel", false);
213 return *CM;
214 }
215 if (JIT)
216 return Is64Bit ? CodeModel::Large : CodeModel::Small;
217 return CodeModel::Small;
218}
219
220/// Create an X86 target.
221///
223 StringRef CPU, StringRef FS,
224 const TargetOptions &Options,
225 std::optional<Reloc::Model> RM,
226 std::optional<CodeModel::Model> CM,
227 CodeGenOptLevel OL, bool JIT)
229 T, computeDataLayout(TT), TT, CPU, FS, Options,
230 getEffectiveRelocModel(TT, JIT, RM),
231 getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
232 OL),
233 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
234 // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
235 // the calling function, and TrapUnreachable is an easy way to get that.
236 if (TT.isPS() || TT.isOSBinFormatMachO()) {
237 this->Options.TrapUnreachable = true;
238 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
239 }
240
241 setMachineOutliner(true);
242
243 // x86 supports the debug entry values.
245
246 initAsmInfo();
247}
248
250
251const X86Subtarget *
253 Attribute CPUAttr = F.getFnAttribute("target-cpu");
254 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
255 Attribute FSAttr = F.getFnAttribute("target-features");
256
257 StringRef CPU =
258 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
259 // "x86-64" is a default target setting for many front ends. In these cases,
260 // they actually request for "generic" tuning unless the "tune-cpu" was
261 // specified.
262 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
263 : CPU == "x86-64" ? "generic"
264 : (StringRef)CPU;
265 StringRef FS =
266 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
267
269 // The additions here are ordered so that the definitely short strings are
270 // added first so we won't exceed the small size. We append the
271 // much longer FS string at the end so that we only heap allocate at most
272 // one time.
273
274 // Extract prefer-vector-width attribute.
275 unsigned PreferVectorWidthOverride = 0;
276 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
277 if (PreferVecWidthAttr.isValid()) {
278 StringRef Val = PreferVecWidthAttr.getValueAsString();
279 unsigned Width;
280 if (!Val.getAsInteger(0, Width)) {
281 Key += 'p';
282 Key += Val;
283 PreferVectorWidthOverride = Width;
284 }
285 }
286
287 // Extract min-legal-vector-width attribute.
288 unsigned RequiredVectorWidth = UINT32_MAX;
289 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
290 if (MinLegalVecWidthAttr.isValid()) {
291 StringRef Val = MinLegalVecWidthAttr.getValueAsString();
292 unsigned Width;
293 if (!Val.getAsInteger(0, Width)) {
294 Key += 'm';
295 Key += Val;
296 RequiredVectorWidth = Width;
297 }
298 }
299
300 // Add CPU to the Key.
301 Key += CPU;
302
303 // Add tune CPU to the Key.
304 Key += TuneCPU;
305
306 // Keep track of the start of the feature portion of the string.
307 unsigned FSStart = Key.size();
308
309 // FIXME: This is related to the code below to reset the target options,
310 // we need to know whether or not the soft float flag is set on the
311 // function before we can generate a subtarget. We also need to use
312 // it as a key for the subtarget since that can be the only difference
313 // between two functions.
314 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
315 // If the soft float attribute is set on the function turn on the soft float
316 // subtarget feature.
317 if (SoftFloat)
318 Key += FS.empty() ? "+soft-float" : "+soft-float,";
319
320 Key += FS;
321
322 // We may have added +soft-float to the features so move the StringRef to
323 // point to the full string in the Key.
324 FS = Key.substr(FSStart);
325
326 auto &I = SubtargetMap[Key];
327 if (!I) {
328 // This needs to be done before we create a new subtarget since any
329 // creation will depend on the TM and the code generation flags on the
330 // function that reside in TargetOptions.
332 I = std::make_unique<X86Subtarget>(
333 TargetTriple, CPU, TuneCPU, FS, *this,
334 MaybeAlign(F.getParent()->getOverrideStackAlignment()),
335 PreferVectorWidthOverride, RequiredVectorWidth);
336 }
337 return I.get();
338}
339
341 unsigned DestAS) const {
342 assert(SrcAS != DestAS && "Expected different address spaces!");
343 if (getPointerSize(SrcAS) != getPointerSize(DestAS))
344 return false;
345 return SrcAS < 256 && DestAS < 256;
346}
347
348//===----------------------------------------------------------------------===//
349// X86 TTI query.
350//===----------------------------------------------------------------------===//
351
354 return TargetTransformInfo(X86TTIImpl(this, F));
355}
356
357//===----------------------------------------------------------------------===//
358// Pass Pipeline Configuration
359//===----------------------------------------------------------------------===//
360
361namespace {
362
363/// X86 Code Generator Pass Configuration Options.
364class X86PassConfig : public TargetPassConfig {
365public:
366 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
367 : TargetPassConfig(TM, PM) {}
368
369 X86TargetMachine &getX86TargetMachine() const {
370 return getTM<X86TargetMachine>();
371 }
372
374 createMachineScheduler(MachineSchedContext *C) const override {
377 return DAG;
378 }
379
381 createPostMachineScheduler(MachineSchedContext *C) const override {
384 return DAG;
385 }
386
387 void addIRPasses() override;
388 bool addInstSelector() override;
389 bool addIRTranslator() override;
390 bool addLegalizeMachineIR() override;
391 bool addRegBankSelect() override;
392 bool addGlobalInstructionSelect() override;
393 bool addILPOpts() override;
394 bool addPreISel() override;
395 void addMachineSSAOptimization() override;
396 void addPreRegAlloc() override;
397 bool addPostFastRegAllocRewrite() override;
398 void addPostRegAlloc() override;
399 void addPreEmitPass() override;
400 void addPreEmitPass2() override;
401 void addPreSched2() override;
402 bool addRegAssignAndRewriteOptimized() override;
403
404 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
405};
406
407class X86ExecutionDomainFix : public ExecutionDomainFix {
408public:
409 static char ID;
410 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
411 StringRef getPassName() const override {
412 return "X86 Execution Dependency Fix";
413 }
414};
415char X86ExecutionDomainFix::ID;
416
417} // end anonymous namespace
418
419INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
420 "X86 Execution Domain Fix", false, false)
422INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
423 "X86 Execution Domain Fix", false, false)
424
426 return new X86PassConfig(*this, PM);
427}
428
430 BumpPtrAllocator &Allocator, const Function &F,
431 const TargetSubtargetInfo *STI) const {
432 return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,
433 STI);
434}
435
436void X86PassConfig::addIRPasses() {
437 addPass(createAtomicExpandPass());
438
439 // We add both pass anyway and when these two passes run, we skip the pass
440 // based on the option level and option attribute.
442 addPass(createX86LowerAMXTypePass());
443
445
446 if (TM->getOptLevel() != CodeGenOptLevel::None) {
449 }
450
451 // Add passes that handle indirect branch removal and insertion of a retpoline
452 // thunk. These will be a no-op unless a function subtarget has the retpoline
453 // feature enabled.
455
456 // Add Control Flow Guard checks.
457 const Triple &TT = TM->getTargetTriple();
458 if (TT.isOSWindows()) {
459 if (TT.getArch() == Triple::x86_64) {
460 addPass(createCFGuardDispatchPass());
461 } else {
462 addPass(createCFGuardCheckPass());
463 }
464 }
465
466 if (TM->Options.JMCInstrument)
467 addPass(createJMCInstrumenterPass());
468}
469
470bool X86PassConfig::addInstSelector() {
471 // Install an instruction selector.
472 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
473
474 // For ELF, cleanup any local-dynamic TLS accesses.
475 if (TM->getTargetTriple().isOSBinFormatELF() &&
476 getOptLevel() != CodeGenOptLevel::None)
478
481 return false;
482}
483
484bool X86PassConfig::addIRTranslator() {
485 addPass(new IRTranslator(getOptLevel()));
486 return false;
487}
488
489bool X86PassConfig::addLegalizeMachineIR() {
490 addPass(new Legalizer());
491 return false;
492}
493
494bool X86PassConfig::addRegBankSelect() {
495 addPass(new RegBankSelect());
496 return false;
497}
498
499bool X86PassConfig::addGlobalInstructionSelect() {
500 addPass(new InstructionSelect(getOptLevel()));
501 return false;
502}
503
504bool X86PassConfig::addILPOpts() {
505 addPass(&EarlyIfConverterID);
507 addPass(&MachineCombinerID);
509 return true;
510}
511
512bool X86PassConfig::addPreISel() {
513 // Only add this pass for 32-bit x86 Windows.
514 const Triple &TT = TM->getTargetTriple();
515 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
516 addPass(createX86WinEHStatePass());
517 return true;
518}
519
520void X86PassConfig::addPreRegAlloc() {
521 if (getOptLevel() != CodeGenOptLevel::None) {
522 addPass(&LiveRangeShrinkID);
523 addPass(createX86FixupSetCC());
524 addPass(createX86OptimizeLEAs());
527 }
528
532
533 if (getOptLevel() != CodeGenOptLevel::None)
535 else
537}
538
539void X86PassConfig::addMachineSSAOptimization() {
542}
543
544void X86PassConfig::addPostRegAlloc() {
547 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
548 // to using the Speculative Execution Side Effect Suppression pass for
549 // mitigation. This is to prevent slow downs due to
550 // analyses needed by the LVIHardening pass when compiling at -O0.
551 if (getOptLevel() != CodeGenOptLevel::None)
553}
554
555void X86PassConfig::addPreSched2() {
556 addPass(createX86ExpandPseudoPass());
557 addPass(createKCFIPass());
558}
559
560void X86PassConfig::addPreEmitPass() {
561 if (getOptLevel() != CodeGenOptLevel::None) {
562 addPass(new X86ExecutionDomainFix());
563 addPass(createBreakFalseDeps());
564 }
565
567
569
570 if (getOptLevel() != CodeGenOptLevel::None) {
571 addPass(createX86FixupBWInsts());
573 addPass(createX86FixupLEAs());
574 addPass(createX86FixupInstTuning());
576 }
577 addPass(createX86EvexToVexInsts());
581}
582
583void X86PassConfig::addPreEmitPass2() {
584 const Triple &TT = TM->getTargetTriple();
585 const MCAsmInfo *MAI = TM->getMCAsmInfo();
586
587 // The X86 Speculative Execution Pass must run after all control
588 // flow graph modifying passes. As a result it was listed to run right before
589 // the X86 Retpoline Thunks pass. The reason it must run after control flow
590 // graph modifications is that the model of LFENCE in LLVM has to be updated
591 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
592 // placement of this pass was hand checked to ensure that the subsequent
593 // passes don't move the code around the LFENCEs in a way that will hurt the
594 // correctness of this pass. This placement has been shown to work based on
595 // hand inspection of the codegen output.
598 addPass(createX86ReturnThunksPass());
599
600 // Insert extra int3 instructions after trailing call instructions to avoid
601 // issues in the unwinder.
602 if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
604
605 // Verify basic block incoming and outgoing cfa offset and register values and
606 // correct CFA calculation rule where needed by inserting appropriate CFI
607 // instructions.
608 if (!TT.isOSDarwin() &&
609 (!TT.isOSWindows() ||
611 addPass(createCFIInstrInserter());
612
613 if (TT.isOSWindows()) {
614 // Identify valid longjmp targets for Windows Control Flow Guard.
615 addPass(createCFGuardLongjmpPass());
616 // Identify valid eh continuation targets for Windows EHCont Guard.
618 }
620
621 // Insert pseudo probe annotation for callsite profiling
622 addPass(createPseudoProbeInserter());
623
624 // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,
625 // also CALL_RVMARKER.
626 addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {
627 // Only run bundle expansion if the module uses kcfi, or there are relevant
628 // ObjC runtime functions present in the module.
629 const Function &F = MF.getFunction();
630 const Module *M = F.getParent();
631 return M->getModuleFlag("kcfi") ||
632 (TT.isOSDarwin() &&
633 (M->getFunction("objc_retainAutoreleasedReturnValue") ||
634 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));
635 }));
636}
637
638bool X86PassConfig::addPostFastRegAllocRewrite() {
640 return true;
641}
642
643std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
644 return getStandardCSEConfigForOpt(TM->getOptLevel());
645}
646
648 const TargetRegisterClass &RC) {
649 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
650}
651
652bool X86PassConfig::addRegAssignAndRewriteOptimized() {
653 // Don't support tile RA when RA is specified by command line "-regalloc".
654 if (!isCustomizedRegAlloc() && EnableTileRAPass) {
655 // Allocate tile register first.
657 addPass(createX86TileConfigPass());
658 }
660}
Falkor HW Prefetch Fix
arm execution domain fix
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallString class.
speculative execution
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
static bool is64Bit(const char *name)
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(std::optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, std::optional< Reloc::Model > RM)
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:169
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:781
Function & getFunction()
Return the LLVM function that this machine code represents.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:474
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
void setMachineOutliner(bool Enable)
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
@ X86
Windows x64, Windows Itanium (IA-64)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
FunctionPass * createIndirectBrExpandPass()
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86PartialReductionPass(PassRegistry &)
void initializeX86CallFrameOptimizationPass(PassRegistry &)
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86ArgumentStackSlotPassPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
@ DwarfCFI
DWARF-like instruction based exceptions.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Target & getTheX86_32Target()
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:310
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition: CSEInfo.cpp:79
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void initializeX86ExpandPseudoPass(PassRegistry &)
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createX86ArgumentStackSlotPass()
void initializeX86PreTileConfigPass(PassRegistry &)
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
void initializeX86DomainReassignmentPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
void initializeX86AvoidSFBPassPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86FastPreTileConfigPass(PassRegistry &)
FunctionPass * createX86SpeculativeLoadHardeningPass()
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
void initializeX86FixupSetCCPassPass(PassRegistry &)
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
char & LiveRangeShrinkID
LiveRangeShrink pass.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
void initializeEvexToVexInstPassPass(PassRegistry &)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
FunctionPass * createX86FixupInstTuning()
Return a pass that replaces equivalent slower instructions with faster ones.
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
void initializeX86LowerTileCopyPass(PassRegistry &)
void initializeX86OptimizeLEAPassPass(PassRegistry &)
void initializeX86PreAMXConfigPassPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
void initializeKCFIPass(PassRegistry &)
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:306
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeX86DAGToDAGISelPass(PassRegistry &)
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
Target & getTheX86_64Target()
void initializePseudoProbeInserterPass(PassRegistry &)
FunctionPass * createX86FixupVectorConstants()
Return a pass that reduces the size of vector constant pool loads.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
void initializeX86ReturnThunksPass(PassRegistry &)
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
void initializeFixupLEAPassPass(PassRegistry &)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
RegisterTargetMachine - Helper template for registering a target machine implementation,...