LLVM  13.0.0git
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56  cl::desc("Enable the machine combiner pass"),
57  cl::init(true), cl::Hidden);
58 
60  // Register the target.
63 
93 }
94 
95 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
96  if (TT.isOSBinFormatMachO()) {
97  if (TT.getArch() == Triple::x86_64)
98  return std::make_unique<X86_64MachoTargetObjectFile>();
99  return std::make_unique<TargetLoweringObjectFileMachO>();
100  }
101 
102  if (TT.isOSBinFormatCOFF())
103  return std::make_unique<TargetLoweringObjectFileCOFF>();
104  return std::make_unique<X86ELFTargetObjectFile>();
105 }
106 
107 static std::string computeDataLayout(const Triple &TT) {
108  // X86 is little endian
109  std::string Ret = "e";
110 
112  // X86 and x32 have 32 bit pointers.
113  if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
114  Ret += "-p:32:32";
115 
116  // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
117  Ret += "-p270:32:32-p271:32:32-p272:64:64";
118 
119  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
120  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
121  Ret += "-i64:64";
122  else if (TT.isOSIAMCU())
123  Ret += "-i64:32-f64:32";
124  else
125  Ret += "-f64:32:64";
126 
127  // Some ABIs align long double to 128 bits, others to 32.
128  if (TT.isOSNaCl() || TT.isOSIAMCU())
129  ; // No f80
130  else if (TT.isArch64Bit() || TT.isOSDarwin())
131  Ret += "-f80:128";
132  else
133  Ret += "-f80:32";
134 
135  if (TT.isOSIAMCU())
136  Ret += "-f128:32";
137 
138  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
139  if (TT.isArch64Bit())
140  Ret += "-n8:16:32:64";
141  else
142  Ret += "-n8:16:32";
143 
144  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
145  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
146  Ret += "-a:0:32-S32";
147  else
148  Ret += "-S128";
149 
150  return Ret;
151 }
152 
154  bool JIT,
156  bool is64Bit = TT.getArch() == Triple::x86_64;
157  if (!RM.hasValue()) {
158  // JIT codegen should use static relocations by default, since it's
159  // typically executed in process and not relocatable.
160  if (JIT)
161  return Reloc::Static;
162 
163  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
164  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
165  // use static relocation model by default.
166  if (TT.isOSDarwin()) {
167  if (is64Bit)
168  return Reloc::PIC_;
169  return Reloc::DynamicNoPIC;
170  }
171  if (TT.isOSWindows() && is64Bit)
172  return Reloc::PIC_;
173  return Reloc::Static;
174  }
175 
176  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
177  // is defined as a model for code which may be used in static or dynamic
178  // executables but not necessarily a shared library. On X86-32 we just
179  // compile in -static mode, in x86-64 we use PIC.
180  if (*RM == Reloc::DynamicNoPIC) {
181  if (is64Bit)
182  return Reloc::PIC_;
183  if (!TT.isOSDarwin())
184  return Reloc::Static;
185  }
186 
187  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
188  // the Mach-O file format doesn't support it.
189  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
190  return Reloc::PIC_;
191 
192  return *RM;
193 }
194 
196  bool JIT, bool Is64Bit) {
197  if (CM) {
198  if (*CM == CodeModel::Tiny)
199  report_fatal_error("Target does not support the tiny CodeModel", false);
200  return *CM;
201  }
202  if (JIT)
203  return Is64Bit ? CodeModel::Large : CodeModel::Small;
204  return CodeModel::Small;
205 }
206 
207 /// Create an X86 target.
208 ///
210  StringRef CPU, StringRef FS,
211  const TargetOptions &Options,
214  CodeGenOpt::Level OL, bool JIT)
216  T, computeDataLayout(TT), TT, CPU, FS, Options,
218  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
219  OL),
220  TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
221  // On PS4, the "return address" of a 'noreturn' call must still be within
222  // the calling function, and TrapUnreachable is an easy way to get that.
223  if (TT.isPS4() || TT.isOSBinFormatMachO()) {
224  this->Options.TrapUnreachable = true;
225  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
226  }
227 
228  setMachineOutliner(true);
229 
230  // x86 supports the debug entry values.
232 
233  initAsmInfo();
234 }
235 
237 
238 const X86Subtarget *
240  Attribute CPUAttr = F.getFnAttribute("target-cpu");
241  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
242  Attribute FSAttr = F.getFnAttribute("target-features");
243 
244  StringRef CPU =
245  CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
246  StringRef TuneCPU =
247  TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
248  StringRef FS =
249  FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
250 
252  // The additions here are ordered so that the definitely short strings are
253  // added first so we won't exceed the small size. We append the
254  // much longer FS string at the end so that we only heap allocate at most
255  // one time.
256 
257  // Extract prefer-vector-width attribute.
258  unsigned PreferVectorWidthOverride = 0;
259  Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
260  if (PreferVecWidthAttr.isValid()) {
261  StringRef Val = PreferVecWidthAttr.getValueAsString();
262  unsigned Width;
263  if (!Val.getAsInteger(0, Width)) {
264  Key += 'p';
265  Key += Val;
266  PreferVectorWidthOverride = Width;
267  }
268  }
269 
270  // Extract min-legal-vector-width attribute.
271  unsigned RequiredVectorWidth = UINT32_MAX;
272  Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
273  if (MinLegalVecWidthAttr.isValid()) {
274  StringRef Val = MinLegalVecWidthAttr.getValueAsString();
275  unsigned Width;
276  if (!Val.getAsInteger(0, Width)) {
277  Key += 'm';
278  Key += Val;
279  RequiredVectorWidth = Width;
280  }
281  }
282 
283  // Add CPU to the Key.
284  Key += CPU;
285 
286  // Add tune CPU to the Key.
287  Key += TuneCPU;
288 
289  // Keep track of the start of the feature portion of the string.
290  unsigned FSStart = Key.size();
291 
292  // FIXME: This is related to the code below to reset the target options,
293  // we need to know whether or not the soft float flag is set on the
294  // function before we can generate a subtarget. We also need to use
295  // it as a key for the subtarget since that can be the only difference
296  // between two functions.
297  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
298  // If the soft float attribute is set on the function turn on the soft float
299  // subtarget feature.
300  if (SoftFloat)
301  Key += FS.empty() ? "+soft-float" : "+soft-float,";
302 
303  Key += FS;
304 
305  // We may have added +soft-float to the features so move the StringRef to
306  // point to the full string in the Key.
307  FS = Key.substr(FSStart);
308 
309  auto &I = SubtargetMap[Key];
310  if (!I) {
311  // This needs to be done before we create a new subtarget since any
312  // creation will depend on the TM and the code generation flags on the
313  // function that reside in TargetOptions.
315  I = std::make_unique<X86Subtarget>(
316  TargetTriple, CPU, TuneCPU, FS, *this,
317  MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
318  RequiredVectorWidth);
319  }
320  return I.get();
321 }
322 
324  unsigned DestAS) const {
325  assert(SrcAS != DestAS && "Expected different address spaces!");
326  if (getPointerSize(SrcAS) != getPointerSize(DestAS))
327  return false;
328  return SrcAS < 256 && DestAS < 256;
329 }
330 
331 //===----------------------------------------------------------------------===//
332 // X86 TTI query.
333 //===----------------------------------------------------------------------===//
334 
337  return TargetTransformInfo(X86TTIImpl(this, F));
338 }
339 
340 //===----------------------------------------------------------------------===//
341 // Pass Pipeline Configuration
342 //===----------------------------------------------------------------------===//
343 
344 namespace {
345 
346 /// X86 Code Generator Pass Configuration Options.
347 class X86PassConfig : public TargetPassConfig {
348 public:
349  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
350  : TargetPassConfig(TM, PM) {}
351 
352  X86TargetMachine &getX86TargetMachine() const {
353  return getTM<X86TargetMachine>();
354  }
355 
357  createMachineScheduler(MachineSchedContext *C) const override {
360  return DAG;
361  }
362 
364  createPostMachineScheduler(MachineSchedContext *C) const override {
367  return DAG;
368  }
369 
370  void addIRPasses() override;
371  bool addInstSelector() override;
372  bool addIRTranslator() override;
373  bool addLegalizeMachineIR() override;
374  bool addRegBankSelect() override;
375  bool addGlobalInstructionSelect() override;
376  bool addILPOpts() override;
377  bool addPreISel() override;
378  void addMachineSSAOptimization() override;
379  void addPreRegAlloc() override;
380  bool addPostFastRegAllocRewrite() override;
381  void addPostRegAlloc() override;
382  void addPreEmitPass() override;
383  void addPreEmitPass2() override;
384  void addPreSched2() override;
385  bool addPreRewrite() override;
386 
387  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
388 };
389 
390 class X86ExecutionDomainFix : public ExecutionDomainFix {
391 public:
392  static char ID;
393  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
394  StringRef getPassName() const override {
395  return "X86 Execution Dependency Fix";
396  }
397 };
399 
400 } // end anonymous namespace
401 
402 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
403  "X86 Execution Domain Fix", false, false)
405 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
406  "X86 Execution Domain Fix", false, false)
407 
409  return new X86PassConfig(*this, PM);
410 }
411 
412 void X86PassConfig::addIRPasses() {
413  addPass(createAtomicExpandPass());
414 
415  // We add both pass anyway and when these two passes run, we skip the pass
416  // based on the option level and option attribute.
418  addPass(createX86LowerAMXTypePass());
419 
420  if (TM->getOptLevel() == CodeGenOpt::None)
421  addPass(createX86PreAMXConfigPass());
422 
424 
425  if (TM->getOptLevel() != CodeGenOpt::None) {
426  addPass(createInterleavedAccessPass());
428  }
429 
430  // Add passes that handle indirect branch removal and insertion of a retpoline
431  // thunk. These will be a no-op unless a function subtarget has the retpoline
432  // feature enabled.
433  addPass(createIndirectBrExpandPass());
434 
435  // Add Control Flow Guard checks.
436  const Triple &TT = TM->getTargetTriple();
437  if (TT.isOSWindows()) {
438  if (TT.getArch() == Triple::x86_64) {
439  addPass(createCFGuardDispatchPass());
440  } else {
441  addPass(createCFGuardCheckPass());
442  }
443  }
444 }
445 
446 bool X86PassConfig::addInstSelector() {
447  // Install an instruction selector.
448  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
449 
450  // For ELF, cleanup any local-dynamic TLS accesses.
451  if (TM->getTargetTriple().isOSBinFormatELF() &&
452  getOptLevel() != CodeGenOpt::None)
454 
455  addPass(createX86GlobalBaseRegPass());
456  return false;
457 }
458 
459 bool X86PassConfig::addIRTranslator() {
460  addPass(new IRTranslator(getOptLevel()));
461  return false;
462 }
463 
464 bool X86PassConfig::addLegalizeMachineIR() {
465  addPass(new Legalizer());
466  return false;
467 }
468 
469 bool X86PassConfig::addRegBankSelect() {
470  addPass(new RegBankSelect());
471  return false;
472 }
473 
474 bool X86PassConfig::addGlobalInstructionSelect() {
475  addPass(new InstructionSelect(getOptLevel()));
476  return false;
477 }
478 
479 bool X86PassConfig::addILPOpts() {
480  addPass(&EarlyIfConverterID);
482  addPass(&MachineCombinerID);
483  addPass(createX86CmovConverterPass());
484  return true;
485 }
486 
487 bool X86PassConfig::addPreISel() {
488  // Only add this pass for 32-bit x86 Windows.
489  const Triple &TT = TM->getTargetTriple();
490  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
491  addPass(createX86WinEHStatePass());
492  return true;
493 }
494 
495 void X86PassConfig::addPreRegAlloc() {
496  if (getOptLevel() != CodeGenOpt::None) {
497  addPass(&LiveRangeShrinkID);
498  addPass(createX86FixupSetCC());
499  addPass(createX86OptimizeLEAs());
502  }
503 
506  addPass(createX86WinAllocaExpander());
507 
508  if (getOptLevel() != CodeGenOpt::None) {
509  addPass(createX86PreTileConfigPass());
510  }
511 }
512 
513 void X86PassConfig::addMachineSSAOptimization() {
516 }
517 
518 void X86PassConfig::addPostRegAlloc() {
519  addPass(createX86LowerTileCopyPass());
521  // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
522  // to using the Speculative Execution Side Effect Suppression pass for
523  // mitigation. This is to prevent slow downs due to
524  // analyses needed by the LVIHardening pass when compiling at -O0.
525  if (getOptLevel() != CodeGenOpt::None)
527 }
528 
529 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
530 
531 void X86PassConfig::addPreEmitPass() {
532  if (getOptLevel() != CodeGenOpt::None) {
533  addPass(new X86ExecutionDomainFix());
534  addPass(createBreakFalseDeps());
535  }
536 
538 
539  addPass(createX86IssueVZeroUpperPass());
540 
541  if (getOptLevel() != CodeGenOpt::None) {
542  addPass(createX86FixupBWInsts());
543  addPass(createX86PadShortFunctions());
544  addPass(createX86FixupLEAs());
545  }
546  addPass(createX86EvexToVexInsts());
548  addPass(createX86InsertPrefetchPass());
549  addPass(createX86InsertX87waitPass());
550 }
551 
552 void X86PassConfig::addPreEmitPass2() {
553  const Triple &TT = TM->getTargetTriple();
554  const MCAsmInfo *MAI = TM->getMCAsmInfo();
555 
556  // The X86 Speculative Execution Pass must run after all control
557  // flow graph modifying passes. As a result it was listed to run right before
558  // the X86 Retpoline Thunks pass. The reason it must run after control flow
559  // graph modifications is that the model of LFENCE in LLVM has to be updated
560  // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
561  // placement of this pass was hand checked to ensure that the subsequent
562  // passes don't move the code around the LFENCEs in a way that will hurt the
563  // correctness of this pass. This placement has been shown to work based on
564  // hand inspection of the codegen output.
566  addPass(createX86IndirectThunksPass());
567 
568  // Insert extra int3 instructions after trailing call instructions to avoid
569  // issues in the unwinder.
570  if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
572 
573  // Verify basic block incoming and outgoing cfa offset and register values and
574  // correct CFA calculation rule where needed by inserting appropriate CFI
575  // instructions.
576  if (!TT.isOSDarwin() &&
577  (!TT.isOSWindows() ||
579  addPass(createCFIInstrInserter());
580 
581  if (TT.isOSWindows()) {
582  // Identify valid longjmp targets for Windows Control Flow Guard.
583  addPass(createCFGuardLongjmpPass());
584  // Identify valid eh continuation targets for Windows EHCont Guard.
586  }
588 }
589 
590 bool X86PassConfig::addPostFastRegAllocRewrite() {
591  addPass(createX86FastTileConfigPass());
592  return true;
593 }
594 
595 bool X86PassConfig::addPreRewrite() {
596  addPass(createX86TileConfigPass());
597  return true;
598 }
599 
600 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
601  return getStandardCSEConfigForOpt(TM->getOptLevel());
602 }
llvm::createX86LowerAMXTypePass
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
Definition: X86LowerAMXType.cpp:686
llvm::createX86FlagsCopyLoweringPass
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
Definition: X86FlagsCopyLowering.cpp:140
llvm::createX86FixupLEAs
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
Definition: X86FixupLEAs.cpp:216
llvm::createX86PadShortFunctions
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
Definition: X86PadShortFunction.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:155
Optional.h
llvm::ARM::PredBlockMask::TT
@ TT
X86CallLowering.h
llvm::createX86AvoidTrailingCallPass
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
Definition: X86AvoidTrailingCall.cpp:63
llvm::ReachingDefAnalysis
This class provides the reaching def analysis.
Definition: ReachingDefAnalysis.h:69
CallLowering.h
X86Subtarget.h
llvm::TargetOptions
Definition: TargetOptions.h:113
llvm::createX86WinAllocaExpander
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
Definition: X86WinAllocaExpander.cpp:75
llvm::Function
Definition: Function.h:61
llvm::Attribute
Definition: Attributes.h:52
StringRef.h
Pass.h
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1005
llvm::initializeX86FastTileConfigPass
void initializeX86FastTileConfigPass(PassRegistry &)
llvm::Triple::x86
@ x86
Definition: Triple.h:83
llvm::createX86PreTileConfigPass
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
Definition: X86PreTileConfig.cpp:402
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:125
llvm::initializeEvexToVexInstPassPass
void initializeEvexToVexInstPassPass(PassRegistry &)
llvm::X86Subtarget
Definition: X86Subtarget.h:52
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::createX86IndirectThunksPass
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
Definition: X86IndirectThunks.cpp:254
llvm::X86TargetMachine::X86TargetMachine
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
Definition: X86TargetMachine.cpp:209
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:84
llvm::DataLayout::getManglingComponent
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:153
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:255
InstructionSelect.h
llvm::initializeX86ExpandPseudoPass
void initializeX86ExpandPseudoPass(PassRegistry &)
llvm::createCleanupLocalDynamicTLSPass
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
Definition: X86InstrInfo.cpp:8912
llvm::Optional< Reloc::Model >
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::ExecutionDomainFix
Definition: ExecutionDomainFix.h:116
getEffectiveX86CodeModel
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
Definition: X86TargetMachine.cpp:195
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
STLExtras.h
llvm::createX86TileConfigPass
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
Definition: X86TileConfig.cpp:196
llvm::createX86FixupSetCC
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
Definition: X86FixupSetCC.cpp:59
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::createX86FastTileConfigPass
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
Definition: X86FastTileConfig.cpp:304
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::createX86MacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
Definition: X86MacroFusion.cpp:70
CommandLine.h
X86.h
llvm::createX86CallFrameOptimization
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
Definition: X86CallFrameOptimization.cpp:638
fix
x86 execution domain fix
Definition: X86TargetMachine.cpp:405
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::X86TargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: X86TargetMachine.cpp:323
X86MacroFusion.h
llvm::createX86FloatingPointStackifierPass
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
Definition: X86FloatingPoint.cpp:311
SmallString.h
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:247
Fix
x86 execution domain X86 Execution Domain Fix
Definition: X86TargetMachine.cpp:406
llvm::Legalizer
Definition: Legalizer.h:31
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::createX86SpeculativeLoadHardeningPass
FunctionPass * createX86SpeculativeLoadHardeningPass()
Definition: X86SpeculativeLoadHardening.cpp:2277
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:660
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
false
Definition: StackSlotColoring.cpp:142
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::createX86PartialReductionPass
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
Definition: X86PartialReduction.cpp:57
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3638
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1199
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:318
llvm::createX86LowerAMXIntrinsicsPass
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Definition: X86LowerAMXIntrinsics.cpp:677
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createCFIInstrInserter
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
llvm::createCFGuardDispatchPass
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:298
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::initializePseudoProbeInserterPass
void initializePseudoProbeInserterPass(PassRegistry &)
llvm::initializeX86SpeculativeLoadHardeningPassPass
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
llvm::initializeWinEHStatePassPass
void initializeWinEHStatePassPass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:508
llvm::createX86LowerTileCopyPass
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
Definition: X86LowerTileCopy.cpp:68
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::createX86LoadValueInjectionRetHardeningPass
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::createX86SpeculativeExecutionSideEffectSuppression
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
Definition: X86SpeculativeExecutionSideEffectSuppression.cpp:176
llvm::cl::opt< bool >
llvm::initializeX86LoadValueInjectionRetHardeningPassPass
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::getTheX86_32Target
Target & getTheX86_32Target()
Definition: X86TargetInfo.cpp:13
llvm::createX86DiscriminateMemOpsPass
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
Definition: X86DiscriminateMemOps.cpp:182
X86MCTargetDesc.h
llvm::createX86WinEHStatePass
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
Definition: X86WinEHState.cpp:114
llvm::initializeFPSPass
void initializeFPSPass(PassRegistry &)
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3485
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:525
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
X86LegalizerInfo.h
llvm::createX86DomainReassignmentPass
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
LLVMInitializeX86Target
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
Definition: X86TargetMachine.cpp:59
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:259
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::createX86InsertPrefetchPass
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
Definition: X86InsertPrefetch.cpp:251
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:810
llvm::createX86AvoidStoreForwardingBlocks
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
Definition: X86AvoidStoreForwardingBlocks.cpp:129
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::createX86ISelDag
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
Definition: X86ISelDAGToDAG.cpp:6001
llvm::TargetOptions::StackAlignmentOverride
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
Definition: TargetOptions.h:205
llvm::LiveRangeShrinkID
char & LiveRangeShrinkID
LiveRangeShrink pass.
Definition: LiveRangeShrink.cpp:65
TargetPassConfig.h
llvm::initializeX86LowerAMXTypeLegacyPassPass
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::initializeX86AvoidTrailingCallPassPass
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:294
llvm::createX86ExpandPseudoPass
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
Definition: X86ExpandPseudo.cpp:759
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::createX86FixupBWInsts
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
Definition: X86FixupBWInsts.cpp:157
llvm::initializeX86LowerTileCopyPass
void initializeX86LowerTileCopyPass(PassRegistry &)
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::X86TargetMachine::getSubtargetImpl
const X86Subtarget * getSubtargetImpl() const =delete
Triple.h
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:469
llvm::createX86PreAMXConfigPass
FunctionPass * createX86PreAMXConfigPass()
The pass insert tile config intrinsics for AMX fast register allocation.
Definition: X86PreAMXConfig.cpp:420
MCAsmInfo.h
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
X86TargetTransformInfo.h
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
IRTranslator.h
EnableMachineCombinerPass
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::createIndirectBrExpandPass
FunctionPass * createIndirectBrExpandPass()
Definition: IndirectBrExpandPass.cpp:81
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:39
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
llvm::createX86LoadValueInjectionLoadHardeningPass
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
Definition: X86LoadValueInjectionLoadHardening.cpp:814
Attributes.h
llvm::createBreakFalseDeps
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
Definition: BreakFalseDeps.cpp:105
llvm::X86TTIImpl
Definition: X86TargetTransformInfo.h:27
llvm::createX86EvexToVexInsts
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
Definition: X86EvexToVex.cpp:278
llvm::initializeFixupBWInstPassPass
void initializeFixupBWInstPassPass(PassRegistry &)
llvm::initializeFixupLEAPassPass
void initializeFixupLEAPassPass(PassRegistry &)
computeDataLayout
static std::string computeDataLayout(const Triple &TT)
Definition: X86TargetMachine.cpp:107
X86TargetMachine.h
llvm::initializeX86LowerAMXIntrinsicsLegacyPassPass
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1233
X86TargetObjectFile.h
RegBankSelect.h
Function.h
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: X86TargetMachine.cpp:95
llvm::createX86InsertX87waitPass
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
Definition: X86InsertWait.cpp:56
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:385
llvm::initializeX86SpeculativeExecutionSideEffectSuppressionPass
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
llvm::initializeX86TileConfigPass
void initializeX86TileConfigPass(PassRegistry &)
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::initializeX86LoadValueInjectionLoadHardeningPassPass
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
llvm::X86TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: X86TargetMachine.cpp:336
llvm::initializeX86CallFrameOptimizationPass
void initializeX86CallFrameOptimizationPass(PassRegistry &)
CodeGen.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:750
ExecutionDomainFix.h
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
Legalizer.h
MachineScheduler.h
llvm::initializeX86PartialReductionPass
void initializeX86PartialReductionPass(PassRegistry &)
llvm::initializeX86FixupSetCCPassPass
void initializeX86FixupSetCCPassPass(PassRegistry &)
llvm::createX86CmovConverterPass
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
Definition: X86CmovConversion.cpp:859
llvm::createX86IndirectBranchTrackingPass
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
Definition: X86IndirectBranchTracking.cpp:68
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:130
TargetTransformInfo.h
llvm::initializeX86AvoidSFBPassPass
void initializeX86AvoidSFBPassPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::initializeX86OptimizeLEAPassPass
void initializeX86OptimizeLEAPassPass(PassRegistry &)
llvm::initializeX86ExecutionDomainFixPass
void initializeX86ExecutionDomainFixPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::createX86GlobalBaseRegPass
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
Definition: X86InstrInfo.cpp:8798
llvm::X86TargetMachine::~X86TargetMachine
~X86TargetMachine() override
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::createX86OptimizeLEAs
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
Definition: X86OptimizeLEAs.cpp:315
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:253
llvm::initializeX86DomainReassignmentPass
void initializeX86DomainReassignmentPass(PassRegistry &)
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
execution
speculative execution
Definition: SpeculativeExecution.cpp:135
llvm::initializeX86FlagsCopyLoweringPassPass
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
llvm::createX86IssueVZeroUpperPass
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
Definition: X86VZeroUpper.cpp:116
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::TargetMachine::getPointerSize
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
Definition: TargetMachine.h:180
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
X86TargetInfo.h
TargetRegistry.h
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::initializeX86PreAMXConfigPassPass
void initializeX86PreAMXConfigPassPass(PassRegistry &)
llvm::initializeX86CmovConverterPassPass
void initializeX86CmovConverterPassPass(PassRegistry &)
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38