LLVM  16.0.0git
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
38 #include "llvm/CodeGen/Passes.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/TargetRegistry.h"
46 #include "llvm/Pass.h"
47 #include "llvm/Support/CodeGen.h"
53 #include <memory>
54 #include <optional>
55 #include <string>
56 
57 using namespace llvm;
58 
59 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
60  cl::desc("Enable the machine combiner pass"),
61  cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool>
64  EnableTileRAPass("x86-tile-ra",
65  cl::desc("Enable the tile register allocation pass"),
66  cl::init(true), cl::Hidden);
67 
69  // Register the target.
72 
106 }
107 
108 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
109  if (TT.isOSBinFormatMachO()) {
110  if (TT.getArch() == Triple::x86_64)
111  return std::make_unique<X86_64MachoTargetObjectFile>();
112  return std::make_unique<TargetLoweringObjectFileMachO>();
113  }
114 
115  if (TT.isOSBinFormatCOFF())
116  return std::make_unique<TargetLoweringObjectFileCOFF>();
117  return std::make_unique<X86ELFTargetObjectFile>();
118 }
119 
120 static std::string computeDataLayout(const Triple &TT) {
121  // X86 is little endian
122  std::string Ret = "e";
123 
125  // X86 and x32 have 32 bit pointers.
126  if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
127  Ret += "-p:32:32";
128 
129  // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
130  Ret += "-p270:32:32-p271:32:32-p272:64:64";
131 
132  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
133  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
134  Ret += "-i64:64";
135  else if (TT.isOSIAMCU())
136  Ret += "-i64:32-f64:32";
137  else
138  Ret += "-f64:32:64";
139 
140  // Some ABIs align long double to 128 bits, others to 32.
141  if (TT.isOSNaCl() || TT.isOSIAMCU())
142  ; // No f80
143  else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
144  Ret += "-f80:128";
145  else
146  Ret += "-f80:32";
147 
148  if (TT.isOSIAMCU())
149  Ret += "-f128:32";
150 
151  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
152  if (TT.isArch64Bit())
153  Ret += "-n8:16:32:64";
154  else
155  Ret += "-n8:16:32";
156 
157  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
158  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
159  Ret += "-a:0:32-S32";
160  else
161  Ret += "-S128";
162 
163  return Ret;
164 }
165 
167  std::optional<Reloc::Model> RM) {
168  bool is64Bit = TT.getArch() == Triple::x86_64;
169  if (!RM) {
170  // JIT codegen should use static relocations by default, since it's
171  // typically executed in process and not relocatable.
172  if (JIT)
173  return Reloc::Static;
174 
175  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
176  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
177  // use static relocation model by default.
178  if (TT.isOSDarwin()) {
179  if (is64Bit)
180  return Reloc::PIC_;
181  return Reloc::DynamicNoPIC;
182  }
183  if (TT.isOSWindows() && is64Bit)
184  return Reloc::PIC_;
185  return Reloc::Static;
186  }
187 
188  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
189  // is defined as a model for code which may be used in static or dynamic
190  // executables but not necessarily a shared library. On X86-32 we just
191  // compile in -static mode, in x86-64 we use PIC.
192  if (*RM == Reloc::DynamicNoPIC) {
193  if (is64Bit)
194  return Reloc::PIC_;
195  if (!TT.isOSDarwin())
196  return Reloc::Static;
197  }
198 
199  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
200  // the Mach-O file format doesn't support it.
201  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
202  return Reloc::PIC_;
203 
204  return *RM;
205 }
206 
207 static CodeModel::Model
208 getEffectiveX86CodeModel(std::optional<CodeModel::Model> CM, bool JIT,
209  bool Is64Bit) {
210  if (CM) {
211  if (*CM == CodeModel::Tiny)
212  report_fatal_error("Target does not support the tiny CodeModel", false);
213  return *CM;
214  }
215  if (JIT)
216  return Is64Bit ? CodeModel::Large : CodeModel::Small;
217  return CodeModel::Small;
218 }
219 
220 /// Create an X86 target.
221 ///
223  StringRef CPU, StringRef FS,
224  const TargetOptions &Options,
225  std::optional<Reloc::Model> RM,
226  std::optional<CodeModel::Model> CM,
227  CodeGenOpt::Level OL, bool JIT)
229  T, computeDataLayout(TT), TT, CPU, FS, Options,
231  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
232  OL),
233  TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
234  // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
235  // the calling function, and TrapUnreachable is an easy way to get that.
236  if (TT.isPS() || TT.isOSBinFormatMachO()) {
237  this->Options.TrapUnreachable = true;
238  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
239  }
240 
241  setMachineOutliner(true);
242 
243  // x86 supports the debug entry values.
245 
246  initAsmInfo();
247 }
248 
250 
251 const X86Subtarget *
253  Attribute CPUAttr = F.getFnAttribute("target-cpu");
254  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
255  Attribute FSAttr = F.getFnAttribute("target-features");
256 
257  StringRef CPU =
258  CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
259  // "x86-64" is a default target setting for many front ends. In these cases,
260  // they actually request for "generic" tuning unless the "tune-cpu" was
261  // specified.
262  StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
263  : CPU == "x86-64" ? "generic"
264  : (StringRef)CPU;
265  StringRef FS =
266  FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
267 
269  // The additions here are ordered so that the definitely short strings are
270  // added first so we won't exceed the small size. We append the
271  // much longer FS string at the end so that we only heap allocate at most
272  // one time.
273 
274  // Extract prefer-vector-width attribute.
275  unsigned PreferVectorWidthOverride = 0;
276  Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
277  if (PreferVecWidthAttr.isValid()) {
278  StringRef Val = PreferVecWidthAttr.getValueAsString();
279  unsigned Width;
280  if (!Val.getAsInteger(0, Width)) {
281  Key += 'p';
282  Key += Val;
283  PreferVectorWidthOverride = Width;
284  }
285  }
286 
287  // Extract min-legal-vector-width attribute.
288  unsigned RequiredVectorWidth = UINT32_MAX;
289  Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
290  if (MinLegalVecWidthAttr.isValid()) {
291  StringRef Val = MinLegalVecWidthAttr.getValueAsString();
292  unsigned Width;
293  if (!Val.getAsInteger(0, Width)) {
294  Key += 'm';
295  Key += Val;
296  RequiredVectorWidth = Width;
297  }
298  }
299 
300  // Add CPU to the Key.
301  Key += CPU;
302 
303  // Add tune CPU to the Key.
304  Key += TuneCPU;
305 
306  // Keep track of the start of the feature portion of the string.
307  unsigned FSStart = Key.size();
308 
309  // FIXME: This is related to the code below to reset the target options,
310  // we need to know whether or not the soft float flag is set on the
311  // function before we can generate a subtarget. We also need to use
312  // it as a key for the subtarget since that can be the only difference
313  // between two functions.
314  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
315  // If the soft float attribute is set on the function turn on the soft float
316  // subtarget feature.
317  if (SoftFloat)
318  Key += FS.empty() ? "+soft-float" : "+soft-float,";
319 
320  Key += FS;
321 
322  // We may have added +soft-float to the features so move the StringRef to
323  // point to the full string in the Key.
324  FS = Key.substr(FSStart);
325 
326  auto &I = SubtargetMap[Key];
327  if (!I) {
328  // This needs to be done before we create a new subtarget since any
329  // creation will depend on the TM and the code generation flags on the
330  // function that reside in TargetOptions.
332  I = std::make_unique<X86Subtarget>(
333  TargetTriple, CPU, TuneCPU, FS, *this,
334  MaybeAlign(F.getParent()->getOverrideStackAlignment()),
335  PreferVectorWidthOverride, RequiredVectorWidth);
336  }
337  return I.get();
338 }
339 
341  unsigned DestAS) const {
342  assert(SrcAS != DestAS && "Expected different address spaces!");
343  if (getPointerSize(SrcAS) != getPointerSize(DestAS))
344  return false;
345  return SrcAS < 256 && DestAS < 256;
346 }
347 
348 //===----------------------------------------------------------------------===//
349 // X86 TTI query.
350 //===----------------------------------------------------------------------===//
351 
354  return TargetTransformInfo(X86TTIImpl(this, F));
355 }
356 
357 //===----------------------------------------------------------------------===//
358 // Pass Pipeline Configuration
359 //===----------------------------------------------------------------------===//
360 
361 namespace {
362 
363 /// X86 Code Generator Pass Configuration Options.
364 class X86PassConfig : public TargetPassConfig {
365 public:
366  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
367  : TargetPassConfig(TM, PM) {}
368 
369  X86TargetMachine &getX86TargetMachine() const {
370  return getTM<X86TargetMachine>();
371  }
372 
374  createMachineScheduler(MachineSchedContext *C) const override {
377  return DAG;
378  }
379 
381  createPostMachineScheduler(MachineSchedContext *C) const override {
384  return DAG;
385  }
386 
387  void addIRPasses() override;
388  bool addInstSelector() override;
389  bool addIRTranslator() override;
390  bool addLegalizeMachineIR() override;
391  bool addRegBankSelect() override;
392  bool addGlobalInstructionSelect() override;
393  bool addILPOpts() override;
394  bool addPreISel() override;
395  void addMachineSSAOptimization() override;
396  void addPreRegAlloc() override;
397  bool addPostFastRegAllocRewrite() override;
398  void addPostRegAlloc() override;
399  void addPreEmitPass() override;
400  void addPreEmitPass2() override;
401  void addPreSched2() override;
402  bool addRegAssignAndRewriteOptimized() override;
403 
404  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
405 };
406 
407 class X86ExecutionDomainFix : public ExecutionDomainFix {
408 public:
409  static char ID;
410  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
411  StringRef getPassName() const override {
412  return "X86 Execution Dependency Fix";
413  }
414 };
416 
417 } // end anonymous namespace
418 
419 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
420  "X86 Execution Domain Fix", false, false)
422 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
423  "X86 Execution Domain Fix", false, false)
424 
426  return new X86PassConfig(*this, PM);
427 }
428 
429 void X86PassConfig::addIRPasses() {
430  addPass(createAtomicExpandPass());
431 
432  // We add both pass anyway and when these two passes run, we skip the pass
433  // based on the option level and option attribute.
435  addPass(createX86LowerAMXTypePass());
436 
438 
439  if (TM->getOptLevel() != CodeGenOpt::None) {
440  addPass(createInterleavedAccessPass());
442  }
443 
444  // Add passes that handle indirect branch removal and insertion of a retpoline
445  // thunk. These will be a no-op unless a function subtarget has the retpoline
446  // feature enabled.
447  addPass(createIndirectBrExpandPass());
448 
449  // Add Control Flow Guard checks.
450  const Triple &TT = TM->getTargetTriple();
451  if (TT.isOSWindows()) {
452  if (TT.getArch() == Triple::x86_64) {
453  addPass(createCFGuardDispatchPass());
454  } else {
455  addPass(createCFGuardCheckPass());
456  }
457  }
458 
459  if (TM->Options.JMCInstrument)
460  addPass(createJMCInstrumenterPass());
461 }
462 
463 bool X86PassConfig::addInstSelector() {
464  // Install an instruction selector.
465  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
466 
467  // For ELF, cleanup any local-dynamic TLS accesses.
468  if (TM->getTargetTriple().isOSBinFormatELF() &&
469  getOptLevel() != CodeGenOpt::None)
471 
472  addPass(createX86GlobalBaseRegPass());
473  return false;
474 }
475 
476 bool X86PassConfig::addIRTranslator() {
477  addPass(new IRTranslator(getOptLevel()));
478  return false;
479 }
480 
481 bool X86PassConfig::addLegalizeMachineIR() {
482  addPass(new Legalizer());
483  return false;
484 }
485 
486 bool X86PassConfig::addRegBankSelect() {
487  addPass(new RegBankSelect());
488  return false;
489 }
490 
491 bool X86PassConfig::addGlobalInstructionSelect() {
492  addPass(new InstructionSelect(getOptLevel()));
493  return false;
494 }
495 
496 bool X86PassConfig::addILPOpts() {
497  addPass(&EarlyIfConverterID);
499  addPass(&MachineCombinerID);
500  addPass(createX86CmovConverterPass());
501  return true;
502 }
503 
504 bool X86PassConfig::addPreISel() {
505  // Only add this pass for 32-bit x86 Windows.
506  const Triple &TT = TM->getTargetTriple();
507  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
508  addPass(createX86WinEHStatePass());
509  return true;
510 }
511 
512 void X86PassConfig::addPreRegAlloc() {
513  if (getOptLevel() != CodeGenOpt::None) {
514  addPass(&LiveRangeShrinkID);
515  addPass(createX86FixupSetCC());
516  addPass(createX86OptimizeLEAs());
519  }
520 
523  addPass(createX86DynAllocaExpander());
524 
525  if (getOptLevel() != CodeGenOpt::None)
526  addPass(createX86PreTileConfigPass());
527  else
529 }
530 
531 void X86PassConfig::addMachineSSAOptimization() {
534 }
535 
536 void X86PassConfig::addPostRegAlloc() {
537  addPass(createX86LowerTileCopyPass());
539  // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
540  // to using the Speculative Execution Side Effect Suppression pass for
541  // mitigation. This is to prevent slow downs due to
542  // analyses needed by the LVIHardening pass when compiling at -O0.
543  if (getOptLevel() != CodeGenOpt::None)
545 }
546 
547 void X86PassConfig::addPreSched2() {
548  addPass(createX86ExpandPseudoPass());
549  addPass(createX86KCFIPass());
550 }
551 
552 void X86PassConfig::addPreEmitPass() {
553  if (getOptLevel() != CodeGenOpt::None) {
554  addPass(new X86ExecutionDomainFix());
555  addPass(createBreakFalseDeps());
556  }
557 
559 
560  addPass(createX86IssueVZeroUpperPass());
561 
562  if (getOptLevel() != CodeGenOpt::None) {
563  addPass(createX86FixupBWInsts());
564  addPass(createX86PadShortFunctions());
565  addPass(createX86FixupLEAs());
566  }
567  addPass(createX86EvexToVexInsts());
569  addPass(createX86InsertPrefetchPass());
570  addPass(createX86InsertX87waitPass());
571 }
572 
573 void X86PassConfig::addPreEmitPass2() {
574  const Triple &TT = TM->getTargetTriple();
575  const MCAsmInfo *MAI = TM->getMCAsmInfo();
576 
577  // The X86 Speculative Execution Pass must run after all control
578  // flow graph modifying passes. As a result it was listed to run right before
579  // the X86 Retpoline Thunks pass. The reason it must run after control flow
580  // graph modifications is that the model of LFENCE in LLVM has to be updated
581  // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
582  // placement of this pass was hand checked to ensure that the subsequent
583  // passes don't move the code around the LFENCEs in a way that will hurt the
584  // correctness of this pass. This placement has been shown to work based on
585  // hand inspection of the codegen output.
587  addPass(createX86IndirectThunksPass());
588  addPass(createX86ReturnThunksPass());
589 
590  // Insert extra int3 instructions after trailing call instructions to avoid
591  // issues in the unwinder.
592  if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
594 
595  // Verify basic block incoming and outgoing cfa offset and register values and
596  // correct CFA calculation rule where needed by inserting appropriate CFI
597  // instructions.
598  if (!TT.isOSDarwin() &&
599  (!TT.isOSWindows() ||
601  addPass(createCFIInstrInserter());
602 
603  if (TT.isOSWindows()) {
604  // Identify valid longjmp targets for Windows Control Flow Guard.
605  addPass(createCFGuardLongjmpPass());
606  // Identify valid eh continuation targets for Windows EHCont Guard.
608  }
610 
611  // Insert pseudo probe annotation for callsite profiling
612  addPass(createPseudoProbeInserter());
613 
614  // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,
615  // also CALL_RVMARKER.
616  addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {
617  // Only run bundle expansion if the module uses kcfi, or there are relevant
618  // ObjC runtime functions present in the module.
619  const Function &F = MF.getFunction();
620  const Module *M = F.getParent();
621  return M->getModuleFlag("kcfi") ||
622  (TT.isOSDarwin() &&
623  (M->getFunction("objc_retainAutoreleasedReturnValue") ||
624  M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));
625  }));
626 }
627 
628 bool X86PassConfig::addPostFastRegAllocRewrite() {
629  addPass(createX86FastTileConfigPass());
630  return true;
631 }
632 
633 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
634  return getStandardCSEConfigForOpt(TM->getOptLevel());
635 }
636 
638  const TargetRegisterClass &RC) {
639  return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
640 }
641 
642 bool X86PassConfig::addRegAssignAndRewriteOptimized() {
643  // Don't support tile RA when RA is specified by command line "-regalloc".
644  if (!isCustomizedRegAlloc() && EnableTileRAPass) {
645  // Allocate tile register first.
647  addPass(createX86TileConfigPass());
648  }
650 }
llvm::createX86LowerAMXTypePass
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
Definition: X86LowerAMXType.cpp:1273
llvm::createJMCInstrumenterPass
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
llvm::createX86FlagsCopyLoweringPass
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
Definition: X86FlagsCopyLowering.cpp:140
onlyAllocateTileRegisters
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)
Definition: X86TargetMachine.cpp:637
llvm::createX86FixupLEAs
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
Definition: X86FixupLEAs.cpp:218
llvm::createX86PadShortFunctions
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
Definition: X86PadShortFunction.cpp:99
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::createGreedyRegisterAllocator
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
Definition: RegAllocGreedy.cpp:186
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::createX86DynAllocaExpander
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
Definition: X86DynAllocaExpander.cpp:75
Optional.h
llvm::ARM::PredBlockMask::TT
@ TT
X86CallLowering.h
llvm::X86TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: X86TargetMachine.cpp:353
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
llvm::createX86AvoidTrailingCallPass
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
Definition: X86AvoidTrailingCall.cpp:64
llvm::ReachingDefAnalysis
This class provides the reaching def analysis.
Definition: ReachingDefAnalysis.h:69
llvm::createX86KCFIPass
FunctionPass * createX86KCFIPass()
This pass inserts KCFI checks before indirect calls.
Definition: X86KCFI.cpp:55
llvm::initializeX86FastPreTileConfigPass
void initializeX86FastPreTileConfigPass(PassRegistry &)
CallLowering.h
X86Subtarget.h
llvm::TargetOptions
Definition: TargetOptions.h:124
T
llvm::Function
Definition: Function.h:60
llvm::Attribute
Definition: Attributes.h:66
StringRef.h
Pass.h
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1018
llvm::initializeX86FastTileConfigPass
void initializeX86FastTileConfigPass(PassRegistry &)
llvm::Triple::x86
@ x86
Definition: Triple.h:85
llvm::createX86PreTileConfigPass
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
Definition: X86PreTileConfig.cpp:412
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:150
llvm::initializeEvexToVexInstPassPass
void initializeEvexToVexInstPassPass(PassRegistry &)
llvm::X86Subtarget
Definition: X86Subtarget.h:52
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::createX86IndirectThunksPass
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
Definition: X86IndirectThunks.cpp:255
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
EnableTileRAPass
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:86
llvm::DataLayout::getManglingComponent
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:153
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:280
InstructionSelect.h
llvm::initializeX86ExpandPseudoPass
void initializeX86ExpandPseudoPass(PassRegistry &)
llvm::createCleanupLocalDynamicTLSPass
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
Definition: X86InstrInfo.cpp:9525
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::ExecutionDomainFix
Definition: ExecutionDomainFix.h:116
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
STLExtras.h
llvm::createX86TileConfigPass
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
Definition: X86TileConfig.cpp:201
llvm::initializeX86ReturnThunksPass
void initializeX86ReturnThunksPass(PassRegistry &)
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::createX86FixupSetCC
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
Definition: X86FixupSetCC.cpp:59
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::createX86FastTileConfigPass
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
Definition: X86FastTileConfig.cpp:186
getEffectiveX86CodeModel
static CodeModel::Model getEffectiveX86CodeModel(std::optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
Definition: X86TargetMachine.cpp:208
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
CSEInfo.h
llvm::createX86MacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
Definition: X86MacroFusion.cpp:71
CommandLine.h
X86.h
llvm::createX86CallFrameOptimization
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
Definition: X86CallFrameOptimization.cpp:638
fix
x86 execution domain fix
Definition: X86TargetMachine.cpp:422
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::X86TargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: X86TargetMachine.cpp:340
X86MacroFusion.h
llvm::createX86FloatingPointStackifierPass
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
Definition: X86FloatingPoint.cpp:311
SmallString.h
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:252
Fix
x86 execution domain X86 Execution Domain Fix
Definition: X86TargetMachine.cpp:423
llvm::Legalizer
Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::initializeX86KCFIPass
void initializeX86KCFIPass(PassRegistry &)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::createX86SpeculativeLoadHardeningPass
FunctionPass * createX86SpeculativeLoadHardeningPass()
Definition: X86SpeculativeLoadHardening.cpp:2277
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:709
llvm::StringRef::getAsInteger
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:474
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
false
Definition: StackSlotColoring.cpp:141
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:782
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::createX86PartialReductionPass
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
Definition: X86PartialReduction.cpp:60
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3645
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1355
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:325
llvm::createX86LowerAMXIntrinsicsPass
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Definition: X86LowerAMXIntrinsics.cpp:679
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createCFIInstrInserter
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
llvm::createCFGuardDispatchPass
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:311
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::initializePseudoProbeInserterPass
void initializePseudoProbeInserterPass(PassRegistry &)
llvm::initializeX86SpeculativeLoadHardeningPassPass
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
llvm::initializeWinEHStatePassPass
void initializeWinEHStatePassPass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:97
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
llvm::createX86LowerTileCopyPass
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
Definition: X86LowerTileCopy.cpp:68
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::createX86LoadValueInjectionRetHardeningPass
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
InstructionSelector.h
llvm::createX86SpeculativeExecutionSideEffectSuppression
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
Definition: X86SpeculativeExecutionSideEffectSuppression.cpp:176
llvm::cl::opt< bool >
llvm::initializeX86LoadValueInjectionRetHardeningPassPass
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:95
llvm::getTheX86_32Target
Target & getTheX86_32Target()
Definition: X86TargetInfo.cpp:13
llvm::createX86DiscriminateMemOpsPass
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
Definition: X86DiscriminateMemOps.cpp:185
X86MCTargetDesc.h
llvm::createX86WinEHStatePass
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
Definition: X86WinEHState.cpp:114
llvm::initializeFPSPass
void initializeFPSPass(PassRegistry &)
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3488
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:525
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
X86LegalizerInfo.h
llvm::createX86DomainReassignmentPass
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
LLVMInitializeX86Target
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
Definition: X86TargetMachine.cpp:68
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:127
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:284
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::createX86InsertPrefetchPass
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
Definition: X86InsertPrefetch.cpp:252
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:81
llvm::createX86AvoidStoreForwardingBlocks
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
Definition: X86AvoidStoreForwardingBlocks.cpp:129
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::createX86ISelDag
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
Definition: X86ISelDAGToDAG.cpp:6197
llvm::TargetPassConfig::addRegAssignAndRewriteOptimized
virtual bool addRegAssignAndRewriteOptimized()
Definition: TargetPassConfig.cpp:1429
llvm::LiveRangeShrinkID
char & LiveRangeShrinkID
LiveRangeShrink pass.
Definition: LiveRangeShrink.cpp:64
TargetPassConfig.h
llvm::initializeX86LowerAMXTypeLegacyPassPass
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::initializeX86AvoidTrailingCallPassPass
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
llvm::createX86ReturnThunksPass
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
Definition: X86ReturnThunks.cpp:96
llvm::X86TargetMachine
Definition: X86TargetMachine.h:29
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:307
llvm::createX86ExpandPseudoPass
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
Definition: X86ExpandPseudo.cpp:752
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:66
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::createX86FixupBWInsts
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
Definition: X86FixupBWInsts.cpp:159
llvm::initializeX86LowerTileCopyPass
void initializeX86LowerTileCopyPass(PassRegistry &)
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:42
llvm::X86TargetMachine::getSubtargetImpl
const X86Subtarget * getSubtargetImpl() const =delete
Triple.h
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
MCAsmInfo.h
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
X86TargetTransformInfo.h
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
IRTranslator.h
EnableMachineCombinerPass
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::createIndirectBrExpandPass
FunctionPass * createIndirectBrExpandPass()
Definition: IndirectBrExpandPass.cpp:78
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
llvm::createX86LoadValueInjectionLoadHardeningPass
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
Definition: X86LoadValueInjectionLoadHardening.cpp:813
Attributes.h
llvm::createBreakFalseDeps
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
Definition: BreakFalseDeps.cpp:107
llvm::X86TTIImpl
Definition: X86TargetTransformInfo.h:28
llvm::createX86EvexToVexInsts
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
Definition: X86EvexToVex.cpp:279
llvm::initializeFixupBWInstPassPass
void initializeFixupBWInstPassPass(PassRegistry &)
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::initializeFixupLEAPassPass
void initializeFixupLEAPassPass(PassRegistry &)
computeDataLayout
static std::string computeDataLayout(const Triple &TT)
Definition: X86TargetMachine.cpp:120
X86TargetMachine.h
llvm::initializeX86LowerAMXIntrinsicsLegacyPassPass
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1309
X86TargetObjectFile.h
RegBankSelect.h
Function.h
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: X86TargetMachine.cpp:108
llvm::createPseudoProbeInserter
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
Definition: PseudoProbeInserter.cpp:151
llvm::initializeX86PreTileConfigPass
void initializeX86PreTileConfigPass(PassRegistry &)
llvm::createX86InsertX87waitPass
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
Definition: X86InsertWait.cpp:56
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:408
llvm::initializeX86SpeculativeExecutionSideEffectSuppressionPass
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
llvm::createX86FastPreTileConfigPass
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
Definition: X86FastPreTileConfig.cpp:707
llvm::initializeX86TileConfigPass
void initializeX86TileConfigPass(PassRegistry &)
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:433
llvm::initializeX86LoadValueInjectionLoadHardeningPassPass
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
llvm::initializeX86CallFrameOptimizationPass
void initializeX86CallFrameOptimizationPass(PassRegistry &)
CodeGen.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:781
ExecutionDomainFix.h
llvm::X86TargetMachine::X86TargetMachine
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
Definition: X86TargetMachine.cpp:222
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
Legalizer.h
MachineScheduler.h
llvm::initializeX86PartialReductionPass
void initializeX86PartialReductionPass(PassRegistry &)
llvm::initializeX86FixupSetCCPassPass
void initializeX86FixupSetCCPassPass(PassRegistry &)
llvm::createX86CmovConverterPass
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
Definition: X86CmovConversion.cpp:877
llvm::createX86IndirectBranchTrackingPass
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
Definition: X86IndirectBranchTracking.cpp:68
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:131
TargetTransformInfo.h
llvm::initializeX86AvoidSFBPassPass
void initializeX86AvoidSFBPassPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::initializeX86OptimizeLEAPassPass
void initializeX86OptimizeLEAPassPass(PassRegistry &)
llvm::initializeX86ExecutionDomainFixPass
void initializeX86ExecutionDomainFixPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::createX86GlobalBaseRegPass
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
Definition: X86InstrInfo.cpp:9411
llvm::X86TargetMachine::~X86TargetMachine
~X86TargetMachine() override
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::createX86OptimizeLEAs
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
Definition: X86OptimizeLEAs.cpp:315
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:258
llvm::initializeX86DomainReassignmentPass
void initializeX86DomainReassignmentPass(PassRegistry &)
llvm::cl::desc
Definition: CommandLine.h:413
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:392
execution
speculative execution
Definition: SpeculativeExecution.cpp:135
llvm::initializeX86FlagsCopyLoweringPassPass
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
llvm::createX86IssueVZeroUpperPass
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
Definition: X86VZeroUpper.cpp:116
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:120
llvm::TargetMachine::getPointerSize
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
Definition: TargetMachine.h:182
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
X86TargetInfo.h
TargetRegistry.h
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:96
llvm::initializeX86PreAMXConfigPassPass
void initializeX86PreAMXConfigPassPass(PassRegistry &)
llvm::initializeX86CmovConverterPassPass
void initializeX86CmovConverterPassPass(PassRegistry &)
RegAllocRegistry.h
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24