LLVM 19.0.0git
X86TargetMachine.cpp
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1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86 specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86TargetMachine.h"
16#include "X86.h"
18#include "X86MacroFusion.h"
19#include "X86Subtarget.h"
20#include "X86TargetObjectFile.h"
22#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringRef.h"
35#include "llvm/CodeGen/Passes.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/DataLayout.h"
40#include "llvm/IR/Function.h"
41#include "llvm/MC/MCAsmInfo.h"
43#include "llvm/Pass.h"
51#include <memory>
52#include <optional>
53#include <string>
54
55using namespace llvm;
56
57static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58 cl::desc("Enable the machine combiner pass"),
59 cl::init(true), cl::Hidden);
60
61static cl::opt<bool>
62 EnableTileRAPass("x86-tile-ra",
63 cl::desc("Enable the tile register allocation pass"),
64 cl::init(true), cl::Hidden);
65
67 // Register the target.
70
107}
108
109static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
110 if (TT.isOSBinFormatMachO()) {
111 if (TT.getArch() == Triple::x86_64)
112 return std::make_unique<X86_64MachoTargetObjectFile>();
113 return std::make_unique<TargetLoweringObjectFileMachO>();
114 }
115
116 if (TT.isOSBinFormatCOFF())
117 return std::make_unique<TargetLoweringObjectFileCOFF>();
118
119 if (TT.getArch() == Triple::x86_64)
120 return std::make_unique<X86_64ELFTargetObjectFile>();
121 return std::make_unique<X86ELFTargetObjectFile>();
122}
123
124static std::string computeDataLayout(const Triple &TT) {
125 // X86 is little endian
126 std::string Ret = "e";
127
129 // X86 and x32 have 32 bit pointers.
130 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
131 Ret += "-p:32:32";
132
133 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
134 Ret += "-p270:32:32-p271:32:32-p272:64:64";
135
136 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
137 // 128 bit integers are not specified in the 32-bit ABIs but are used
138 // internally for lowering f128, so we match the alignment to that.
139 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
140 Ret += "-i64:64-i128:128";
141 else if (TT.isOSIAMCU())
142 Ret += "-i64:32-f64:32";
143 else
144 Ret += "-i128:128-f64:32:64";
145
146 // Some ABIs align long double to 128 bits, others to 32.
147 if (TT.isOSNaCl() || TT.isOSIAMCU())
148 ; // No f80
149 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
150 Ret += "-f80:128";
151 else
152 Ret += "-f80:32";
153
154 if (TT.isOSIAMCU())
155 Ret += "-f128:32";
156
157 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
158 if (TT.isArch64Bit())
159 Ret += "-n8:16:32:64";
160 else
161 Ret += "-n8:16:32";
162
163 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
164 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
165 Ret += "-a:0:32-S32";
166 else
167 Ret += "-S128";
168
169 return Ret;
170}
171
172static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
173 std::optional<Reloc::Model> RM) {
174 bool is64Bit = TT.getArch() == Triple::x86_64;
175 if (!RM) {
176 // JIT codegen should use static relocations by default, since it's
177 // typically executed in process and not relocatable.
178 if (JIT)
179 return Reloc::Static;
180
181 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
182 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
183 // use static relocation model by default.
184 if (TT.isOSDarwin()) {
185 if (is64Bit)
186 return Reloc::PIC_;
187 return Reloc::DynamicNoPIC;
188 }
189 if (TT.isOSWindows() && is64Bit)
190 return Reloc::PIC_;
191 return Reloc::Static;
192 }
193
194 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
195 // is defined as a model for code which may be used in static or dynamic
196 // executables but not necessarily a shared library. On X86-32 we just
197 // compile in -static mode, in x86-64 we use PIC.
198 if (*RM == Reloc::DynamicNoPIC) {
199 if (is64Bit)
200 return Reloc::PIC_;
201 if (!TT.isOSDarwin())
202 return Reloc::Static;
203 }
204
205 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
206 // the Mach-O file format doesn't support it.
207 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
208 return Reloc::PIC_;
209
210 return *RM;
211}
212
213static CodeModel::Model
214getEffectiveX86CodeModel(std::optional<CodeModel::Model> CM, bool JIT,
215 bool Is64Bit) {
216 if (CM) {
217 if (*CM == CodeModel::Tiny)
218 report_fatal_error("Target does not support the tiny CodeModel", false);
219 return *CM;
220 }
221 if (JIT)
222 return Is64Bit ? CodeModel::Large : CodeModel::Small;
223 return CodeModel::Small;
224}
225
226/// Create an X86 target.
227///
229 StringRef CPU, StringRef FS,
230 const TargetOptions &Options,
231 std::optional<Reloc::Model> RM,
232 std::optional<CodeModel::Model> CM,
233 CodeGenOptLevel OL, bool JIT)
235 T, computeDataLayout(TT), TT, CPU, FS, Options,
236 getEffectiveRelocModel(TT, JIT, RM),
237 getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
238 OL),
239 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
240 // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
241 // the calling function, and TrapUnreachable is an easy way to get that.
242 if (TT.isPS() || TT.isOSBinFormatMachO()) {
243 this->Options.TrapUnreachable = true;
244 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
245 }
246
247 setMachineOutliner(true);
248
249 // x86 supports the debug entry values.
251
252 initAsmInfo();
253}
254
256
257const X86Subtarget *
259 Attribute CPUAttr = F.getFnAttribute("target-cpu");
260 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
261 Attribute FSAttr = F.getFnAttribute("target-features");
262
263 StringRef CPU =
264 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
265 // "x86-64" is a default target setting for many front ends. In these cases,
266 // they actually request for "generic" tuning unless the "tune-cpu" was
267 // specified.
268 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
269 : CPU == "x86-64" ? "generic"
270 : (StringRef)CPU;
271 StringRef FS =
272 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
273
275 // The additions here are ordered so that the definitely short strings are
276 // added first so we won't exceed the small size. We append the
277 // much longer FS string at the end so that we only heap allocate at most
278 // one time.
279
280 // Extract prefer-vector-width attribute.
281 unsigned PreferVectorWidthOverride = 0;
282 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
283 if (PreferVecWidthAttr.isValid()) {
284 StringRef Val = PreferVecWidthAttr.getValueAsString();
285 unsigned Width;
286 if (!Val.getAsInteger(0, Width)) {
287 Key += 'p';
288 Key += Val;
289 PreferVectorWidthOverride = Width;
290 }
291 }
292
293 // Extract min-legal-vector-width attribute.
294 unsigned RequiredVectorWidth = UINT32_MAX;
295 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
296 if (MinLegalVecWidthAttr.isValid()) {
297 StringRef Val = MinLegalVecWidthAttr.getValueAsString();
298 unsigned Width;
299 if (!Val.getAsInteger(0, Width)) {
300 Key += 'm';
301 Key += Val;
302 RequiredVectorWidth = Width;
303 }
304 }
305
306 // Add CPU to the Key.
307 Key += CPU;
308
309 // Add tune CPU to the Key.
310 Key += TuneCPU;
311
312 // Keep track of the start of the feature portion of the string.
313 unsigned FSStart = Key.size();
314
315 // FIXME: This is related to the code below to reset the target options,
316 // we need to know whether or not the soft float flag is set on the
317 // function before we can generate a subtarget. We also need to use
318 // it as a key for the subtarget since that can be the only difference
319 // between two functions.
320 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
321 // If the soft float attribute is set on the function turn on the soft float
322 // subtarget feature.
323 if (SoftFloat)
324 Key += FS.empty() ? "+soft-float" : "+soft-float,";
325
326 Key += FS;
327
328 // We may have added +soft-float to the features so move the StringRef to
329 // point to the full string in the Key.
330 FS = Key.substr(FSStart);
331
332 auto &I = SubtargetMap[Key];
333 if (!I) {
334 // This needs to be done before we create a new subtarget since any
335 // creation will depend on the TM and the code generation flags on the
336 // function that reside in TargetOptions.
338 I = std::make_unique<X86Subtarget>(
339 TargetTriple, CPU, TuneCPU, FS, *this,
340 MaybeAlign(F.getParent()->getOverrideStackAlignment()),
341 PreferVectorWidthOverride, RequiredVectorWidth);
342 }
343 return I.get();
344}
345
347 unsigned DestAS) const {
348 assert(SrcAS != DestAS && "Expected different address spaces!");
349 if (getPointerSize(SrcAS) != getPointerSize(DestAS))
350 return false;
351 return SrcAS < 256 && DestAS < 256;
352}
353
354//===----------------------------------------------------------------------===//
355// X86 TTI query.
356//===----------------------------------------------------------------------===//
357
360 return TargetTransformInfo(X86TTIImpl(this, F));
361}
362
363//===----------------------------------------------------------------------===//
364// Pass Pipeline Configuration
365//===----------------------------------------------------------------------===//
366
367namespace {
368
369/// X86 Code Generator Pass Configuration Options.
370class X86PassConfig : public TargetPassConfig {
371public:
372 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
373 : TargetPassConfig(TM, PM) {}
374
375 X86TargetMachine &getX86TargetMachine() const {
376 return getTM<X86TargetMachine>();
377 }
378
380 createMachineScheduler(MachineSchedContext *C) const override {
383 return DAG;
384 }
385
387 createPostMachineScheduler(MachineSchedContext *C) const override {
390 return DAG;
391 }
392
393 void addIRPasses() override;
394 bool addInstSelector() override;
395 bool addIRTranslator() override;
396 bool addLegalizeMachineIR() override;
397 bool addRegBankSelect() override;
398 bool addGlobalInstructionSelect() override;
399 bool addILPOpts() override;
400 bool addPreISel() override;
401 void addMachineSSAOptimization() override;
402 void addPreRegAlloc() override;
403 bool addPostFastRegAllocRewrite() override;
404 void addPostRegAlloc() override;
405 void addPreEmitPass() override;
406 void addPreEmitPass2() override;
407 void addPreSched2() override;
408 bool addRegAssignAndRewriteOptimized() override;
409
410 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
411};
412
413class X86ExecutionDomainFix : public ExecutionDomainFix {
414public:
415 static char ID;
416 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
417 StringRef getPassName() const override {
418 return "X86 Execution Dependency Fix";
419 }
420};
421char X86ExecutionDomainFix::ID;
422
423} // end anonymous namespace
424
425INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
426 "X86 Execution Domain Fix", false, false)
428INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
429 "X86 Execution Domain Fix", false, false)
430
432 return new X86PassConfig(*this, PM);
433}
434
436 BumpPtrAllocator &Allocator, const Function &F,
437 const TargetSubtargetInfo *STI) const {
438 return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,
439 STI);
440}
441
442void X86PassConfig::addIRPasses() {
444
445 // We add both pass anyway and when these two passes run, we skip the pass
446 // based on the option level and option attribute.
448 addPass(createX86LowerAMXTypePass());
449
451
452 if (TM->getOptLevel() != CodeGenOptLevel::None) {
455 }
456
457 // Add passes that handle indirect branch removal and insertion of a retpoline
458 // thunk. These will be a no-op unless a function subtarget has the retpoline
459 // feature enabled.
461
462 // Add Control Flow Guard checks.
463 const Triple &TT = TM->getTargetTriple();
464 if (TT.isOSWindows()) {
465 if (TT.getArch() == Triple::x86_64) {
466 addPass(createCFGuardDispatchPass());
467 } else {
468 addPass(createCFGuardCheckPass());
469 }
470 }
471
472 if (TM->Options.JMCInstrument)
473 addPass(createJMCInstrumenterPass());
474}
475
476bool X86PassConfig::addInstSelector() {
477 // Install an instruction selector.
478 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
479
480 // For ELF, cleanup any local-dynamic TLS accesses.
481 if (TM->getTargetTriple().isOSBinFormatELF() &&
482 getOptLevel() != CodeGenOptLevel::None)
484
487 return false;
488}
489
490bool X86PassConfig::addIRTranslator() {
491 addPass(new IRTranslator(getOptLevel()));
492 return false;
493}
494
495bool X86PassConfig::addLegalizeMachineIR() {
496 addPass(new Legalizer());
497 return false;
498}
499
500bool X86PassConfig::addRegBankSelect() {
501 addPass(new RegBankSelect());
502 return false;
503}
504
505bool X86PassConfig::addGlobalInstructionSelect() {
506 addPass(new InstructionSelect(getOptLevel()));
507 return false;
508}
509
510bool X86PassConfig::addILPOpts() {
511 addPass(&EarlyIfConverterID);
513 addPass(&MachineCombinerID);
515 return true;
516}
517
518bool X86PassConfig::addPreISel() {
519 // Only add this pass for 32-bit x86 Windows.
520 const Triple &TT = TM->getTargetTriple();
521 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
522 addPass(createX86WinEHStatePass());
523 return true;
524}
525
526void X86PassConfig::addPreRegAlloc() {
527 if (getOptLevel() != CodeGenOptLevel::None) {
528 addPass(&LiveRangeShrinkID);
529 addPass(createX86FixupSetCC());
530 addPass(createX86OptimizeLEAs());
533 }
534
538
539 if (getOptLevel() != CodeGenOptLevel::None)
541 else
543}
544
545void X86PassConfig::addMachineSSAOptimization() {
548}
549
550void X86PassConfig::addPostRegAlloc() {
553 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
554 // to using the Speculative Execution Side Effect Suppression pass for
555 // mitigation. This is to prevent slow downs due to
556 // analyses needed by the LVIHardening pass when compiling at -O0.
557 if (getOptLevel() != CodeGenOptLevel::None)
559}
560
561void X86PassConfig::addPreSched2() {
562 addPass(createX86ExpandPseudoPass());
563 addPass(createKCFIPass());
564}
565
566void X86PassConfig::addPreEmitPass() {
567 if (getOptLevel() != CodeGenOptLevel::None) {
568 addPass(new X86ExecutionDomainFix());
569 addPass(createBreakFalseDeps());
570 }
571
573
575
576 if (getOptLevel() != CodeGenOptLevel::None) {
577 addPass(createX86FixupBWInsts());
579 addPass(createX86FixupLEAs());
580 addPass(createX86FixupInstTuning());
582 }
583 addPass(createX86CompressEVEXPass());
587}
588
589void X86PassConfig::addPreEmitPass2() {
590 const Triple &TT = TM->getTargetTriple();
591 const MCAsmInfo *MAI = TM->getMCAsmInfo();
592
593 // The X86 Speculative Execution Pass must run after all control
594 // flow graph modifying passes. As a result it was listed to run right before
595 // the X86 Retpoline Thunks pass. The reason it must run after control flow
596 // graph modifications is that the model of LFENCE in LLVM has to be updated
597 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
598 // placement of this pass was hand checked to ensure that the subsequent
599 // passes don't move the code around the LFENCEs in a way that will hurt the
600 // correctness of this pass. This placement has been shown to work based on
601 // hand inspection of the codegen output.
604 addPass(createX86ReturnThunksPass());
605
606 // Insert extra int3 instructions after trailing call instructions to avoid
607 // issues in the unwinder.
608 if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
610
611 // Verify basic block incoming and outgoing cfa offset and register values and
612 // correct CFA calculation rule where needed by inserting appropriate CFI
613 // instructions.
614 if (!TT.isOSDarwin() &&
615 (!TT.isOSWindows() ||
617 addPass(createCFIInstrInserter());
618
619 if (TT.isOSWindows()) {
620 // Identify valid longjmp targets for Windows Control Flow Guard.
621 addPass(createCFGuardLongjmpPass());
622 // Identify valid eh continuation targets for Windows EHCont Guard.
624 }
626
627 // Insert pseudo probe annotation for callsite profiling
628 addPass(createPseudoProbeInserter());
629
630 // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,
631 // also CALL_RVMARKER.
632 addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {
633 // Only run bundle expansion if the module uses kcfi, or there are relevant
634 // ObjC runtime functions present in the module.
635 const Function &F = MF.getFunction();
636 const Module *M = F.getParent();
637 return M->getModuleFlag("kcfi") ||
638 (TT.isOSDarwin() &&
639 (M->getFunction("objc_retainAutoreleasedReturnValue") ||
640 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));
641 }));
642}
643
644bool X86PassConfig::addPostFastRegAllocRewrite() {
646 return true;
647}
648
649std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
650 return getStandardCSEConfigForOpt(TM->getOptLevel());
651}
652
654 const TargetRegisterClass &RC) {
655 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
656}
657
658bool X86PassConfig::addRegAssignAndRewriteOptimized() {
659 // Don't support tile RA when RA is specified by command line "-regalloc".
660 if (!isCustomizedRegAlloc() && EnableTileRAPass) {
661 // Allocate tile register first.
663 addPass(createX86TileConfigPass());
664 }
666}
Falkor HW Prefetch Fix
arm execution domain fix
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallString class.
speculative execution
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
static bool is64Bit(const char *name)
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(std::optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, std::optional< Reloc::Model > RM)
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:169
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:787
Function & getFunction()
Return the LLVM function that this machine code represents.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:466
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:95
void setMachineOutliner(bool Enable)
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::string TargetFS
Definition: TargetMachine.h:97
std::string TargetCPU
Definition: TargetMachine.h:96
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
@ X86
Windows x64, Windows Itanium (IA-64)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
FunctionPass * createIndirectBrExpandPass()
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86PartialReductionPass(PassRegistry &)
void initializeX86CallFrameOptimizationPass(PassRegistry &)
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86ArgumentStackSlotPassPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
@ DwarfCFI
DWARF-like instruction based exceptions.
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Target & getTheX86_32Target()
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:317
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition: CSEInfo.cpp:79
FunctionPass * createX86CompressEVEXPass()
This pass compress instructions from EVEX space to legacy/VEX/EVEX space when possible in order to re...
void initializeX86ExpandPseudoPass(PassRegistry &)
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createX86ArgumentStackSlotPass()
void initializeX86PreTileConfigPass(PassRegistry &)
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
void initializeX86DomainReassignmentPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
void initializeX86AvoidSFBPassPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86FastPreTileConfigPass(PassRegistry &)
FunctionPass * createX86SpeculativeLoadHardeningPass()
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
void initializeX86FixupSetCCPassPass(PassRegistry &)
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
char & LiveRangeShrinkID
LiveRangeShrink pass.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
FunctionPass * createX86FixupInstTuning()
Return a pass that replaces equivalent slower instructions with faster ones.
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
void initializeX86LowerTileCopyPass(PassRegistry &)
void initializeX86OptimizeLEAPassPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeX86FixupInstTuningPassPass(PassRegistry &)
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
void initializeKCFIPass(PassRegistry &)
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
void initializeCompressEVEXPassPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:313
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
void initializeX86FixupVectorConstantsPassPass(PassRegistry &)
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeX86DAGToDAGISelPass(PassRegistry &)
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
Target & getTheX86_64Target()
void initializePseudoProbeInserterPass(PassRegistry &)
FunctionPass * createX86FixupVectorConstants()
Return a pass that reduces the size of vector constant pool loads.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
void initializeX86ReturnThunksPass(PassRegistry &)
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
void initializeFixupLEAPassPass(PassRegistry &)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
RegisterTargetMachine - Helper template for registering a target machine implementation,...