SIISelLowering.cpp File Reference

Custom DAG lowering for SI. More...

#include "SIISelLowering.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUTargetMachine.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/FloatingPointMode.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/Analysis/UniformityAnalysis.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/ByteProvider.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/ModRef.h"
#include <optional>

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "si-lower"

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static bool	denormalModeIsFlushAllF32 (const MachineFunction &MF)
static bool	denormalModeIsFlushAllF64F16 (const MachineFunction &MF)
static unsigned	findFirstFreeSGPR (CCState &CCInfo)
static EVT	memVTFromLoadIntrData (Type *Ty, unsigned MaxNumLanes)
static EVT	memVTFromLoadIntrReturn (Type *Ty, unsigned MaxNumLanes)
static void	processPSInputArgs (SmallVectorImpl< ISD::InputArg > &Splits, CallingConv::ID CallConv, ArrayRef< ISD::InputArg > Ins, BitVector &Skipped, FunctionType *FType, SIMachineFunctionInfo *Info)
static ArgDescriptor	allocateVGPR32Input (CCState &CCInfo, unsigned Mask=~0u, ArgDescriptor Arg=ArgDescriptor())
static ArgDescriptor	allocateSGPR32InputImpl (CCState &CCInfo, const TargetRegisterClass *RC, unsigned NumArgRegs)
static void	allocateFixedSGPRInputImpl (CCState &CCInfo, const TargetRegisterClass *RC, MCRegister Reg)
static void	allocateSGPR32Input (CCState &CCInfo, ArgDescriptor &Arg)
static void	allocateSGPR64Input (CCState &CCInfo, ArgDescriptor &Arg)
static void	reservePrivateMemoryRegs (const TargetMachine &TM, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info)
static bool	canGuaranteeTCO (CallingConv::ID CC)
static bool	mayTailCallThisCC (CallingConv::ID CC)
	Return true if we might ever do TCO for calls with this calling convention.
static std::pair< MachineBasicBlock *, MachineBasicBlock * >	splitBlockForLoop (MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop)
static MachineBasicBlock::iterator	emitLoadM0FromVGPRLoop (const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &Idx, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode, Register &SGPRIdxReg)
static MachineBasicBlock::iterator	loadM0FromVGPR (const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI, unsigned InitResultReg, unsigned PhiReg, int Offset, bool UseGPRIdxMode, Register &SGPRIdxReg)
static std::pair< unsigned, int >	computeIndirectRegAndOffset (const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, unsigned VecReg, int Offset)
static void	setM0ToIndexFromSGPR (const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineInstr &MI, int Offset)
static Register	getIndirectSGPRIdx (const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineInstr &MI, int Offset)
static MachineBasicBlock *	emitIndirectSrc (MachineInstr &MI, MachineBasicBlock &MBB, const GCNSubtarget &ST)
static MachineBasicBlock *	emitIndirectDst (MachineInstr &MI, MachineBasicBlock &MBB, const GCNSubtarget &ST)
static MachineBasicBlock *	lowerWaveReduce (MachineInstr &MI, MachineBasicBlock &BB, const GCNSubtarget &ST, unsigned Opc)
static SDValue	adjustLoadValueTypeImpl (SDValue Result, EVT LoadVT, const SDLoc &DL, SelectionDAG &DAG, bool Unpacked)
static SDValue	lowerICMPIntrinsic (const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static SDValue	lowerFCMPIntrinsic (const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static SDValue	lowerBALLOTIntrinsic (const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static SDNode *	findUser (SDValue Value, unsigned Opcode)
	Helper function for LowerBRCOND.
static bool	isKnownNonNull (SDValue Val, SelectionDAG &DAG, const AMDGPUTargetMachine &TM, unsigned AddrSpace)
	Return true if the value is a known valid address, such that a null check is not necessary.
static bool	elementPairIsContiguous (ArrayRef< int > Mask, int Elt)
static SDValue	buildPCRelGlobalAddress (SelectionDAG &DAG, const GlobalValue *GV, const SDLoc &DL, int64_t Offset, EVT PtrVT, unsigned GAFlags=SIInstrInfo::MO_NONE)
static SDValue	emitNonHSAIntrinsicError (SelectionDAG &DAG, const SDLoc &DL, EVT VT)
static SDValue	emitRemovedIntrinsicError (SelectionDAG &DAG, const SDLoc &DL, EVT VT)
static SDValue	getBuildDwordsVector (SelectionDAG &DAG, SDLoc DL, ArrayRef< SDValue > Elts)
static SDValue	padEltsToUndef (SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, SDValue Src, int ExtraElts)
static SDValue	constructRetValue (SelectionDAG &DAG, MachineSDNode *Result, ArrayRef< EVT > ResultTypes, bool IsTexFail, bool Unpacked, bool IsD16, int DMaskPop, int NumVDataDwords, const SDLoc &DL)
static bool	parseTexFail (SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE, SDValue *LWE, bool &IsTexFail)
static void	packImage16bitOpsToDwords (SelectionDAG &DAG, SDValue Op, MVT PackVectorVT, SmallVectorImpl< SDValue > &PackedAddrs, unsigned DimIdx, unsigned EndIdx, unsigned NumGradients)
static unsigned	getIdxEn (SDValue VIndex)
static SDValue	getLoadExtOrTrunc (SelectionDAG &DAG, ISD::LoadExtType ExtType, SDValue Op, const SDLoc &SL, EVT VT)
static bool	addressMayBeAccessedAsPrivate (const MachineMemOperand *MMO, const SIMachineFunctionInfo &Info)
static SDValue	getFPBinOp (SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue GlueChain, SDNodeFlags Flags)
static SDValue	getFPTernOp (SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue C, SDValue GlueChain, SDNodeFlags Flags)
static SDValue	getSPDenormModeValue (uint32_t SPDenormMode, SelectionDAG &DAG, const SIMachineFunctionInfo *Info, const GCNSubtarget *ST)
static unsigned	getBasePtrIndex (const MemSDNode *N)
	MemSDNode::getBasePtr() does not work for intrinsics, which needs to offset by the chain and intrinsic ID.
static bool	bitOpWithConstantIsReducible (unsigned Opc, uint32_t Val)
static bool	isBoolSGPR (SDValue V)
static uint32_t	getConstantPermuteMask (uint32_t C)
static uint32_t	getPermuteMask (SDValue V)
static const std::optional< ByteProvider< SDValue > >	calculateSrcByte (const SDValue Op, uint64_t DestByte, uint64_t SrcIndex=0, unsigned Depth=0)
static const std::optional< ByteProvider< SDValue > >	calculateByteProvider (const SDValue &Op, unsigned Index, unsigned Depth, unsigned StartingIndex=0)
static bool	isExtendedFrom16Bits (SDValue &Operand)
static bool	addresses16Bits (int Mask)
static bool	hasNon16BitAccesses (uint64_t PermMask, SDValue &Op, SDValue &OtherOp)
static bool	vectorEltWillFoldAway (SDValue Op)
static unsigned	minMaxOpcToMin3Max3Opc (unsigned Opc)
static ConstantFPSDNode *	getSplatConstantFP (SDValue Op)
static bool	isClampZeroToOne (SDValue A, SDValue B)
static SDValue	strictFPExtFromF16 (SelectionDAG &DAG, SDValue Src)
	Return the source of an fp_extend from f16 to f32, or a converted FP constant.
static SDValue	getMad64_32 (SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue N0, SDValue N1, SDValue N2, bool Signed)
static unsigned	SubIdx2Lane (unsigned Idx)
	Helper function for adjustWritemask.
static bool	isFrameIndexOp (SDValue Op)
static SDValue	buildSMovImm32 (SelectionDAG &DAG, const SDLoc &DL, uint64_t Val)
static bool	isImmConstraint (StringRef Constraint)
static uint64_t	clearUnusedBits (uint64_t Val, unsigned Size)
static int	getAlignedAGPRClassID (unsigned UnalignedClassID)
static void	knownBitsForWorkitemID (const GCNSubtarget &ST, GISelKnownBits &KB, KnownBits &Known, unsigned Dim)
static LLVM_ATTRIBUTE_UNUSED bool	isCopyFromRegOfInlineAsm (const SDNode *N)
static bool	fpModeMatchesGlobalFPAtomicMode (const AtomicRMWInst *RMW)
bool	unsafeFPAtomicsDisabled (Function *F)
static bool	hasCFUser (const Value *V, SmallPtrSet< const Value *, 16 > &Visited, unsigned WaveSize)

Variables
static cl::opt< bool >	DisableLoopAlignment ("amdgpu-disable-loop-alignment", cl::desc("Do not align and prefetch loops"), cl::init(false))
static cl::opt< bool >	UseDivergentRegisterIndexing ("amdgpu-use-divergent-register-indexing", cl::Hidden, cl::desc("Use indirect register addressing for divergent indexes"), cl::init(false))

Detailed Description

Custom DAG lowering for SI.

Definition in file SIISelLowering.cpp.

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "si-lower"

Definition at line 49 of file SIISelLowering.cpp.

Function Documentation

addresses16Bits()

static bool addresses16Bits ( int  Mask )

static

Definition at line 10957 of file SIISelLowering.cpp.

References assert().

Referenced by hasNon16BitAccesses().

addressMayBeAccessedAsPrivate()

static bool addressMayBeAccessedAsPrivate ( const MachineMemOperand *  MMO, const SIMachineFunctionInfo &  Info  )

static

Definition at line 9164 of file SIISelLowering.cpp.

References Info.

adjustLoadValueTypeImpl()

static SDValue adjustLoadValueTypeImpl ( SDValue  Result, EVT  LoadVT, const SDLoc &  DL, SelectionDAG &  DAG, bool  Unpacked  )

static

Definition at line 5148 of file SIISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), DL, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::TRUNCATE.

Referenced by constructRetValue().

allocateFixedSGPRInputImpl()

static void allocateFixedSGPRInputImpl ( CCState &  CCInfo, const TargetRegisterClass *  RC, MCRegister  Reg  )

static

Definition at line 2082 of file SIISelLowering.cpp.

References llvm::MachineFunction::addLiveIn(), llvm::CCState::AllocateReg(), assert(), and llvm::CCState::getMachineFunction().

Referenced by allocateSGPR32Input(), and allocateSGPR64Input().

allocateSGPR32Input()

static void allocateSGPR32Input ( CCState &  CCInfo, ArgDescriptor &  Arg  )

static

Definition at line 2091 of file SIISelLowering.cpp.

References allocateFixedSGPRInputImpl(), allocateSGPR32InputImpl(), and llvm::ArgDescriptor::getRegister().

Referenced by llvm::SITargetLowering::allocateSpecialInputSGPRs().

allocateSGPR32InputImpl()

static ArgDescriptor allocateSGPR32InputImpl ( CCState &  CCInfo, const TargetRegisterClass *  RC, unsigned  NumArgRegs  )

static

Definition at line 2062 of file SIISelLowering.cpp.

References llvm::MachineFunction::addLiveIn(), llvm::CCState::AllocateReg(), assert(), llvm::TargetRegisterClass::begin(), llvm::ArgDescriptor::createRegister(), llvm::CCState::getFirstUnallocated(), llvm::CCState::getMachineFunction(), llvm::report_fatal_error(), and llvm::ArrayRef< T >::size().

Referenced by allocateSGPR32Input(), and allocateSGPR64Input().

allocateSGPR64Input()

static void allocateSGPR64Input ( CCState &  CCInfo, ArgDescriptor &  Arg  )

static

Definition at line 2099 of file SIISelLowering.cpp.

References allocateFixedSGPRInputImpl(), allocateSGPR32InputImpl(), and llvm::ArgDescriptor::getRegister().

Referenced by llvm::SITargetLowering::allocateSpecialInputSGPRs().

allocateVGPR32Input()

static ArgDescriptor allocateVGPR32Input ( CCState &  CCInfo, unsigned  Mask = ~0u, ArgDescriptor  Arg = ArgDescriptor()  )

static

Definition at line 2038 of file SIISelLowering.cpp.

References llvm::MachineFunction::addLiveIn(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), assert(), llvm::ArgDescriptor::createArg(), llvm::ArgDescriptor::createRegister(), llvm::ArgDescriptor::createStack(), llvm::CCState::getFirstUnallocated(), llvm::CCState::getMachineFunction(), llvm::MachineFunction::getRegInfo(), llvm::Offset, llvm::LLT::scalar(), llvm::MachineRegisterInfo::setType(), and llvm::ArrayRef< T >::size().

Referenced by llvm::SITargetLowering::allocateSpecialInputVGPRs().

bitOpWithConstantIsReducible()

static bool bitOpWithConstantIsReducible ( unsigned  Opc, uint32_t  Val  )

static

Definition at line 10311 of file SIISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::OR, and llvm::ISD::XOR.

buildPCRelGlobalAddress()

static SDValue buildPCRelGlobalAddress ( SelectionDAG &  DAG, const GlobalValue *  GV, const SDLoc &  DL, int64_t  Offset, EVT  PtrVT, unsigned  GAFlags = SIInstrInfo::MO_NONE  )

static

Definition at line 6485 of file SIISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SIInstrInfo::MO_NONE, llvm::Offset, and llvm::AMDGPUISD::PC_ADD_REL_OFFSET.

buildSMovImm32()

static SDValue buildSMovImm32 ( SelectionDAG &  DAG, const SDLoc &  DL, uint64_t  Val  )

static

Definition at line 13593 of file SIISelLowering.cpp.

References DL, llvm::SelectionDAG::getMachineNode(), and llvm::SelectionDAG::getTargetConstant().

Referenced by llvm::SITargetLowering::buildRSRC(), and llvm::SITargetLowering::wrapAddr64Rsrc().

calculateByteProvider()

static const std::optional< ByteProvider< SDValue > > calculateByteProvider ( const SDValue &  Op, unsigned  Index, unsigned  Depth, unsigned  StartingIndex = 0  )

static

Definition at line 10717 of file SIISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::BitWidth, llvm::ISD::BSWAP, calculateByteProvider(), calculateSrcByte(), llvm::ISD::CopyFromReg, llvm::Depth, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ByteProvider< ISelOp >::getConstantZero(), llvm::SDValue::getValueSizeInBits(), LHS, llvm_unreachable, llvm::ISD::LOAD, llvm::ISD::OR, llvm::AMDGPUISD::PERM, RHS, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

calculateSrcByte()

static const std::optional< ByteProvider< SDValue > > calculateSrcByte ( const SDValue  Op, uint64_t  DestByte, uint64_t  SrcIndex = 0, unsigned  Depth = 0  )

static

Definition at line 10654 of file SIISelLowering.cpp.

References calculateSrcByte(), llvm::Depth, llvm::ByteProvider< ISelOp >::getSrc(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), llvm::EVT::isByteSized(), llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by calculateByteProvider(), and calculateSrcByte().

canGuaranteeTCO()

static bool canGuaranteeTCO ( CallingConv::ID  CC )

static

Definition at line 3084 of file SIISelLowering.cpp.

References CC, and llvm::CallingConv::Fast.

clearUnusedBits()

static uint64_t clearUnusedBits ( uint64_t  Val, unsigned  Size  )

static

Definition at line 13812 of file SIISelLowering.cpp.

References llvm::AMDGPU::isInlinableIntLiteral(), and Size.

Referenced by llvm::APInt::APInt(), llvm::APInt::ashrInPlace(), llvm::SITargetLowering::checkAsmConstraintVal(), llvm::APInt::flipAllBits(), llvm::SITargetLowering::LowerAsmOperandForConstraint(), llvm::APInt::operator<<=(), llvm::APInt::operator=(), llvm::APInt::operator^=(), llvm::APInt::operator|=(), and llvm::APInt::setAllBits().

computeIndirectRegAndOffset()

static std::pair< unsigned, int > computeIndirectRegAndOffset ( const SIRegisterInfo &  TRI, const TargetRegisterClass *  SuperRC, unsigned  VecReg, int  Offset  )

static

Definition at line 3933 of file SIISelLowering.cpp.

References llvm::SIRegisterInfo::getSubRegFromChannel(), llvm::Offset, and TRI.

Referenced by emitIndirectDst(), and emitIndirectSrc().

constructRetValue()

static SDValue constructRetValue ( SelectionDAG &  DAG, MachineSDNode *  Result, ArrayRef< EVT >  ResultTypes, bool  IsTexFail, bool  Unpacked, bool  IsD16, int  DMaskPop, int  NumVDataDwords, const SDLoc &  DL  )

static

Definition at line 6688 of file SIISelLowering.cpp.

References adjustLoadValueTypeImpl(), llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), llvm::Data, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::MVT::isVector(), llvm::EVT::isVector(), padEltsToUndef(), and llvm::ISD::TRUNCATE.

denormalModeIsFlushAllF32()

static bool denormalModeIsFlushAllF32 ( const MachineFunction &  MF )

static

Definition at line 64 of file SIISelLowering.cpp.

References llvm::MachineFunction::getInfo(), llvm::DenormalMode::getPreserveSign(), and Info.

Referenced by llvm::SITargetLowering::denormalsEnabledForType(), llvm::SITargetLowering::isFMADLegal(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), and llvm::SITargetLowering::isFPExtFoldable().

denormalModeIsFlushAllF64F16()

static bool denormalModeIsFlushAllF64F16 ( const MachineFunction &  MF )

static

Definition at line 69 of file SIISelLowering.cpp.

References llvm::MachineFunction::getInfo(), llvm::DenormalMode::getPreserveSign(), and Info.

Referenced by llvm::SITargetLowering::denormalsEnabledForType(), llvm::SITargetLowering::isFMADLegal(), and llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd().

elementPairIsContiguous()

static bool elementPairIsContiguous ( ArrayRef< int >  Mask, int  Elt  )

static

Definition at line 6324 of file SIISelLowering.cpp.

References assert().

emitIndirectDst()

static MachineBasicBlock * emitIndirectDst ( MachineInstr &  MI, MachineBasicBlock &  MBB, const GCNSubtarget &  ST  )

static

Definition at line 4072 of file SIISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), computeIndirectRegAndOffset(), DL, getIndirectSGPRIdx(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), I, Idx, llvm::MachineOperand::isReg(), loadM0FromVGPR(), MBB, MI, MRI, llvm::Offset, setM0ToIndexFromSGPR(), SubReg, TII, and TRI.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().

emitIndirectSrc()

static MachineBasicBlock * emitIndirectSrc ( MachineInstr &  MI, MachineBasicBlock &  MBB, const GCNSubtarget &  ST  )

static

Definition at line 3986 of file SIISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), computeIndirectRegAndOffset(), DL, getIndirectSGPRIdx(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, Idx, llvm::RegState::Implicit, loadM0FromVGPR(), MBB, MI, MRI, llvm::Offset, setM0ToIndexFromSGPR(), SubReg, TII, and TRI.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().

emitLoadM0FromVGPRLoop()

static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop ( const SIInstrInfo *  TII, MachineRegisterInfo &  MRI, MachineBasicBlock &  OrigBB, MachineBasicBlock &  LoopBB, const DebugLoc &  DL, const MachineOperand &  Idx, unsigned  InitReg, unsigned  ResultReg, unsigned  PhiReg, unsigned  InitSaveExecReg, int  Offset, bool  UseGPRIdxMode, Register &  SGPRIdxReg  )

static

Definition at line 3792 of file SIISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::getUndefRegState(), I, Idx, llvm::RegState::Kill, MRI, llvm::Offset, TII, and TRI.

Referenced by loadM0FromVGPR().

emitNonHSAIntrinsicError()

static SDValue emitNonHSAIntrinsicError ( SelectionDAG &  DAG, const SDLoc &  DL, EVT  VT  )

static

Definition at line 6620 of file SIISelLowering.cpp.

References llvm::LLVMContext::diagnose(), DL, llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), and llvm::SelectionDAG::getUNDEF().

emitRemovedIntrinsicError()

static SDValue emitRemovedIntrinsicError ( SelectionDAG &  DAG, const SDLoc &  DL, EVT  VT  )

static

Definition at line 6629 of file SIISelLowering.cpp.

References llvm::LLVMContext::diagnose(), DL, llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), and llvm::SelectionDAG::getUNDEF().

findFirstFreeSGPR()

static unsigned findFirstFreeSGPR ( CCState &  CCInfo )

static

Definition at line 74 of file SIISelLowering.cpp.

References llvm::CCState::isAllocated(), and llvm_unreachable.

Referenced by llvm::SITargetLowering::allocateSystemSGPRs().

findUser()

static SDNode * findUser ( SDValue  Value, unsigned  Opcode  )

static

Helper function for LowerBRCOND.

Definition at line 5510 of file SIISelLowering.cpp.

References E, I, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

fpModeMatchesGlobalFPAtomicMode()

static bool fpModeMatchesGlobalFPAtomicMode ( const AtomicRMWInst *  RMW )

static

Definition at line 14364 of file SIISelLowering.cpp.

References Flt, llvm::Function::getDenormalMode(), llvm::Type::getFltSemantics(), llvm::DenormalMode::getIEEE(), llvm::BasicBlock::getParent(), llvm::Instruction::getParent(), llvm::DenormalMode::getPreserveSign(), llvm::Type::getScalarType(), llvm::Value::getType(), and llvm::APFloatBase::IEEEsingle().

Referenced by llvm::SITargetLowering::shouldExpandAtomicRMWInIR().

getAlignedAGPRClassID()

static int getAlignedAGPRClassID ( unsigned  UnalignedClassID )

static

Definition at line 13915 of file SIISelLowering.cpp.

Referenced by llvm::SITargetLowering::finalizeLowering().

getBasePtrIndex()

static unsigned getBasePtrIndex ( const MemSDNode *  N )

static

MemSDNode::getBasePtr() does not work for intrinsics, which needs to offset by the chain and intrinsic ID.

Theoretically we would also need to check the specific intrinsic, but they all place the pointer operand first.

Definition at line 10277 of file SIISelLowering.cpp.

References llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, N, and llvm::ISD::STORE.

Referenced by llvm::SITargetLowering::hasMemSDNodeUser().

getBuildDwordsVector()

static SDValue getBuildDwordsVector ( SelectionDAG &  DAG, SDLoc  DL, ArrayRef< SDValue >  Elts  )

static

Definition at line 6638 of file SIISelLowering.cpp.

References assert(), DL, llvm::ArrayRef< T >::empty(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorVT(), and llvm::ArrayRef< T >::size().

getConstantPermuteMask()

static uint32_t getConstantPermuteMask ( uint32_t  C )

static

Definition at line 10365 of file SIISelLowering.cpp.

References llvm::CallingConv::C.

Referenced by getPermuteMask().

getFPBinOp()

static SDValue getFPBinOp ( SelectionDAG &  DAG, unsigned  Opcode, const SDLoc &  SL, EVT  VT, SDValue  A, SDValue  B, SDValue  GlueChain, SDNodeFlags  Flags  )

static

Definition at line 9444 of file SIISelLowering.cpp.

References A, assert(), B, llvm::ISD::FMUL, llvm::AMDGPUISD::FMUL_W_CHAIN, llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), and llvm_unreachable.

getFPTernOp()

static SDValue getFPTernOp ( SelectionDAG &  DAG, unsigned  Opcode, const SDLoc &  SL, EVT  VT, SDValue  A, SDValue  B, SDValue  C, SDValue  GlueChain, SDNodeFlags  Flags  )

static

Definition at line 9466 of file SIISelLowering.cpp.

References A, assert(), B, llvm::CallingConv::C, llvm::ISD::FMA, llvm::AMDGPUISD::FMA_W_CHAIN, llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), and llvm_unreachable.

getIdxEn()

static unsigned getIdxEn ( SDValue  VIndex )

static

Definition at line 7636 of file SIISelLowering.cpp.

References llvm::isNullConstant().

getIndirectSGPRIdx()

static Register getIndirectSGPRIdx ( const SIInstrInfo *  TII, MachineRegisterInfo &  MRI, MachineInstr &  MI, int  Offset  )

static

Definition at line 3967 of file SIISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, I, Idx, MBB, MI, MRI, llvm::Offset, and TII.

Referenced by emitIndirectDst(), and emitIndirectSrc().

getLoadExtOrTrunc()

static SDValue getLoadExtOrTrunc ( SelectionDAG &  DAG, ISD::LoadExtType  ExtType, SDValue  Op, const SDLoc &  SL, EVT  VT  )

static

Definition at line 9077 of file SIISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsLT(), llvm::ISD::EXTLOAD, llvm::SelectionDAG::getNode(), llvm_unreachable, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

getMad64_32()

static SDValue getMad64_32 ( SelectionDAG &  DAG, const SDLoc &  SL, EVT  VT, SDValue  N0, SDValue  N1, SDValue  N2, bool  Signed  )

static

Definition at line 12380 of file SIISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::AMDGPUISD::MAD_I64_I32, llvm::AMDGPUISD::MAD_U64_U32, Signed, and llvm::ISD::TRUNCATE.

getPermuteMask()

static uint32_t getPermuteMask ( SDValue  V )

static

Definition at line 10385 of file SIISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::CallingConv::C, getConstantPermuteMask(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::OR, llvm::ISD::SHL, and llvm::ISD::SRL.

getSPDenormModeValue()

static SDValue getSPDenormModeValue ( uint32_t  SPDenormMode, SelectionDAG &  DAG, const SIMachineFunctionInfo *  Info, const GCNSubtarget *  ST  )

static

Definition at line 9544 of file SIISelLowering.cpp.

References assert(), llvm::SelectionDAG::getTargetConstant(), and Info.

getSplatConstantFP()

static ConstantFPSDNode * getSplatConstantFP ( SDValue  Op )

static

Definition at line 11843 of file SIISelLowering.cpp.

References llvm::CallingConv::C.

hasCFUser()

static bool hasCFUser ( const Value *  V, SmallPtrSet< const Value *, 16 > &  Visited, unsigned  WaveSize  )

static

Definition at line 14552 of file SIISelLowering.cpp.

References hasCFUser(), llvm::SmallPtrSetImpl< PtrType >::insert(), and IT.

Referenced by hasCFUser(), and llvm::SITargetLowering::requiresUniformRegister().

hasNon16BitAccesses()

static bool hasNon16BitAccesses ( uint64_t  PermMask, SDValue &  Op, SDValue &  OtherOp  )

static

Definition at line 10976 of file SIISelLowering.cpp.

References addresses16Bits(), assert(), llvm::SDValue::getValueType(), llvm::EVT::isByteSized(), isExtendedFrom16Bits(), and llvm::peekThroughBitcasts().

isBoolSGPR()

static bool isBoolSGPR ( SDValue  V )

static

Definition at line 10346 of file SIISelLowering.cpp.

References llvm::ISD::AND, llvm::AMDGPUISD::FP_CLASS, isBoolSGPR(), llvm::ISD::OR, llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by isBoolSGPR().

isClampZeroToOne()

static bool isClampZeroToOne ( SDValue  A, SDValue  B  )

static

Definition at line 11990 of file SIISelLowering.cpp.

References A, and B.

isCopyFromRegOfInlineAsm()

static LLVM_ATTRIBUTE_UNUSED bool isCopyFromRegOfInlineAsm ( const SDNode *  N )

static

Definition at line 14242 of file SIISelLowering.cpp.

References assert(), llvm::ISD::CopyFromReg, llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, and N.

Referenced by llvm::SITargetLowering::isSDNodeSourceOfDivergence().

isExtendedFrom16Bits()

static bool isExtendedFrom16Bits ( SDValue &  Operand )

static

Definition at line 10931 of file SIISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::EXTLOAD, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), llvm::ISD::LOAD, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

Referenced by hasNon16BitAccesses().

isFrameIndexOp()

static bool isFrameIndexOp ( SDValue  Op )

static

Definition at line 13312 of file SIISelLowering.cpp.

References llvm::ISD::AssertZext.

Referenced by llvm::SITargetLowering::legalizeTargetIndependentNode().

isImmConstraint()

static bool isImmConstraint ( StringRef  Constraint )

static

Definition at line 13777 of file SIISelLowering.cpp.

References llvm::StringRef::size().

Referenced by llvm::SITargetLowering::getConstraintType(), and llvm::SITargetLowering::LowerAsmOperandForConstraint().

isKnownNonNull()

static bool isKnownNonNull ( SDValue  Val, SelectionDAG &  DAG, const AMDGPUTargetMachine &  TM, unsigned  AddrSpace  )

static

Return true if the value is a known valid address, such that a null check is not necessary.

Definition at line 6008 of file SIISelLowering.cpp.

References TM.

knownBitsForWorkitemID()

static void knownBitsForWorkitemID ( const GCNSubtarget &  ST, GISelKnownBits &  KB, KnownBits &  Known, unsigned  Dim  )

static

Definition at line 14076 of file SIISelLowering.cpp.

References llvm::countl_zero(), llvm::MachineFunction::getFunction(), llvm::GISelKnownBits::getMachineFunction(), llvm::APInt::setHighBits(), and llvm::KnownBits::Zero.

Referenced by llvm::SITargetLowering::computeKnownBitsForTargetInstr().

loadM0FromVGPR()

static MachineBasicBlock::iterator loadM0FromVGPR ( const SIInstrInfo *  TII, MachineBasicBlock &  MBB, MachineInstr &  MI, unsigned  InitResultReg, unsigned  PhiReg, int  Offset, bool  UseGPRIdxMode, Register &  SGPRIdxReg  )

static

Definition at line 3884 of file SIISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, emitLoadM0FromVGPRLoop(), llvm::First, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), I, Idx, llvm::MachineFunction::insert(), MBB, MBBI, MI, MRI, llvm::Offset, llvm::MachineBasicBlock::removeSuccessor(), splitBlockForLoop(), TII, and TRI.

Referenced by emitIndirectDst(), and emitIndirectSrc().

lowerBALLOTIntrinsic()

static SDValue lowerBALLOTIntrinsic ( const SITargetLowering &  TLI, SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 5337 of file SIISelLowering.cpp.

References llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getZExtOrTrunc(), N, llvm::ISD::SETCC, llvm::AMDGPUISD::SETCC, and llvm::ISD::SETNE.

lowerFCMPIntrinsic()

static SDValue lowerFCMPIntrinsic ( const SITargetLowering &  TLI, SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 5307 of file SIISelLowering.cpp.

References llvm::EVT::bitsEq(), llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getContext(), llvm::getFCmpCondCode(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SITargetLowering::getSubtarget(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::CmpInst::isFPPredicate(), llvm::TargetLoweringBase::isTypeLegal(), N, and llvm::AMDGPUISD::SETCC.

lowerICMPIntrinsic()

static SDValue lowerICMPIntrinsic ( const SITargetLowering &  TLI, SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 5272 of file SIISelLowering.cpp.

References llvm::EVT::bitsEq(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getContext(), llvm::getICmpCondCode(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SITargetLowering::getSubtarget(), llvm::SelectionDAG::getUNDEF(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::CmpInst::isIntPredicate(), llvm::CmpInst::isSigned(), llvm::TargetLoweringBase::isTypeLegal(), LHS, N, RHS, llvm::AMDGPUISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

lowerWaveReduce()

static MachineBasicBlock * lowerWaveReduce ( MachineInstr &  MI, MachineBasicBlock &  BB, const GCNSubtarget &  ST, unsigned  Opc  )

static

Definition at line 4176 of file SIISelLowering.cpp.

References Accumulator, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MI, MRI, splitBlockForLoop(), TII, and TRI.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().

mayTailCallThisCC()

static bool mayTailCallThisCC ( CallingConv::ID  CC )

static

Return true if we might ever do TCO for calls with this calling convention.

Definition at line 3089 of file SIISelLowering.cpp.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, canGuaranteeTCO(), and CC.

memVTFromLoadIntrData()

static EVT memVTFromLoadIntrData ( Type *  Ty, unsigned  MaxNumLanes  )

static

Definition at line 982 of file SIISelLowering.cpp.

References assert(), llvm::Type::getContext(), llvm::EVT::getEVT(), and llvm::EVT::getVectorVT().

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic(), and memVTFromLoadIntrReturn().

memVTFromLoadIntrReturn()

static EVT memVTFromLoadIntrReturn ( Type *  Ty, unsigned  MaxNumLanes  )

static

Definition at line 996 of file SIISelLowering.cpp.

References assert(), and memVTFromLoadIntrData().

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic().

minMaxOpcToMin3Max3Opc()

static unsigned minMaxOpcToMin3Max3Opc ( unsigned  Opc )

static

Definition at line 11784 of file SIISelLowering.cpp.

References llvm::AMDGPUISD::FMAX3, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMIN3, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm_unreachable, llvm::ISD::SMAX, llvm::AMDGPUISD::SMAX3, llvm::ISD::SMIN, llvm::AMDGPUISD::SMIN3, llvm::ISD::UMAX, llvm::AMDGPUISD::UMAX3, llvm::ISD::UMIN, and llvm::AMDGPUISD::UMIN3.

packImage16bitOpsToDwords()

static void packImage16bitOpsToDwords ( SelectionDAG &  DAG, SDValue  Op, MVT  PackVectorVT, SmallVectorImpl< SDValue > &  PackedAddrs, unsigned  DimIdx, unsigned  EndIdx, unsigned  NumGradients  )

static

Definition at line 6779 of file SIISelLowering.cpp.

References Addr, llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), I, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

padEltsToUndef()

static SDValue padEltsToUndef ( SelectionDAG &  DAG, const SDLoc &  DL, EVT  CastVT, SDValue  Src, int  ExtraElts  )

static

Definition at line 6667 of file SIISelLowering.cpp.

References DL, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBuildVector(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::isVector(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by constructRetValue().

parseTexFail()

static bool parseTexFail ( SDValue  TexFailCtrl, SelectionDAG &  DAG, SDValue *  TFE, SDValue *  LWE, bool &  IsTexFail  )

static

Definition at line 6761 of file SIISelLowering.cpp.

References DL, llvm::SDValue::getNode(), and llvm::SelectionDAG::getTargetConstant().

processPSInputArgs()

static void processPSInputArgs ( SmallVectorImpl< ISD::InputArg > &  Splits, CallingConv::ID  CallConv, ArrayRef< ISD::InputArg >  Ins, BitVector &  Skipped, FunctionType *  FType, SIMachineFunctionInfo *  Info  )

static

Definition at line 1939 of file SIISelLowering.cpp.

References llvm::CallingConv::AMDGPU_PS, assert(), E, llvm::ISD::InputArg::Flags, llvm::ISD::InputArg::getOrigArgIndex(), llvm::MVT::getScalarSizeInBits(), I, Info, llvm::ISD::ArgFlagsTy::isInReg(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::BitVector::set(), llvm::ISD::InputArg::Used, and llvm::ISD::InputArg::VT.

Referenced by llvm::SITargetLowering::LowerFormalArguments().

reservePrivateMemoryRegs()

static void reservePrivateMemoryRegs ( const TargetMachine &  TM, MachineFunction &  MF, const SIRegisterInfo &  TRI, SIMachineFunctionInfo &  Info  )

static

Definition at line 2332 of file SIISelLowering.cpp.

References assert(), llvm::Function::getCallingConv(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFrameInfo::hasCalls(), llvm::MachineFrameInfo::hasStackObjects(), Info, llvm::AMDGPU::isShader(), MRI, llvm::None, llvm::AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER, llvm::report_fatal_error(), TM, and TRI.

Referenced by llvm::SITargetLowering::finalizeLowering().

setM0ToIndexFromSGPR()

static void setM0ToIndexFromSGPR ( const SIInstrInfo *  TII, MachineRegisterInfo &  MRI, MachineInstr &  MI, int  Offset  )

static

Definition at line 3947 of file SIISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), DL, I, Idx, MBB, MI, llvm::Offset, and TII.

Referenced by emitIndirectDst(), and emitIndirectSrc().

splitBlockForLoop()

static std::pair< MachineBasicBlock *, MachineBasicBlock * > splitBlockForLoop ( MachineInstr &  MI, MachineBasicBlock &  MBB, bool  InstInLoop  )

static

Returns

{ LoopBody, Remainder }

Definition at line 3690 of file SIISelLowering.cpp.

References llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getParent(), I, llvm::MachineFunction::insert(), MBB, MBBI, MI, llvm::MachineBasicBlock::splice(), and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by llvm::SITargetLowering::emitGWSMemViolTestLoop(), loadM0FromVGPR(), and lowerWaveReduce().

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

strictFPExtFromF16()

static SDValue strictFPExtFromF16 ( SelectionDAG &  DAG, SDValue  Src  )

static

Return the source of an fp_extend from f16 to f32, or a converted FP constant.

Definition at line 12256 of file SIISelLowering.cpp.

References llvm::APFloat::convert(), llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstantFP(), llvm::APFloatBase::IEEEhalf(), and llvm::APFloatBase::rmNearestTiesToEven.

SubIdx2Lane()

static unsigned SubIdx2Lane ( unsigned  Idx )

static

Helper function for adjustWritemask.

Definition at line 13131 of file SIISelLowering.cpp.

References Idx.

unsafeFPAtomicsDisabled()

bool unsafeFPAtomicsDisabled

(

Function *

F

)

Definition at line 14376 of file SIISelLowering.cpp.

References F.

Referenced by llvm::SITargetLowering::shouldExpandAtomicRMWInIR().

vectorEltWillFoldAway()

static bool vectorEltWillFoldAway ( SDValue  Op )

static

Definition at line 11692 of file SIISelLowering.cpp.

Variable Documentation

DisableLoopAlignment

cl::opt< bool > DisableLoopAlignment("amdgpu-disable-loop-alignment", cl::desc("Do not align and prefetch loops"), cl::init(false)) ( "amdgpu-disable-loop-alignment"  , cl::desc("Do not align and prefetch loops")  , cl::init(false)    )

static

Referenced by llvm::SITargetLowering::getPrefLoopAlignment().

UseDivergentRegisterIndexing

cl::opt< bool > UseDivergentRegisterIndexing("amdgpu-use-divergent-register-indexing", cl::Hidden, cl::desc("Use indirect register addressing for divergent indexes"), cl::init(false)) ( "amdgpu-use-divergent-register-indexing"  , cl::Hidden  , cl::desc("Use indirect register addressing for divergent indexes")  , cl::init(false)    )

static

Referenced by llvm::SITargetLowering::shouldExpandVectorDynExt().